diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/se | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/se')
84 files changed, 17662 insertions, 17121 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini index 20272ec5e..459e4731f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout index 1a3679afb..06eacea30 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:03:02 -gem5 executing on e108600-lin, pid 24162 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:02 +gem5 executing on e108600-lin, pid 17345 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 62408957500 because target called exit() +Exiting @ tick 62552970500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 2d36751f4..38958d98d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062421 # Number of seconds simulated -sim_ticks 62420912500 # Number of ticks simulated -final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062553 # Number of seconds simulated +sim_ticks 62552970500 # Number of ticks simulated +final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 255603 # Simulator instruction rate (inst/s) -host_op_rate 256876 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 176097831 # Simulator tick rate (ticks/s) -host_mem_usage 405340 # Number of bytes of host memory used -host_seconds 354.47 # Real time elapsed on the host +host_inst_rate 185964 # Simulator instruction rate (inst/s) +host_op_rate 186891 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 128391357 # Simulator tick rate (ticks/s) +host_mem_usage 403424 # Number of bytes of host memory used +host_seconds 487.21 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 790882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15143390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15934271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 790882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 790882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 790882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15143390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15934271 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62420817500 # Total gap between requests +system.physmem.totGap 62552869500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -188,28 +188,28 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.476336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.605762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 178 11.56% 28.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 79 5.13% 33.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 72080000 # Total ticks spent queuing -system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 211081250 # Total ticks spent queuing +system.physmem.totMemAccLat 503093750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13553.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32303.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage @@ -217,48 +217,58 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14024 # Number of row buffer hits during reads +system.physmem.readRowHits 14027 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4008014.48 # Average gap between requests -system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4016493.48 # Average gap between requests +system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.524455 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 136599930 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8776800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 736788270 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 212075520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14428808400 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15801654720 # Total energy per rank (pJ) +system.physmem_0.averagePower 252.612376 # Core power per rank (mW) +system.physmem_0.totalIdleTime 62230500750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states +system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 60062510500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states +system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.484088 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 20808241 # Number of BP lookups -system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 136420380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13274400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 827381220 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 248160000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14377425165 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15919954335 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.503567 # Core power per rank (mW) +system.physmem_1.totalIdleTime 62217855000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states +system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 59758396500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 646214750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 203977250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1814551000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 20808248 # Number of BP lookups +system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8965663 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8840828 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.607632 # BTB Hit Percentage system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. @@ -266,7 +276,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 124841825 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 125105941 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.377902 # CPI: cycles per instruction -system.cpu.ipc 0.725741 # IPC: instructions per cycle +system.cpu.cpi 1.380817 # CPI: cycles per instruction +system.cpu.ipc 0.724209 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -432,60 +442,60 @@ system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 110521627 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14584314 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3621.108293 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274912 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.652068 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.108293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2202 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605963 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits -system.cpu.dcache.overall_hits::total 26267147 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26266630 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266630 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26267138 # number of overall hits +system.cpu.dcache.overall_hits::total 26267138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906313 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906313 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses -system.cpu.dcache.overall_misses::total 980613 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 980627 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980627 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980631 # number of overall misses +system.cpu.dcache.overall_misses::total 980631 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11831745500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11831745500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760211000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2760211000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14591956500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14591956500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14591956500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14591956500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -494,28 +504,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27247257 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035990 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035990 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14880.231219 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14880.170523 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,14 +534,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2883 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2883 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30433 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30433 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30433 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30433 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses @@ -542,16 +552,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194 system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889954000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889954000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486142500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12486142500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486312500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12486312500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -562,71 +572,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.568004 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 689.568004 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27835051 # number of overall hits -system.cpu.icache.overall_hits::total 27835051 # number of overall hits +system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27835083 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27835083 # number of overall hits +system.cpu.icache.overall_hits::total 27835083 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses system.cpu.icache.overall_misses::total 801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60780500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27835852 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 71410000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 71410000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71410000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 71410000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71410000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27835884 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27835884 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27835884 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27835884 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 89151.061174 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 89151.061174 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,36 +651,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801 system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 70609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 70609000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 11307.978899 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.572897 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id @@ -680,7 +690,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -709,18 +719,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses system.cpu.l2cache.overall_misses::total 15581 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1081439500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21652500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58471000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1161563000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58471000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182252000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1182252000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69100500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 69100500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49237000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 69100500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1231489000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1300589500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 69100500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1231489000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1300589500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) @@ -749,18 +759,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,18 +799,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 954685000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036812000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036812000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083046000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1144343000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083046000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1144343000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses @@ -813,25 +823,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -871,7 +881,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution @@ -892,9 +902,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21777000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 9dfbe1ac3..afbdccd37 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index e215a7e6c..07887a4ce 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12217 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:52:57 +gem5 executing on e108600-lin, pid 17480 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 58199030500 because target called exit() +Exiting @ tick 58675371500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index a9bdce95d..3b8f7cb56 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058328 # Number of seconds simulated -sim_ticks 58328364500 # Number of ticks simulated -final_tick 58328364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058675 # Number of seconds simulated +sim_ticks 58675371500 # Number of ticks simulated +final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135523 # Simulator instruction rate (inst/s) -host_op_rate 136198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87259482 # Simulator tick rate (ticks/s) -host_mem_usage 492508 # Number of bytes of host memory used -host_seconds 668.45 # Real time elapsed on the host +host_inst_rate 111966 # Simulator instruction rate (inst/s) +host_op_rate 112523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72520515 # Simulator tick rate (ticks/s) +host_mem_usage 490592 # Number of bytes of host memory used +host_seconds 809.09 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 218752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 921408 # Number of bytes read from this memory -system.physmem.bytes_read::total 1184896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory +system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5696 # Number of bytes written to this memory -system.physmem.bytes_written::total 5696 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory +system.physmem.bytes_written::total 6656 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3418 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14397 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18514 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 89 # Number of write requests responded to by this memory -system.physmem.num_writes::total 89 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 766968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3750354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15796911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20314233 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 766968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 766968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 766968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3750354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15796911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20411887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18515 # Number of read requests accepted -system.physmem.writeReqs 89 # Number of write requests accepted -system.physmem.readBursts 18515 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 89 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1179904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue -system.physmem.bytesWritten 4480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1184960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one +system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18533 # Number of read requests accepted +system.physmem.writeReqs 104 # Number of write requests accepted +system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 3247 # Per bank write bursts +system.physmem.perBankRdBursts::0 3245 # Per bank write bursts system.physmem.perBankRdBursts::1 921 # Per bank write bursts -system.physmem.perBankRdBursts::2 949 # Per bank write bursts +system.physmem.perBankRdBursts::2 952 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1061 # Per bank write bursts -system.physmem.perBankRdBursts::5 1117 # Per bank write bursts -system.physmem.perBankRdBursts::6 1095 # Per bank write bursts -system.physmem.perBankRdBursts::7 1097 # Per bank write bursts +system.physmem.perBankRdBursts::4 1065 # Per bank write bursts +system.physmem.perBankRdBursts::5 1118 # Per bank write bursts +system.physmem.perBankRdBursts::6 1097 # Per bank write bursts +system.physmem.perBankRdBursts::7 1096 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts system.physmem.perBankRdBursts::10 932 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 902 # Per bank write bursts -system.physmem.perBankRdBursts::13 896 # Per bank write bursts -system.physmem.perBankRdBursts::14 1399 # Per bank write bursts -system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::13 895 # Per bank write bursts +system.physmem.perBankRdBursts::14 1401 # Per bank write bursts +system.physmem.perBankRdBursts::15 903 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 2 # Per bank write bursts -system.physmem.perBankWrBursts::3 1 # Per bank write bursts -system.physmem.perBankWrBursts::4 2 # Per bank write bursts -system.physmem.perBankWrBursts::5 9 # Per bank write bursts -system.physmem.perBankWrBursts::6 10 # Per bank write bursts -system.physmem.perBankWrBursts::7 8 # Per bank write bursts -system.physmem.perBankWrBursts::8 2 # Per bank write bursts +system.physmem.perBankWrBursts::2 3 # Per bank write bursts +system.physmem.perBankWrBursts::3 3 # Per bank write bursts +system.physmem.perBankWrBursts::4 12 # Per bank write bursts +system.physmem.perBankWrBursts::5 10 # Per bank write bursts +system.physmem.perBankWrBursts::6 15 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 1 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::10 1 # Per bank write bursts system.physmem.perBankWrBursts::11 3 # Per bank write bursts -system.physmem.perBankWrBursts::12 2 # Per bank write bursts -system.physmem.perBankWrBursts::13 9 # Per bank write bursts -system.physmem.perBankWrBursts::14 13 # Per bank write bursts -system.physmem.perBankWrBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::12 5 # Per bank write bursts +system.physmem.perBankWrBursts::13 12 # Per bank write bursts +system.physmem.perBankWrBursts::14 7 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58328356000 # Total gap between requests +system.physmem.totGap 58675363000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18515 # Read request sizes (log2) +system.physmem.readPktSize::6 18533 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 89 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 13470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 477 # What read queue length does an incoming req see +system.physmem.writePktSize::6 104 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -149,20 +149,20 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see @@ -198,102 +198,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.704216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.847183 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.867268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1088 35.02% 35.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 865 27.84% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 3.03% 65.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 72 2.32% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 65 2.09% 70.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 68 2.19% 72.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 56 1.80% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 51 1.64% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 748 24.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4608 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 1496.681558 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7484.705695 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 1 25.00% 25.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 25.00% 50.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.500000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.477704 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 25.00% 25.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3 75.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.physmem.totQLat 204802662 # Total ticks spent queuing -system.physmem.totMemAccLat 550477662 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11108.84 # Average queueing delay per DRAM burst +system.physmem.totQLat 819558662 # Total ticks spent queuing +system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29858.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 20.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.16 # Data bus utilization in percentage system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.38 # Average write queue length when enqueuing -system.physmem.readRowHits 15382 # Number of row buffer hits during reads -system.physmem.writeRowHits 10 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.49 # Row buffer hit rate for writes -system.physmem.avgGap 3135258.87 # Average gap between requests -system.physmem.pageHitRate 83.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 17803800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 9714375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 81876600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 162000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6575109030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29228595750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39722884515 # Total energy per rank (pJ) -system.physmem_0.averagePower 681.036990 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48583441495 # Time in different power states -system.physmem_0.memoryStateTime::REF 1947660000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7795971005 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5609520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3060750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 61760400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 187920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2425538385 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32868570000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39174349935 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.632528 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54671634140 # Time in different power states -system.physmem_1.memoryStateTime::REF 1947660000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1708703360 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28233990 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266525 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835401 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829630 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11747896 # Number of BTB hits +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing +system.physmem.readRowHits 15523 # Number of row buffer hits during reads +system.physmem.writeRowHits 12 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes +system.physmem.avgGap 3148326.61 # Average gap between requests +system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ) +system.physmem_0.averagePower 336.815504 # Core power per rank (mW) +system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states +system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states +system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states +system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ) +system.physmem_1.averagePower 255.006594 # Core power per rank (mW) +system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states +system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states +system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28234010 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.309074 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74550 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27225 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1747 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -323,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,84 +421,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 116656730 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117350744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746133 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134907690 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28233990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11847924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115018036 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674227 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275439 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 555 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116602964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.162155 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.318550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59067374 50.66% 50.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13933709 11.95% 62.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9228635 7.91% 70.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34373246 29.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116602964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242026 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.156450 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8835100 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64368120 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33012562 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9561783 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825399 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097891 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11814 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114395515 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1985251 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825399 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15271601 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50089085 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 110009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35409630 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14897240 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110872720 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412183 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11133547 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1231881 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1645196 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 486344 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129945840 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483153679 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119447461 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 433 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22632921 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21513680 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805319 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347286 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 522469 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 256366 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109667529 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366370 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074686 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18634782 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41671490 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116602964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.869329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54969091 47.14% 47.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31363076 26.90% 74.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22007447 18.87% 92.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7065313 6.06% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197724 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -499,9 +506,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116602964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9783594 48.67% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available @@ -530,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615674 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702930 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615894 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702925 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970691 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued @@ -560,86 +567,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337594 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047205 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337772 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047242 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366370 # Type of FU issued -system.cpu.iq.rate 0.868929 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20102261 # FU busy when requested +system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued +system.cpu.iq.rate 0.863794 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20102375 # FU busy when requested system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340512191 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128311283 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99607990 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes +system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121468392 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288047 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 238 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329408 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602442 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130712 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825399 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8206553 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 706266 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109688634 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805319 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347286 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 180569 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 362078 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435086 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412401 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847487 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100109489 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23802993 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1256881 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12822 # number of nop insts executed -system.cpu.iew.exec_refs 28718621 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621294 # Number of branches executed -system.cpu.iew.exec_stores 4915628 # Number of stores executed -system.cpu.iew.exec_rate 0.858154 # Inst execution rate -system.cpu.iew.wb_sent 99693258 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99608103 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59691284 # num instructions producing a value -system.cpu.iew.wb_consumers 95529167 # num instructions consuming a value -system.cpu.iew.wb_rate 0.853856 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624849 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17363279 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 12823 # number of nop insts executed +system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621332 # Number of branches executed +system.cpu.iew.exec_stores 4915668 # Number of stores executed +system.cpu.iew.exec_rate 0.853083 # Inst execution rate +system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59691499 # num instructions producing a value +system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value +system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823687 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113915056 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.799312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.736114 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77490817 68.03% 68.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18611366 16.34% 84.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7154135 6.28% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469454 3.05% 93.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644903 1.44% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541342 0.48% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703110 0.62% 96.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178773 0.16% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4121156 3.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113915056 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -685,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4121156 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218205084 # The number of ROB reads -system.cpu.rob.rob_writes 219522331 # The number of ROB writes -system.cpu.timesIdled 576 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53766 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218887121 # The number of ROB reads +system.cpu.rob.rob_writes 219522508 # The number of ROB writes +system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.287747 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.287747 # CPI: Total CPI of All Threads -system.cpu.ipc 0.776550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.776550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108097252 # number of integer regfile reads -system.cpu.int_regfile_writes 58691902 # number of integer regfile writes +system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108097860 # number of integer regfile reads +system.cpu.int_regfile_writes 58692141 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 369002875 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686679 # number of cc regfile writes -system.cpu.misc_regfile_reads 28409649 # number of misc regfile reads +system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes +system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470636 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.779483 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249262 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471148 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335545 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 36545500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.779483 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999569 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999569 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 5470621 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61906894 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61906894 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887138 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887138 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353836 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353836 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18240974 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18240974 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18241496 # number of overall hits -system.cpu.dcache.overall_hits::total 18241496 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587451 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587451 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381145 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381145 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits +system.cpu.dcache.overall_hits::total 18241616 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968596 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968596 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968603 # number of overall misses -system.cpu.dcache.overall_misses::total 9968603 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88929958000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88929958000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000514273 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4000514273 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 284000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 284000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92930472273 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92930472273 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92930472273 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92930472273 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474589 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474589 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses +system.cpu.dcache.overall_misses::total 9968629 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -767,474 +774,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209570 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210099 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210099 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408418 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408418 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353376 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353376 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353370 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353370 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9275.662322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9275.662322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10496.042905 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10496.042905 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20285.714286 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20285.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9322.323051 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9322.323051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9322.316504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9322.316504 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 330469 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 108734 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121517 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.719529 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.469699 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470636 # number of writebacks -system.cpu.dcache.writebacks::total 5470636 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338792 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338792 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158657 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158657 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks +system.cpu.dcache.writebacks::total 5470621 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4497449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4497449 # number of demand (read+write) MSHR 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miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285050165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285050165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 217500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 217500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45714667165 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45714667165 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45714884665 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45714884665 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses 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-system.cpu.icache.overall_mshr_hits::cpu.inst 237 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 237 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50842984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50842984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50842984 # number of demand (read+write) MSHR miss cycles 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(read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60405484 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 60405484 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56180.092818 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56180.092818 # average ReadReq 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Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3478 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9594 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 837 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003723 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884583 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180526187 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180526187 # Number of data accesses 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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 89 # number of writebacks -system.cpu.l2cache.writebacks::total 89 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks +system.cpu.l2cache.writebacks::total 104 # number of writebacks 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system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3078 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3078 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3068 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3068 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3419 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4119 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3411 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4111 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3419 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316573 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 320692 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 866631987 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 46500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 46500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32627500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32627500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44309000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44309000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 208942500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 208942500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44309000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 241570000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 285879000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44309000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 241570000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1152510987 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 3411 # number of overall MSHR misses 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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53848500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 589212500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 589212500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53848500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 634858500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 688707000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53848500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.773481 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000587 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000753 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058605 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2737.542327 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95681.818182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95681.818182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63298.571429 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63298.571429 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67882.553606 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67882.553606 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69404.952658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3593.825187 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943139 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 302176 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5457869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13303 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318447 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318574 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5952 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790626 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052683 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223400 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318864 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485560 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305065 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790626 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942652515 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206727492 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18642 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3008 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18174 # Transaction distribution -system.membus.trans_dist::WritebackDirty 89 # Transaction distribution -system.membus.trans_dist::CleanEvict 34 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18190 # Transaction distribution +system.membus.trans_dist::WritebackDirty 104 # Transaction distribution +system.membus.trans_dist::CleanEvict 36 # Transaction distribution system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 340 # Transaction distribution -system.membus.trans_dist::ReadExResp 340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18175 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37156 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1190592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1190592 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 342 # Transaction distribution +system.membus.trans_dist::ReadExResp 342 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18519 # Request fanout histogram +system.membus.snoop_fanout::samples 18537 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18519 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18519 # Request fanout histogram -system.membus.reqLayer0.occupancy 29524488 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 18537 # Request fanout histogram +system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97237655 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index fa42af61f..e54b7db9f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -179,7 +179,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,6 +756,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -767,7 +768,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -775,29 +776,36 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -817,6 +825,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -848,9 +857,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index e1bfb6d2d..9e929c5a5 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:18 -gem5 executing on e108600-lin, pid 18558 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:08:11 +gem5 executing on e108600-lin, pid 17630 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -21,11 +21,11 @@ active arcs : 1905 simplex iterations : 1502 info: Increasing stack size by one page. flow value : 4990014995 +info: Increasing stack size by one page. new implicit arcs : 23867 active arcs : 25772 -info: Increasing stack size by one page. simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 65986743500 because target called exit() +Exiting @ tick 66079350000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1e87ba0e2..dac7009e5 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065554 # Number of seconds simulated -sim_ticks 65553895500 # Number of ticks simulated -final_tick 65553895500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066079 # Number of seconds simulated +sim_ticks 66079350000 # Number of ticks simulated +final_tick 66079350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122580 # Simulator instruction rate (inst/s) -host_op_rate 215844 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50862026 # Simulator tick rate (ticks/s) -host_mem_usage 417260 # Number of bytes of host memory used -host_seconds 1288.86 # Real time elapsed on the host +host_inst_rate 104457 # Simulator instruction rate (inst/s) +host_op_rate 183932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43689609 # Simulator tick rate (ticks/s) +host_mem_usage 414668 # Number of bytes of host memory used +host_seconds 1512.47 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1890944 # Number of bytes read from this memory -system.physmem.bytes_read::total 1960576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory -system.physmem.bytes_written::total 17920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29546 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30634 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory -system.physmem.num_writes::total 280 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1062210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28845639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29907849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1062210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1062210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 273363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 273363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 273363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1062210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28845639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30181212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30634 # Number of read requests accepted -system.physmem.writeReqs 280 # Number of write requests accepted -system.physmem.readBursts 30634 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1951616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.physmem.bytesWritten 16000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1960576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 69696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1892800 # Number of bytes read from this memory +system.physmem.bytes_read::total 1962496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19520 # Number of bytes written to this memory +system.physmem.bytes_written::total 19520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29575 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30664 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 305 # Number of write requests responded to by this memory +system.physmem.num_writes::total 305 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1054732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28644350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29699081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1054732 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1054732 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 295402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 295402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 295402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1054732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28644350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29994484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30664 # Number of read requests accepted +system.physmem.writeReqs 305 # Number of write requests accepted +system.physmem.readBursts 30664 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 305 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.bytesWritten 18368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1962496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1938 # Per bank write bursts -system.physmem.perBankRdBursts::1 2083 # Per bank write bursts +system.physmem.perBankRdBursts::0 1940 # Per bank write bursts +system.physmem.perBankRdBursts::1 2080 # Per bank write bursts system.physmem.perBankRdBursts::2 2040 # Per bank write bursts -system.physmem.perBankRdBursts::3 1941 # Per bank write bursts -system.physmem.perBankRdBursts::4 2041 # Per bank write bursts -system.physmem.perBankRdBursts::5 1918 # Per bank write bursts -system.physmem.perBankRdBursts::6 1976 # Per bank write bursts +system.physmem.perBankRdBursts::3 1947 # Per bank write bursts +system.physmem.perBankRdBursts::4 2062 # Per bank write bursts +system.physmem.perBankRdBursts::5 1911 # Per bank write bursts +system.physmem.perBankRdBursts::6 1975 # Per bank write bursts system.physmem.perBankRdBursts::7 1870 # Per bank write bursts system.physmem.perBankRdBursts::8 1951 # Per bank write bursts -system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::9 1941 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1799 # Per bank write bursts -system.physmem.perBankRdBursts::14 1827 # Per bank write bursts +system.physmem.perBankRdBursts::14 1826 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 10 # Per bank write bursts -system.physmem.perBankWrBursts::1 107 # Per bank write bursts -system.physmem.perBankWrBursts::2 31 # Per bank write bursts -system.physmem.perBankWrBursts::3 25 # Per bank write bursts -system.physmem.perBankWrBursts::4 39 # Per bank write bursts -system.physmem.perBankWrBursts::5 13 # Per bank write bursts -system.physmem.perBankWrBursts::6 16 # Per bank write bursts +system.physmem.perBankWrBursts::0 26 # Per bank write bursts +system.physmem.perBankWrBursts::1 125 # Per bank write bursts +system.physmem.perBankWrBursts::2 27 # Per bank write bursts +system.physmem.perBankWrBursts::3 24 # Per bank write bursts +system.physmem.perBankWrBursts::4 54 # Per bank write bursts +system.physmem.perBankWrBursts::5 3 # Per bank write bursts +system.physmem.perBankWrBursts::6 18 # Per bank write bursts system.physmem.perBankWrBursts::7 1 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 5 # Per bank write bursts +system.physmem.perBankWrBursts::9 6 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts @@ -83,28 +83,28 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65553697500 # Total gap between requests +system.physmem.totGap 66079146500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30634 # Read request sizes (log2) +system.physmem.readPktSize::6 30664 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 280 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 305 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -147,24 +147,24 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,335 +194,347 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2859 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 687.860091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 477.665686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.129385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 441 15.42% 15.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 263 9.20% 24.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 134 4.69% 29.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 136 4.76% 34.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 118 4.13% 38.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 116 4.06% 42.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 85 2.97% 45.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 96 3.36% 48.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1470 51.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2859 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2173.928571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.222071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 8074.812153 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.857143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.849200 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.534522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 13 92.86% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads -system.physmem.totQLat 136299000 # Total ticks spent queuing -system.physmem.totMemAccLat 708061500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4469.70 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 685.122783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 477.283945 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 398.354531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 431 14.99% 14.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 281 9.77% 24.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 140 4.87% 29.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 134 4.66% 34.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 130 4.52% 38.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 125 4.35% 43.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 77 2.68% 45.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 84 2.92% 48.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1473 51.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2875 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1904.687500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.337942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7552.888425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 15 93.75% 93.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 6.25% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.937500 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.900644 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.181454 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3 18.75% 18.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 10 62.50% 81.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 6.25% 87.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 12.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads +system.physmem.totQLat 407578000 # Total ticks spent queuing +system.physmem.totMemAccLat 979678000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13357.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23219.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32107.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.28 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.62 # Average write queue length when enqueuing -system.physmem.readRowHits 27721 # Number of row buffer hits during reads -system.physmem.writeRowHits 161 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.50 # Row buffer hit rate for writes -system.physmem.avgGap 2120518.13 # Average gap between requests -system.physmem.pageHitRate 90.60 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11740680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 6406125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 123169800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1568160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3052855305 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36653676000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 44130982710 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.213820 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 60959756000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2188940000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2404016500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9873360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5387250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114558600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3230070300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36498224250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 44139732240 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.347293 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 60700713000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2188940000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2663059500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40360668 # Number of BP lookups -system.cpu.branchPred.condPredicted 40360668 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1392637 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26664097 # Number of BTB lookups +system.physmem.avgWrQLen 15.50 # Average write queue length when enqueuing +system.physmem.readRowHits 27718 # Number of row buffer hits during reads +system.physmem.writeRowHits 199 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.25 # Row buffer hit rate for writes +system.physmem.avgGap 2133719.09 # Average gap between requests +system.physmem.pageHitRate 90.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11095560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5886045 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 112990500 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1451160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 311007840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 261882510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17017920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 979925760 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 266852640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15064489440 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 17032599375 # Total energy per rank (pJ) +system.physmem_0.averagePower 257.759790 # Core power per rank (mW) +system.physmem_0.totalIdleTime 65460562250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 23034750 # Time in different power states +system.physmem_0.memoryStateTime::REF 131986000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62616842500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 694916500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 463599750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 2148970500 # Time in different power states +system.physmem_1.actEnergy 9481920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5024580 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 104865180 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 381691440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 255809160 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 19980960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1151008410 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 399268320 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14907041175 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17234823375 # Total energy per rank (pJ) +system.physmem_1.averagePower 260.820111 # Core power per rank (mW) +system.physmem_1.totalIdleTime 65463256000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 30077000 # Time in different power states +system.physmem_1.memoryStateTime::REF 162078000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 61901089500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1039749000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 422083750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2524272750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40670761 # Number of BP lookups +system.cpu.branchPred.condPredicted 40670761 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1447235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26704882 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5988252 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 86625 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26664097 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21157452 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5506645 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 511906 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 6058055 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92918 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26704882 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21174798 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5530084 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 547932 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131107792 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 132158701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30523578 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219647427 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40360668 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27145704 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 98945290 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2900833 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 518 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 114030 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29742559 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 352958 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 20 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131040277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.949675 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.407509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30720551 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 221310466 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40670761 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27232853 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99729501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3011659 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 476 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6367 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 115460 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 59 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29905952 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 15 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 132078466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.409240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65532629 50.01% 50.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4015050 3.06% 53.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3611452 2.76% 55.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6110552 4.66% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7743592 5.91% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5553299 4.24% 70.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3377797 2.58% 73.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2818268 2.15% 75.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32277638 24.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66113924 50.06% 50.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4057337 3.07% 53.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3620378 2.74% 55.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6125698 4.64% 60.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7769884 5.88% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5562288 4.21% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3378570 2.56% 73.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2898316 2.19% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32552071 24.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131040277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307843 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.675319 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15257836 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64260169 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40205069 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9866787 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1450416 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 361840570 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1450416 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20789312 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11161609 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17754 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44252475 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53368711 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 352352816 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16475 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 802883 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46797603 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4838735 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 354809982 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 933969547 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 575070468 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 25233 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 132078466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307742 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.674581 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15424627 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64723504 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40539404 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9885102 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1505829 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 364367574 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1505829 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20975204 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11377644 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18396 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44575622 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53625771 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 354569179 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16511 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 791289 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46695905 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5223216 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 357047318 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 939748965 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 578695140 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 22535 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 75597235 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 487 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 488 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64661942 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112312024 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38476139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51587404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9144280 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343861767 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 317818488 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 169830 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65674018 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 101673382 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4270 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131040277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.425350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.164581 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 77834571 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 494 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 495 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64563941 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112883257 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38651230 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51754424 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9024100 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 345545955 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4258 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 318634973 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 172634 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 67357749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 104786759 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3813 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 132078466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.412467 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.166876 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35194225 26.86% 26.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20112862 15.35% 42.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17093441 13.04% 55.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17641161 13.46% 68.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15328111 11.70% 80.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12869587 9.82% 90.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6689257 5.10% 95.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4093724 3.12% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2017909 1.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 36007190 27.26% 27.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20156467 15.26% 42.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17165000 13.00% 55.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17631185 13.35% 68.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15357300 11.63% 80.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12905365 9.77% 90.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6726655 5.09% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4095436 3.10% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2033868 1.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131040277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 132078466 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 366862 8.95% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3538662 86.29% 95.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 195200 4.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 366214 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3544036 86.42% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 190508 4.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181791277 57.20% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11724 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 408 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 305 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101272470 31.86% 89.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34708964 10.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 182328648 57.22% 57.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11540 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 353 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101489755 31.85% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34771062 10.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 317818488 # Type of FU issued -system.cpu.iq.rate 2.424101 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4100724 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012903 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 770927721 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 409562927 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 313648272 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 20086 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 38326 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4607 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321877132 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8740 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57541030 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 318634973 # Type of FU issued +system.cpu.iq.rate 2.411003 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4100758 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012870 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 773602517 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 412934380 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314305089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 19287 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 34996 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4478 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 322693854 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8537 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57471685 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21532639 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67356 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 63407 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7036387 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 22103872 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67270 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 64283 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7211478 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3908 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141249 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3969 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 140998 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1450416 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8045146 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3020269 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343866482 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 122594 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112312024 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38476139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1910 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3213 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3025719 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 63407 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 529775 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1033204 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1562979 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 315414153 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100518036 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2404335 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1505829 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8247421 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3042364 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 345550213 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133191 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112883257 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38651230 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1745 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2963 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3048582 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 64283 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 545574 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1082259 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1627833 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 316133024 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100718075 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2501949 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134824639 # number of memory reference insts executed -system.cpu.iew.exec_branches 32104448 # Number of branches executed -system.cpu.iew.exec_stores 34306603 # Number of stores executed -system.cpu.iew.exec_rate 2.405762 # Inst execution rate -system.cpu.iew.wb_sent 314286106 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 313652879 # cumulative count of insts written-back -system.cpu.iew.wb_producers 237682188 # num instructions producing a value -system.cpu.iew.wb_consumers 343423954 # num instructions consuming a value -system.cpu.iew.wb_rate 2.392328 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 65797430 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 135067596 # number of memory reference insts executed +system.cpu.iew.exec_branches 32155475 # Number of branches executed +system.cpu.iew.exec_stores 34349521 # Number of stores executed +system.cpu.iew.exec_rate 2.392071 # Inst execution rate +system.cpu.iew.wb_sent 314966910 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 314309567 # cumulative count of insts written-back +system.cpu.iew.wb_producers 238188610 # num instructions producing a value +system.cpu.iew.wb_consumers 344086280 # num instructions consuming a value +system.cpu.iew.wb_rate 2.378274 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692235 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 67483313 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1399141 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121633848 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.287130 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.051606 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1453904 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122408865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.272650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.045643 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 56556051 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16464352 13.54% 60.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11233282 9.24% 69.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8748892 7.19% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2045691 1.68% 78.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1756798 1.44% 79.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 927336 0.76% 80.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727466 0.60% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23173980 19.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57244612 46.77% 46.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16526306 13.50% 60.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11253907 9.19% 69.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8747083 7.15% 76.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2074138 1.69% 78.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1764583 1.44% 79.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 930878 0.76% 80.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726504 0.59% 81.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23140854 18.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121633848 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122408865 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,466 +580,466 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23173980 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 442449762 # The number of ROB reads -system.cpu.rob.rob_writes 697455131 # The number of ROB writes -system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 67515 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23140854 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 444943788 # The number of ROB reads +system.cpu.rob.rob_writes 701094607 # The number of ROB writes +system.cpu.timesIdled 892 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80235 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.829856 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829856 # CPI: Total CPI of All Threads -system.cpu.ipc 1.205028 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.205028 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 502814986 # number of integer regfile reads -system.cpu.int_regfile_writes 247784196 # number of integer regfile writes -system.cpu.fp_regfile_reads 4396 # number of floating regfile reads -system.cpu.fp_regfile_writes 732 # number of floating regfile writes -system.cpu.cc_regfile_reads 109093589 # number of cc regfile reads -system.cpu.cc_regfile_writes 65488596 # number of cc regfile writes -system.cpu.misc_regfile_reads 201890594 # number of misc regfile reads +system.cpu.cpi 0.836508 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.836508 # CPI: Total CPI of All Threads +system.cpu.ipc 1.195446 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.195446 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 503639899 # number of integer regfile reads +system.cpu.int_regfile_writes 248370602 # number of integer regfile writes +system.cpu.fp_regfile_reads 4288 # number of floating regfile reads +system.cpu.fp_regfile_writes 677 # number of floating regfile writes +system.cpu.cc_regfile_reads 109192725 # number of cc regfile reads +system.cpu.cc_regfile_writes 65564647 # number of cc regfile writes +system.cpu.misc_regfile_reads 202344104 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073601 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.108072 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71473739 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077697 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.400463 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21041764500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.108072 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993190 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993190 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073334 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.317880 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71743454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077430 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.534715 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21320595500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.317880 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992998 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992998 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 507 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3433 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3441 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150601371 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150601371 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40127755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40127755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345984 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345984 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71473739 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71473739 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71473739 # number of overall hits -system.cpu.dcache.overall_hits::total 71473739 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2694330 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2694330 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93768 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93768 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2788098 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2788098 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2788098 # number of overall misses -system.cpu.dcache.overall_misses::total 2788098 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32345718500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32345718500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2982305493 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2982305493 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35328023993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35328023993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35328023993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35328023993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42822085 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42822085 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 151138894 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 151138894 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40397499 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40397499 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345955 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345955 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71743454 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71743454 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71743454 # number of overall hits +system.cpu.dcache.overall_hits::total 71743454 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693481 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693481 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93797 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93797 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2787278 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787278 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787278 # number of overall misses +system.cpu.dcache.overall_misses::total 2787278 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32417345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32417345000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3182155993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3182155993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35599500993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35599500993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35599500993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35599500993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43090980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74261837 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74261837 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74261837 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74261837 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062919 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062919 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002982 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002982 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037544 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037544 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037544 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037544 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12005.106464 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12005.106464 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31805.152003 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31805.152003 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12671.012279 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12671.012279 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 218790 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 393 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43059 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74530732 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74530732 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74530732 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74530732 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062507 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062507 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002983 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002983 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037398 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037398 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037398 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037398 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12035.483079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12035.483079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33925.989029 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33925.989029 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12772.138622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12772.138622 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219409 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 385 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43429 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.081168 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 98.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2067196 # number of writebacks -system.cpu.dcache.writebacks::total 2067196 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698496 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 698496 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11905 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11905 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 710401 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 710401 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 710401 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 710401 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995834 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995834 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81863 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81863 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077697 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077697 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077697 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077697 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24223051500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24223051500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2825101993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2825101993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27048153493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27048153493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27048153493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27048153493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046608 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046608 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.052131 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.250000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2066585 # number of writebacks +system.cpu.dcache.writebacks::total 2066585 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697929 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 697929 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11919 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11919 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 709848 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 709848 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 709848 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 709848 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995552 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995552 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81878 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81878 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077430 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077430 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077430 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077430 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24266554500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24266554500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3024734993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3024734993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27291289493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27291289493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27291289493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27291289493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046310 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046310 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.806718 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.806718 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34510.120482 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34510.120482 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 91 # number of replacements -system.cpu.icache.tags.tagsinuse 875.979350 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29741086 # Total number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027873 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027873 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12160.321806 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12160.321806 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36941.974560 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36941.974560 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 94 # number of replacements +system.cpu.icache.tags.tagsinuse 871.416193 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29904477 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26625.860340 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 26772.136974 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 875.979350 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.427724 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.427724 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1026 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 914 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.500977 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59486235 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59486235 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29741086 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29741086 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29741086 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29741086 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29741086 # number of overall hits -system.cpu.icache.overall_hits::total 29741086 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1473 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1473 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1473 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1473 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1473 # number of overall misses -system.cpu.icache.overall_misses::total 1473 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 110309999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 110309999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 110309999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 110309999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 110309999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 110309999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29742559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29742559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29742559 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29742559 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29742559 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29742559 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74887.983028 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74887.983028 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74887.983028 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74887.983028 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74887.983028 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74887.983028 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1013 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 871.416193 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.425496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.425496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1023 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 905 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.499512 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59813021 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59813021 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 29904477 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29904477 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29904477 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29904477 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29904477 # number of overall hits +system.cpu.icache.overall_hits::total 29904477 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1475 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1475 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1475 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1475 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1475 # number of overall misses +system.cpu.icache.overall_misses::total 1475 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 154630499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 154630499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 154630499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 154630499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 154630499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 154630499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29905952 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29905952 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29905952 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29905952 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29905952 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29905952 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.389241 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20887.316157 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000100 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.637430 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.659209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29987 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id 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rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014736 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74041.757218 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74041.757218 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78090.073529 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78090.073529 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75660.682226 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75660.682226 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74214.973559 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74214.973559 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 2077430 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078547 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353937 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353937 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974933 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974933 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.974933 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014236 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014753 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.974933 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014236 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014753 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80899.937925 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80899.937925 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103924.701561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103924.701561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 151690.311419 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 151690.311419 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103924.701561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82283.431953 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83051.999087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103924.701561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82283.431953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83051.999087 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks -system.cpu.l2cache.writebacks::total 280 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28989 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28989 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1088 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1088 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 557 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 557 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1088 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29546 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30634 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1088 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29546 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30634 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1856506500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1856506500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74082000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74082000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 36573000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36573000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74082000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1893079500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1967161500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74082000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1893079500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1967161500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354004 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354004 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974038 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000279 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000279 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014736 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014736 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64041.757218 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64041.757218 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68090.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68090.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65660.682226 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65660.682226 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4152506 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073696 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.writebacks::writebacks 305 # number of writebacks +system.cpu.l2cache.writebacks::total 305 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28997 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28997 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1089 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1089 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 578 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 578 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1089 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30664 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1089 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30664 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055885500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055885500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 102284000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 102284000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 81897000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 81897000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102284000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2137782500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2240066500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102284000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2137782500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2240066500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353937 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353937 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974933 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000290 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000290 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70899.937925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70899.937925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93924.701561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93924.701561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 141690.311419 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 141690.311419 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4151975 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073430 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 91 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81889 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2066890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 94 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 7138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81927 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81927 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995808 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6231320 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265273152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 663 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 17920 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000168 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012972 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995503 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2328 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6230522 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265216960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265294464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 694 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19520 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2079241 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000169 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013010 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2079127 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 350 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2078889 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 352 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4143540000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079241 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4142666500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116545500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 30966 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 332 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 3116145000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 31027 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 363 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1645 # Transaction distribution -system.membus.trans_dist::WritebackDirty 280 # Transaction distribution -system.membus.trans_dist::CleanEvict 52 # Transaction distribution -system.membus.trans_dist::ReadExReq 28989 # Transaction distribution -system.membus.trans_dist::ReadExResp 28989 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61600 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1978496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1978496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1978496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1667 # Transaction distribution +system.membus.trans_dist::WritebackDirty 305 # Transaction distribution +system.membus.trans_dist::CleanEvict 58 # Transaction distribution +system.membus.trans_dist::ReadExReq 28997 # Transaction distribution +system.membus.trans_dist::ReadExResp 28997 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1667 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61691 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1982016 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30634 # Request fanout histogram +system.membus.snoop_fanout::samples 30664 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30634 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30634 # Request fanout histogram -system.membus.reqLayer0.occupancy 43502500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30664 # Request fanout histogram +system.membus.reqLayer0.occupancy 43847500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161439750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161573250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini index d14e71c27..4a417985d 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout index 48ddcf72a..8606e90c7 100755 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4298 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28069 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second @@ -69,4 +69,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 417309765500 because target called exit() +Exiting @ tick 422342506500 because target called exit() diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index eadbc59cf..ddf2151ed 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417806 # Number of seconds simulated -sim_ticks 417805983500 # Number of ticks simulated -final_tick 417805983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.422343 # Number of seconds simulated +sim_ticks 422342506500 # Number of ticks simulated +final_tick 422342506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243916 # Simulator instruction rate (inst/s) -host_op_rate 243916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 166545939 # Simulator tick rate (ticks/s) -host_mem_usage 257728 # Number of bytes of host memory used -host_seconds 2508.65 # Real time elapsed on the host +host_inst_rate 265332 # Simulator instruction rate (inst/s) +host_op_rate 265332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 183135937 # Simulator tick rate (ticks/s) +host_mem_usage 256400 # Number of bytes of host memory used +host_seconds 2306.17 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 156672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24196352 # Number of bytes read from this memory -system.physmem.bytes_read::total 24353024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24196288 # Number of bytes read from this memory +system.physmem.bytes_read::total 24352960 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 156672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 156672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18839232 # Number of bytes written to this memory -system.physmem.bytes_written::total 18839232 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 18839168 # Number of bytes written to this memory +system.physmem.bytes_written::total 18839168 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 378068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294363 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294363 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 374987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57912890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58287878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 374987 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 374987 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45090862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45090862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45090862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 374987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57912890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 103378740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380516 # Number of read requests accepted -system.physmem.writeReqs 294363 # Number of write requests accepted -system.physmem.readBursts 380516 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294363 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24332224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue -system.physmem.bytesWritten 18837888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24353024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18839232 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 378067 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380515 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294362 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294362 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 370960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57290677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 57661636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 370960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 370960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 44606374 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 44606374 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 44606374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 370960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57290677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102268011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380515 # Number of read requests accepted +system.physmem.writeReqs 294362 # Number of write requests accepted +system.physmem.readBursts 380515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294362 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24331840 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue +system.physmem.bytesWritten 18837824 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24352960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18839168 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23763 # Per bank write bursts -system.physmem.perBankRdBursts::1 23178 # Per bank write bursts +system.physmem.perBankRdBursts::0 23759 # Per bank write bursts +system.physmem.perBankRdBursts::1 23180 # Per bank write bursts system.physmem.perBankRdBursts::2 23498 # Per bank write bursts -system.physmem.perBankRdBursts::3 24610 # Per bank write bursts -system.physmem.perBankRdBursts::4 25501 # Per bank write bursts -system.physmem.perBankRdBursts::5 23627 # Per bank write bursts -system.physmem.perBankRdBursts::6 23703 # Per bank write bursts -system.physmem.perBankRdBursts::7 23985 # Per bank write bursts -system.physmem.perBankRdBursts::8 23235 # Per bank write bursts +system.physmem.perBankRdBursts::3 24625 # Per bank write bursts +system.physmem.perBankRdBursts::4 25498 # Per bank write bursts +system.physmem.perBankRdBursts::5 23629 # Per bank write bursts +system.physmem.perBankRdBursts::6 23701 # Per bank write bursts +system.physmem.perBankRdBursts::7 23987 # Per bank write bursts +system.physmem.perBankRdBursts::8 23227 # Per bank write bursts system.physmem.perBankRdBursts::9 24022 # Per bank write bursts -system.physmem.perBankRdBursts::10 24757 # Per bank write bursts -system.physmem.perBankRdBursts::11 22829 # Per bank write bursts -system.physmem.perBankRdBursts::12 23792 # Per bank write bursts -system.physmem.perBankRdBursts::13 24451 # Per bank write bursts -system.physmem.perBankRdBursts::14 22759 # Per bank write bursts -system.physmem.perBankRdBursts::15 22481 # Per bank write bursts +system.physmem.perBankRdBursts::10 24752 # Per bank write bursts +system.physmem.perBankRdBursts::11 22836 # Per bank write bursts +system.physmem.perBankRdBursts::12 23786 # Per bank write bursts +system.physmem.perBankRdBursts::13 24450 # Per bank write bursts +system.physmem.perBankRdBursts::14 22762 # Per bank write bursts +system.physmem.perBankRdBursts::15 22473 # Per bank write bursts system.physmem.perBankWrBursts::0 17837 # Per bank write bursts system.physmem.perBankWrBursts::1 17476 # Per bank write bursts system.physmem.perBankWrBursts::2 17996 # Per bank write bursts @@ -75,32 +75,32 @@ system.physmem.perBankWrBursts::6 18825 # Pe system.physmem.perBankWrBursts::7 18731 # Per bank write bursts system.physmem.perBankWrBursts::8 18487 # Per bank write bursts system.physmem.perBankWrBursts::9 18977 # Per bank write bursts -system.physmem.perBankWrBursts::10 19289 # Per bank write bursts -system.physmem.perBankWrBursts::11 18103 # Per bank write bursts +system.physmem.perBankWrBursts::10 19288 # Per bank write bursts +system.physmem.perBankWrBursts::11 18104 # Per bank write bursts system.physmem.perBankWrBursts::12 18331 # Per bank write bursts -system.physmem.perBankWrBursts::13 18779 # Per bank write bursts +system.physmem.perBankWrBursts::13 18778 # Per bank write bursts system.physmem.perBankWrBursts::14 17209 # Per bank write bursts system.physmem.perBankWrBursts::15 17155 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417805895500 # Total gap between requests +system.physmem.totGap 422342412500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380516 # Read request sizes (log2) +system.physmem.readPktSize::6 380515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294363 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 379108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1078 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294362 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 379040 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,101 +194,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 138680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.287453 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.207223 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.580337 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47172 34.01% 34.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38791 27.97% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13255 9.56% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8020 5.78% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5116 3.69% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3846 2.77% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3216 2.32% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2646 1.91% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16618 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 138680 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.716228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.015056 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 232.517715 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17502 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 138956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.667780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.031528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.663803 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47467 34.16% 34.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38428 27.65% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13549 9.75% 71.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8124 5.85% 77.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5242 3.77% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3828 2.75% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3157 2.27% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2628 1.89% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16533 11.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 138956 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17561 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.649109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.965863 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 233.199678 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17556 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.812818 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.784450 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.984212 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10318 58.94% 58.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 249 1.42% 60.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 6843 39.09% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 94 0.54% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads -system.physmem.totQLat 4112094750 # Total ticks spent queuing -system.physmem.totMemAccLat 11240676000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1900955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10815.87 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17561 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17561 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.761061 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.733847 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.964147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10711 60.99% 60.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 371 2.11% 63.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6450 36.73% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 26 0.15% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17561 # Writes before turning the bus around for reads +system.physmem.totQLat 8688901500 # Total ticks spent queuing +system.physmem.totMemAccLat 15817370250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1900925000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22854.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29565.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41604.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 57.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 44.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 57.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 44.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.81 # Data bus utilization in percentage +system.physmem.busUtil 0.80 # Data bus utilization in percentage system.physmem.busUtilRead 0.45 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing -system.physmem.readRowHits 314275 # Number of row buffer hits during reads -system.physmem.writeRowHits 221571 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.27 # Row buffer hit rate for writes -system.physmem.avgGap 619082.67 # Average gap between requests -system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 534363480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 291567375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1496445600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 959027040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27288821040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62100331785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 196207614000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 288878170320 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.422544 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 325857976500 # Time in different power states -system.physmem_0.memoryStateTime::REF 13951340000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77993346000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 513853200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280376250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1468724400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 948101760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27288821040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59269027500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 198691214250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288460118400 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.421947 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 330008811500 # Time in different power states -system.physmem_1.memoryStateTime::REF 13951340000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 73843223000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 124433678 # Number of BP lookups -system.cpu.branchPred.condPredicted 87996740 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6213240 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71713362 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67453030 # Number of BTB hits +system.physmem.avgWrQLen 20.60 # Average write queue length when enqueuing +system.physmem.readRowHits 314590 # Number of row buffer hits during reads +system.physmem.writeRowHits 220977 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.07 # Row buffer hit rate for writes +system.physmem.avgGap 625806.50 # Average gap between requests +system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 505526280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 268693590 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1370001780 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 772622640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 11362849680.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8093551410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 616183200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 31552584270 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 13412815680 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 73287717855 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 141246410115 # Total energy per rank (pJ) +system.physmem_0.averagePower 334.435695 # Core power per rank (mW) +system.physmem_0.totalIdleTime 402979630750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 931134000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4824278000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 298856786250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 34929182250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13606935500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 69194190500 # Time in different power states +system.physmem_1.actEnergy 486640980 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 258644430 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1344519120 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 763837380 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 10801683360.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7884425820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 575860800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 29572982250 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 12813870240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 74790220020 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 139297315230 # Total energy per rank (pJ) +system.physmem_1.averagePower 329.820729 # Core power per rank (mW) +system.physmem_1.totalIdleTime 403542198250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 850086750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4586322000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 305319724750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 33369590750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13363845750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 64852936500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 124433445 # Number of BP lookups +system.cpu.branchPred.condPredicted 87996604 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6213149 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71713401 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67452940 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.059221 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15161942 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1121063 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.059045 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15161931 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1121038 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 7034 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 4431 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 2603 # Number of indirect misses. @@ -298,22 +309,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149830726 # DTB read hits -system.cpu.dtb.read_misses 559355 # DTB read misses +system.cpu.dtb.read_hits 149830728 # DTB read hits +system.cpu.dtb.read_misses 559329 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150390081 # DTB read accesses -system.cpu.dtb.write_hits 57603616 # DTB write hits -system.cpu.dtb.write_misses 71398 # DTB write misses +system.cpu.dtb.read_accesses 150390057 # DTB read accesses +system.cpu.dtb.write_hits 57603632 # DTB write hits +system.cpu.dtb.write_misses 71396 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57675014 # DTB write accesses -system.cpu.dtb.data_hits 207434342 # DTB hits -system.cpu.dtb.data_misses 630753 # DTB misses +system.cpu.dtb.write_accesses 57675028 # DTB write accesses +system.cpu.dtb.data_hits 207434360 # DTB hits +system.cpu.dtb.data_misses 630725 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 208065095 # DTB accesses -system.cpu.itb.fetch_hits 227957240 # ITB hits +system.cpu.dtb.data_accesses 208065085 # DTB accesses +system.cpu.itb.fetch_hits 227956774 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 227957288 # ITB accesses +system.cpu.itb.fetch_accesses 227956822 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -327,16 +338,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 417805983500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 835611967 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 422342506500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 844685013 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14840404 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 14840042 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.365599 # CPI: cycles per instruction -system.cpu.ipc 0.732280 # IPC: instructions per cycle +system.cpu.cpi 1.380426 # CPI: cycles per instruction +system.cpu.ipc 0.724414 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction @@ -372,107 +383,107 @@ system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 611901617 # Class of committed instruction -system.cpu.tickCycles 746834854 # Number of cycles that the object actually ticked -system.cpu.idleCycles 88777113 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2535509 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.671717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 203187431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539605 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 80.007494 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1657773500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.671717 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997967 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997967 # Average percentage of cache occupancy +system.cpu.tickCycles 746838140 # Number of cycles that the object actually ticked +system.cpu.idleCycles 97846873 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2535505 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.585414 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 203187430 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539601 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 80.007619 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1692948500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.585414 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997946 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997946 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 827 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3149 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 415624617 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 415624617 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147521260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147521260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666171 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666171 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 203187431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 203187431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 203187431 # number of overall hits -system.cpu.dcache.overall_hits::total 203187431 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1811212 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1811212 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543863 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543863 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3355075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3355075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3355075 # number of overall misses -system.cpu.dcache.overall_misses::total 3355075 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36424837000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36424837000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 48227162000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 48227162000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84651999000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84651999000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84651999000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84651999000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 149332472 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 149332472 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 415624517 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 415624517 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 147521210 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147521210 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666220 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666220 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 203187430 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 203187430 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 203187430 # number of overall hits +system.cpu.dcache.overall_hits::total 203187430 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1811214 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1811214 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543814 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543814 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3355028 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3355028 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3355028 # number of overall misses +system.cpu.dcache.overall_misses::total 3355028 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39457833000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39457833000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 51431912500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 51431912500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90889745500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90889745500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90889745500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90889745500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 149332424 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 149332424 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206542506 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206542506 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206542506 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206542506 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206542458 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206542458 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206542458 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206542458 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012129 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012129 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016244 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016244 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20110.752910 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20110.752910 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31237.980313 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31237.980313 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25231.030305 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25231.030305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25231.030305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25231.030305 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21785.295940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21785.295940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33314.837474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33314.837474 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27090.607142 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27090.607142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27090.607142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27090.607142 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2339290 # number of writebacks -system.cpu.dcache.writebacks::total 2339290 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46416 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 46416 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769054 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769054 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 815470 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 815470 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 815470 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 815470 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764796 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764796 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 2339286 # number of writebacks +system.cpu.dcache.writebacks::total 2339286 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46422 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 46422 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769005 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769005 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 815427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 815427 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 815427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 815427 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764792 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764792 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774809 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 774809 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539605 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539605 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539605 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539605 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33407226500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33407226500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23596131500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23596131500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57003358000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 57003358000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57003358000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 57003358000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2539601 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539601 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539601 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539601 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36307875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36307875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25218661500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25218661500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61526536500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61526536500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61526536500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61526536500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011818 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011818 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -481,70 +492,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012296 system.cpu.dcache.demand_mshr_miss_rate::total 0.012296 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012296 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18929.795002 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18929.795002 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30454.126759 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30454.126759 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22445.757510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22445.757510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.757510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.757510 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states 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system.cpu.icache.tags.replacements 3176 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.932847 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 227952235 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1116.241776 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 227951769 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5005 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45544.902098 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 45544.808991 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.932847 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545377 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545377 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.241776 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545040 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545040 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1592 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 455919485 # Number of tag accesses -system.cpu.icache.tags.data_accesses 455919485 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 227952235 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 227952235 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 227952235 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 227952235 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 227952235 # number of overall hits -system.cpu.icache.overall_hits::total 227952235 # number of overall hits +system.cpu.icache.tags.tag_accesses 455918553 # Number of tag accesses +system.cpu.icache.tags.data_accesses 455918553 # Number of data accesses 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(read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 227957240 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 227957240 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293603500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293603500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293603500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293603500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293603500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293603500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 227956774 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 227956774 # number of ReadReq accesses(hits+misses) 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1761453 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1761449 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1761449 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 5005 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2539605 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544610 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2539601 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544606 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 5005 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2539605 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544610 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2539601 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544606 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265318 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.265318 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.489111 # miss rate for ReadCleanReq accesses @@ -669,52 +680,52 @@ system.cpu.l2cache.demand_miss_rate::total 0.149538 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.489111 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.148869 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.149538 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79796.856988 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 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cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26702568500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26879002500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 378067 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380515 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16033226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16033226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 229744000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 229744000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15192569000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15192569000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229744000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 31225795000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31455539000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229744000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 31225795000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31455539000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265318 # mshr miss rate for ReadExReq accesses @@ -729,90 +740,90 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.149538 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.149538 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69796.856988 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69796.856988 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72072.712418 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72072.712418 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71630.143931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71630.143931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72072.712418 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70629.009861 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70638.297733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72072.712418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70629.009861 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70638.297733 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5083295 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538685 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77658.535877 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77658.535877 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93849.673203 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93849.673203 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88530.141193 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88530.141193 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93849.673203 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82593.283730 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82665.700432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93849.673203 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82593.283730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82665.700432 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5083287 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538681 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2446 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2446 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1766458 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633653 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1766454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633648 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3176 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 250480 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 778152 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 778152 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 5005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761453 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761449 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13186 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614719 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7627905 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614707 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7627893 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 523584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312249280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312772864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348624 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18839232 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2893234 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312248768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312772352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348623 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18839168 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2893229 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.029064 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2890788 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2890783 99.92% 99.92% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2446 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2893234 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4884113500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2893229 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4884105500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7507500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3809407500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3809401500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 726699 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 346183 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 726697 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 346182 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 174058 # Transaction distribution -system.membus.trans_dist::WritebackDirty 294363 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 174057 # Transaction distribution +system.membus.trans_dist::WritebackDirty 294362 # Transaction distribution system.membus.trans_dist::CleanEvict 51820 # Transaction distribution system.membus.trans_dist::ReadExReq 206458 # Transaction distribution system.membus.trans_dist::ReadExResp 206458 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174058 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1107215 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1107215 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43192256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43192256 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 174057 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1107212 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1107212 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43192128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43192128 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 380516 # Request fanout histogram +system.membus.snoop_fanout::samples 380515 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 380516 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 380515 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 380516 # Request fanout histogram -system.membus.reqLayer0.occupancy 2021728500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 380515 # Request fanout histogram +system.membus.reqLayer0.occupancy 2021742500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2014027500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2013933750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index 9fc640f03..2bcdda822 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout index 0165cf685..e03b3777c 100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:21 -gem5 executing on e108600-lin, pid 23072 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:47:38 +gem5 executing on e108600-lin, pid 17428 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second @@ -70,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 366439129500 because target called exit() +Exiting @ tick 368600034500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 3a2939b58..3968e09e7 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366632 # Number of seconds simulated -sim_ticks 366631719500 # Number of ticks simulated -final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.368600 # Number of seconds simulated +sim_ticks 368600034500 # Number of ticks simulated +final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211005 # Simulator instruction rate (inst/s) -host_op_rate 228546 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152712719 # Simulator tick rate (ticks/s) -host_mem_usage 277288 # Number of bytes of host memory used -host_seconds 2400.79 # Real time elapsed on the host +host_inst_rate 189198 # Simulator instruction rate (inst/s) +host_op_rate 204927 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137665575 # Simulator tick rate (ticks/s) +host_mem_usage 274600 # Number of bytes of host memory used +host_seconds 2677.50 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory @@ -26,54 +26,54 @@ system.physmem.num_reads::cpu.data 141459 # Nu system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 144269 # Number of read requests accepted system.physmem.writeReqs 97528 # Number of write requests accepted system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue -system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 9225856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 6240448 # Total number of bytes written to DRAM system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9376 # Per bank write bursts +system.physmem.perBankRdBursts::0 9372 # Per bank write bursts system.physmem.perBankRdBursts::1 8929 # Per bank write bursts -system.physmem.perBankRdBursts::2 8964 # Per bank write bursts -system.physmem.perBankRdBursts::3 8666 # Per bank write bursts -system.physmem.perBankRdBursts::4 9423 # Per bank write bursts -system.physmem.perBankRdBursts::5 9371 # Per bank write bursts +system.physmem.perBankRdBursts::2 8963 # Per bank write bursts +system.physmem.perBankRdBursts::3 8667 # Per bank write bursts +system.physmem.perBankRdBursts::4 9424 # Per bank write bursts +system.physmem.perBankRdBursts::5 9372 # Per bank write bursts system.physmem.perBankRdBursts::6 8974 # Per bank write bursts -system.physmem.perBankRdBursts::7 8126 # Per bank write bursts -system.physmem.perBankRdBursts::8 8634 # Per bank write bursts +system.physmem.perBankRdBursts::7 8127 # Per bank write bursts +system.physmem.perBankRdBursts::8 8635 # Per bank write bursts system.physmem.perBankRdBursts::9 8697 # Per bank write bursts -system.physmem.perBankRdBursts::10 8760 # Per bank write bursts -system.physmem.perBankRdBursts::11 9487 # Per bank write bursts -system.physmem.perBankRdBursts::12 9347 # Per bank write bursts -system.physmem.perBankRdBursts::13 9550 # Per bank write bursts -system.physmem.perBankRdBursts::14 8728 # Per bank write bursts -system.physmem.perBankRdBursts::15 9135 # Per bank write bursts -system.physmem.perBankWrBursts::0 6252 # Per bank write bursts +system.physmem.perBankRdBursts::10 8761 # Per bank write bursts +system.physmem.perBankRdBursts::11 9485 # Per bank write bursts +system.physmem.perBankRdBursts::12 9346 # Per bank write bursts +system.physmem.perBankRdBursts::13 9545 # Per bank write bursts +system.physmem.perBankRdBursts::14 8729 # Per bank write bursts +system.physmem.perBankRdBursts::15 9128 # Per bank write bursts +system.physmem.perBankWrBursts::0 6253 # Per bank write bursts system.physmem.perBankWrBursts::1 6118 # Per bank write bursts system.physmem.perBankWrBursts::2 6042 # Per bank write bursts system.physmem.perBankWrBursts::3 5901 # Per bank write bursts system.physmem.perBankWrBursts::4 6273 # Per bank write bursts system.physmem.perBankWrBursts::5 6263 # Per bank write bursts system.physmem.perBankWrBursts::6 6069 # Per bank write bursts -system.physmem.perBankWrBursts::7 5534 # Per bank write bursts -system.physmem.perBankWrBursts::8 5815 # Per bank write bursts +system.physmem.perBankWrBursts::7 5535 # Per bank write bursts +system.physmem.perBankWrBursts::8 5819 # Per bank write bursts system.physmem.perBankWrBursts::9 5920 # Per bank write bursts system.physmem.perBankWrBursts::10 5985 # Per bank write bursts system.physmem.perBankWrBursts::11 6510 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 6013 # Pe system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366631694000 # Total gap between requests +system.physmem.totGap 368600009000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 97528 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 143801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,32 +145,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -194,106 +194,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 63970 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.763327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.115864 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.210402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22774 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18302 28.61% 64.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7461 11.66% 75.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8049 12.58% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2117 3.31% 91.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1180 1.84% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 776 1.21% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 623 0.97% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2688 4.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63970 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5740 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.113240 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 375.658190 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5737 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads -system.physmem.totQLat 1581653750 # Total ticks spent queuing -system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5740 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5740 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.987282 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.957535 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.009458 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2852 49.69% 49.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 159 2.77% 52.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2701 47.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 19 0.33% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 6 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads +system.physmem.totQLat 3577413000 # Total ticks spent queuing +system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing -system.physmem.readRowHits 110439 # Number of row buffer hits during reads -system.physmem.writeRowHits 67921 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes -system.physmem.avgGap 1516278.92 # Average gap between requests -system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.547573 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.512070 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states -system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132103795 # Number of BP lookups -system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted +system.physmem.avgWrQLen 20.06 # Average write queue length when enqueuing +system.physmem.readRowHits 110541 # Number of row buffer hits during reads +system.physmem.writeRowHits 67141 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes +system.physmem.avgGap 1524419.28 # Average gap between requests +system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ) +system.physmem_0.averagePower 312.209476 # Core power per rank (mW) +system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states +system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states +system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ) +system.physmem_1.averagePower 311.172732 # Core power per rank (mW) +system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states +system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 132103819 # Number of BP lookups +system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits +system.cpu.branchPred.BTBLookups 68601561 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60590477 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 88.322301 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10017121 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3891575 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3883028 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -323,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +363,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,16 +424,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 733263439 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 737200069 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12939783 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.447480 # CPI: cycles per instruction -system.cpu.ipc 0.690856 # IPC: instructions per cycle +system.cpu.cpi 1.455251 # CPI: cycles per instruction +system.cpu.ipc 0.687167 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction @@ -459,61 +469,61 @@ system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked -system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked +system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits -system.cpu.dcache.overall_hits::total 168106740 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 701120 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits +system.cpu.dcache.overall_hits::total 168106742 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 701114 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1512501 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses -system.cpu.dcache.overall_misses::total 1512516 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1512467 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses +system.cpu.dcache.overall_misses::total 1512482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) @@ -522,10 +532,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses @@ -536,14 +546,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -552,14 +562,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks system.cpu.dcache.writebacks::total 1068942 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344732 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 367080 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 367080 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 367080 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 367080 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22320 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22320 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344726 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344726 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 367046 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 367046 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 367046 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 367046 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses @@ -570,16 +580,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses @@ -590,26 +600,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 18175 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency 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Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id @@ -617,180 +627,180 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 57 system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task 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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 18175 # number of writebacks -system.cpu.icache.writebacks::total 18175 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20047 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 20047 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 20047 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 18178 # number of writebacks +system.cpu.icache.writebacks::total 18178 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20050 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 20050 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 20050 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 112761 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average 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107686.756063 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,16 +809,16 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks system.cpu.l2cache.writebacks::total 97528 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 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ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 20050 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58269 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58278 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3490481 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144166592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 112761 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1278244 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006015 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077350 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270559 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7682 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1278244 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249619000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30098453 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) @@ -903,7 +913,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 43291 # Transaction distribution system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution system.membus.trans_dist::CleanEvict 12615 # Transaction distribution @@ -926,9 +936,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 144269 # Request fanout histogram -system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 74b919a26..4329f3215 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 03bbf5323..87601728e 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:27:26 -gem5 executing on e108600-lin, pid 12521 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:00 +gem5 executing on e108600-lin, pid 17328 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -70,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 232864525000 because target called exit() +Exiting @ tick 236034256000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index f10b69af3..48fa8fd80 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233363 # Number of seconds simulated -sim_ticks 233363457000 # Number of ticks simulated -final_tick 233363457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.236034 # Number of seconds simulated +sim_ticks 236034256000 # Number of ticks simulated +final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153279 # Simulator instruction rate (inst/s) -host_op_rate 166055 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70798116 # Simulator tick rate (ticks/s) -host_mem_usage 302508 # Number of bytes of host memory used -host_seconds 3296.18 # Real time elapsed on the host +host_inst_rate 147811 # Simulator instruction rate (inst/s) +host_op_rate 160132 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69053974 # Simulator tick rate (ticks/s) +host_mem_usage 301356 # Number of bytes of host memory used +host_seconds 3418.11 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 641792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10513600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16409344 # Number of bytes read from this memory -system.physmem.bytes_read::total 27564736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 641792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 641792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18651328 # Number of bytes written to this memory -system.physmem.bytes_written::total 18651328 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256396 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430699 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291427 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291427 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2750182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45052469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70316682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 118119333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2750182 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2750182 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 79923945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 79923945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 79923945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2750182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45052469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70316682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 198043278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430699 # Number of read requests accepted -system.physmem.writeReqs 291427 # Number of write requests accepted -system.physmem.readBursts 430699 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291427 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27407296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 157440 # Total number of bytes read from write queue -system.physmem.bytesWritten 18649728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27564736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18651328 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2460 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 637184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10497472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16389440 # Number of bytes read from this memory +system.physmem.bytes_read::total 27524096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 637184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 637184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18641536 # Number of bytes written to this memory +system.physmem.bytes_written::total 18641536 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256085 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430064 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291274 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291274 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2699540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44474358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 69436701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116610599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2699540 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2699540 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78978095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78978095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78978095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2699540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44474358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 69436701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195588695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430064 # Number of read requests accepted +system.physmem.writeReqs 291274 # Number of write requests accepted +system.physmem.readBursts 430064 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291274 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27360896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 163200 # Total number of bytes read from write queue +system.physmem.bytesWritten 18638848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27524096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18641536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2550 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27205 # Per bank write bursts -system.physmem.perBankRdBursts::1 26463 # Per bank write bursts -system.physmem.perBankRdBursts::2 25602 # Per bank write bursts -system.physmem.perBankRdBursts::3 32969 # Per bank write bursts -system.physmem.perBankRdBursts::4 28037 # Per bank write bursts -system.physmem.perBankRdBursts::5 29890 # Per bank write bursts -system.physmem.perBankRdBursts::6 25340 # Per bank write bursts -system.physmem.perBankRdBursts::7 24398 # Per bank write bursts -system.physmem.perBankRdBursts::8 25649 # Per bank write bursts -system.physmem.perBankRdBursts::9 25581 # Per bank write bursts -system.physmem.perBankRdBursts::10 25884 # Per bank write bursts -system.physmem.perBankRdBursts::11 26303 # Per bank write bursts -system.physmem.perBankRdBursts::12 27555 # Per bank write bursts -system.physmem.perBankRdBursts::13 26148 # Per bank write bursts -system.physmem.perBankRdBursts::14 24908 # Per bank write bursts -system.physmem.perBankRdBursts::15 26307 # Per bank write bursts -system.physmem.perBankWrBursts::0 18644 # Per bank write bursts -system.physmem.perBankWrBursts::1 18139 # Per bank write bursts -system.physmem.perBankWrBursts::2 17950 # Per bank write bursts -system.physmem.perBankWrBursts::3 17944 # Per bank write bursts -system.physmem.perBankWrBursts::4 18581 # Per bank write bursts -system.physmem.perBankWrBursts::5 18235 # Per bank write bursts -system.physmem.perBankWrBursts::6 17841 # Per bank write bursts -system.physmem.perBankWrBursts::7 17708 # Per bank write bursts -system.physmem.perBankWrBursts::8 18005 # Per bank write bursts -system.physmem.perBankWrBursts::9 17734 # Per bank write bursts -system.physmem.perBankWrBursts::10 18244 # Per bank write bursts -system.physmem.perBankWrBursts::11 18783 # Per bank write bursts -system.physmem.perBankWrBursts::12 18680 # Per bank write bursts -system.physmem.perBankWrBursts::13 18156 # Per bank write bursts -system.physmem.perBankWrBursts::14 18369 # Per bank write bursts -system.physmem.perBankWrBursts::15 18389 # Per bank write bursts +system.physmem.perBankRdBursts::0 27217 # Per bank write bursts +system.physmem.perBankRdBursts::1 26580 # Per bank write bursts +system.physmem.perBankRdBursts::2 25459 # Per bank write bursts +system.physmem.perBankRdBursts::3 32933 # Per bank write bursts +system.physmem.perBankRdBursts::4 28005 # Per bank write bursts +system.physmem.perBankRdBursts::5 30095 # Per bank write bursts +system.physmem.perBankRdBursts::6 25324 # Per bank write bursts +system.physmem.perBankRdBursts::7 24336 # Per bank write bursts +system.physmem.perBankRdBursts::8 25637 # Per bank write bursts +system.physmem.perBankRdBursts::9 25661 # Per bank write bursts +system.physmem.perBankRdBursts::10 25768 # Per bank write bursts +system.physmem.perBankRdBursts::11 26242 # Per bank write bursts +system.physmem.perBankRdBursts::12 27581 # Per bank write bursts +system.physmem.perBankRdBursts::13 26014 # Per bank write bursts +system.physmem.perBankRdBursts::14 24864 # Per bank write bursts +system.physmem.perBankRdBursts::15 25798 # Per bank write bursts +system.physmem.perBankWrBursts::0 18651 # Per bank write bursts +system.physmem.perBankWrBursts::1 18268 # Per bank write bursts +system.physmem.perBankWrBursts::2 17926 # Per bank write bursts +system.physmem.perBankWrBursts::3 17983 # Per bank write bursts +system.physmem.perBankWrBursts::4 18558 # Per bank write bursts +system.physmem.perBankWrBursts::5 18375 # Per bank write bursts +system.physmem.perBankWrBursts::6 17786 # Per bank write bursts +system.physmem.perBankWrBursts::7 17681 # Per bank write bursts +system.physmem.perBankWrBursts::8 18027 # Per bank write bursts +system.physmem.perBankWrBursts::9 17737 # Per bank write bursts +system.physmem.perBankWrBursts::10 18114 # Per bank write bursts +system.physmem.perBankWrBursts::11 18781 # Per bank write bursts +system.physmem.perBankWrBursts::12 18716 # Per bank write bursts +system.physmem.perBankWrBursts::13 18163 # Per bank write bursts +system.physmem.perBankWrBursts::14 18303 # Per bank write bursts +system.physmem.perBankWrBursts::15 18163 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233363404500 # Total gap between requests +system.physmem.totGap 236034203500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430699 # Read request sizes (log2) +system.physmem.readPktSize::6 430064 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291427 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 330391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291274 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,41 +149,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -198,117 +198,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 328347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 140.266048 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.833830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.808988 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 208753 63.58% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 80037 24.38% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14980 4.56% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7256 2.21% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4857 1.48% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2521 0.77% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1858 0.57% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1524 0.46% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6561 2.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 328347 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 16970 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.230642 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.328941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 16968 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 329061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 139.787432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.478985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.644390 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 210353 63.93% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79320 24.10% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14852 4.51% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7229 2.20% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4899 1.49% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2483 0.75% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1823 0.55% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1564 0.48% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6538 1.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 329061 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17032 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.095820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.258821 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17030 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 16970 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 16970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.171597 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.099419 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.840930 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 9436 55.60% 55.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6694 39.45% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 588 3.46% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 150 0.88% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 55 0.32% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 20 0.12% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 4 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 8 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::94-95 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 16970 # Writes before turning the bus around for reads -system.physmem.totQLat 8687632010 # Total ticks spent queuing -system.physmem.totMemAccLat 16717113260 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2141195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20286.88 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17032 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17032 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.099108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.028520 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.818567 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 10039 58.94% 58.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6203 36.42% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 545 3.20% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 139 0.82% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 59 0.35% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 18 0.11% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 9 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 2 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 3 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 5 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-105 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17032 # Writes before turning the bus around for reads +system.physmem.totQLat 14213030846 # Total ticks spent queuing +system.physmem.totMemAccLat 22228918346 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2137570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33245.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39036.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 117.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 79.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 118.12 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 79.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51995.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 78.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 78.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.54 # Data bus utilization in percentage -system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.52 # Data bus utilization in percentage +system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.52 # Average write queue length when enqueuing -system.physmem.readRowHits 308039 # Number of row buffer hits during reads -system.physmem.writeRowHits 83248 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.57 # Row buffer hit rate for writes -system.physmem.avgGap 323161.62 # Average gap between requests -system.physmem.pageHitRate 54.37 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1261242360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 688177875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1715142000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 939872160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86511761685 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64129665000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 170487912840 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.572857 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 106127593352 # Time in different power states -system.physmem_0.memoryStateTime::REF 7792460000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 119441919148 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1221045840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 666245250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1624857000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 948412800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 81485025165 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 68539083000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169726720815 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.311005 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 113492657633 # Time in different power states -system.physmem_1.memoryStateTime::REF 7792460000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 112077139867 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174594135 # Number of BP lookups -system.cpu.branchPred.condPredicted 131061438 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7233022 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90315091 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79002409 # Number of BTB hits +system.physmem.avgWrQLen 21.65 # Average write queue length when enqueuing +system.physmem.readRowHits 307655 # Number of row buffer hits during reads +system.physmem.writeRowHits 82023 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.16 # Row buffer hit rate for writes +system.physmem.avgGap 327217.20 # Average gap between requests +system.physmem.pageHitRate 54.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1196014260 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 635677680 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1570435860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 758090160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15730481520.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13398551100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 618704160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 46181225010 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17503538880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15597346500 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 113194744170 # Total energy per rank (pJ) +system.physmem_0.averagePower 479.569128 # Core power per rank (mW) +system.physmem_0.totalIdleTime 205028158054 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 920292705 # Time in different power states +system.physmem_0.memoryStateTime::REF 6672444000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 58173065750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 45581110454 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23413245991 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 101274097100 # Time in different power states +system.physmem_1.actEnergy 1153531260 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 613108815 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1482014100 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 762140880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15061753200.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13366111830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 607264320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 42525061470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 17168834400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 17794675410 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 110539948695 # Total energy per rank (pJ) +system.physmem_1.averagePower 468.321620 # Core power per rank (mW) +system.physmem_1.totalIdleTime 205130134268 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 923619714 # Time in different power states +system.physmem_1.memoryStateTime::REF 6390116000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67161872750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 44710479181 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23590386018 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 93257782337 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174591760 # Number of BP lookups +system.cpu.branchPred.condPredicted 131058406 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7233420 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90376052 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79001018 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.474206 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12105110 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104499 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4687937 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4674274 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13663 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53871 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.413664 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12105632 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104483 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4688252 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4674256 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13996 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53921 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -338,7 +345,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -368,7 +375,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -398,7 +405,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -429,233 +436,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233363457000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 466726915 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 472068513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7649319 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727510991 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174594135 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95781793 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 451018276 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14520177 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5415 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13360 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235275678 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36827 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465946604 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.690437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.183518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7651832 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727514898 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174591760 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95780906 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 456008633 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14520873 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 8018 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 72 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 15159 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235276766 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36821 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 470944150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.672513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.189889 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 96241342 20.66% 20.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132050994 28.34% 49.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57360477 12.31% 61.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180293791 38.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 101233581 21.50% 21.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132057346 28.04% 49.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57356975 12.18% 61.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180296248 38.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465946604 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374082 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.558751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32536552 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 120918293 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282902203 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22817634 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6771922 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23855471 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495849 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710960604 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29091371 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6771922 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63349282 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 56784032 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40401553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273510163 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25129652 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682692967 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12844145 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9945202 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2511648 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1805093 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1905777 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827472920 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000392013 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718609980 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 470944150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369844 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.541121 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32549558 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 125926098 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282874913 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22821432 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6772149 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23855969 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495947 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710956468 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29088219 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6772149 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63367796 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61282237 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40473434 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273481495 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25567039 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682687004 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12847672 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 10037372 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2522908 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1816731 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2323927 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827475029 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000364097 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718606364 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 112 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173377246 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545812 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536134 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43839802 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142358029 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67522859 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12902461 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11335768 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664750936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979334 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608926553 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5748894 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120382115 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306467952 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1702 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465946604 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.306859 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.102130 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173379355 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545861 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536327 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43857094 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142358041 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67520451 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12908238 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11335045 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664745436 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979378 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608905066 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5749480 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120376659 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306522000 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1746 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 470944150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.292945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.104492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 149520607 32.09% 32.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100880237 21.65% 53.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145552540 31.24% 84.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63032249 13.53% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6960366 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 605 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 154541552 32.82% 32.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100868277 21.42% 54.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145535828 30.90% 85.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63029448 13.38% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6968436 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 609 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465946604 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 470944150 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71896734 53.12% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44291867 32.73% 85.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19147796 14.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71902487 53.13% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44305814 32.74% 85.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19132145 14.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412590919 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352109 0.06% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133574983 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62408539 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412584657 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352207 0.06% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133573210 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62394989 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608926553 # Type of FU issued -system.cpu.iq.rate 1.304674 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135336427 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222254 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1824884935 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788141663 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594200588 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 96 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued +system.cpu.iq.rate 1.289866 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135340476 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 106 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744262920 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7284479 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26474746 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24624 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29798 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10662639 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24641 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29761 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10660231 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225013 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22508 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 224867 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23122 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6771922 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22843049 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 918168 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669223084 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6772149 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23809987 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 977416 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669217601 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142358029 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67522859 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490792 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256633 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 523882 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29798 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3590923 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3742651 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7333574 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598420503 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129081054 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10506050 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142358041 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67520451 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490836 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256647 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 583506 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29761 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3591077 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742851 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7333928 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598406414 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129080217 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10498652 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492814 # number of nop insts executed -system.cpu.iew.exec_refs 190002009 # number of memory reference insts executed -system.cpu.iew.exec_branches 131263961 # Number of branches executed -system.cpu.iew.exec_stores 60920955 # Number of stores executed -system.cpu.iew.exec_rate 1.282164 # Inst execution rate -system.cpu.iew.wb_sent 595445456 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594200604 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349565575 # num instructions producing a value -system.cpu.iew.wb_consumers 571385188 # num instructions consuming a value -system.cpu.iew.wb_rate 1.273123 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611786 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107116116 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492787 # number of nop insts executed +system.cpu.iew.exec_refs 189993781 # number of memory reference insts executed +system.cpu.iew.exec_branches 131261458 # Number of branches executed +system.cpu.iew.exec_stores 60913564 # Number of stores executed +system.cpu.iew.exec_rate 1.267626 # Inst execution rate +system.cpu.iew.wb_sent 595430710 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594185380 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349559163 # num instructions producing a value +system.cpu.iew.wb_consumers 571371780 # num instructions consuming a value +system.cpu.iew.wb_rate 1.258685 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611789 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107108792 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6744856 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 449285999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.221253 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.890713 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6745133 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 454284606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.207816 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.884395 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 220514428 49.08% 49.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116376748 25.90% 74.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43480691 9.68% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23177999 5.16% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11514242 2.56% 92.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7755129 1.73% 94.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8259802 1.84% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4227193 0.94% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13979767 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 225505384 49.64% 49.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116384460 25.62% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43472433 9.57% 84.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23172184 5.10% 89.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11521266 2.54% 92.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7756423 1.71% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8277792 1.82% 95.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4245082 0.93% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13949582 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 449285999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 454284606 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -701,560 +708,559 @@ system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13979767 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1091107249 # The number of ROB reads -system.cpu.rob.rob_writes 1328306301 # The number of ROB writes -system.cpu.timesIdled 14326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 780311 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13949582 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1096128717 # The number of ROB reads +system.cpu.rob.rob_writes 1328290478 # The number of ROB writes +system.cpu.timesIdled 14613 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1124363 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.923782 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.923782 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082507 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082507 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610129735 # number of integer regfile reads -system.cpu.int_regfile_writes 327331512 # number of integer regfile writes +system.cpu.cpi 0.934354 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.934354 # CPI: Total CPI of All Threads +system.cpu.ipc 1.070258 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.070258 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610109745 # number of integer regfile reads +system.cpu.int_regfile_writes 327329948 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166233884 # number of cc regfile reads -system.cpu.cc_regfile_writes 376536291 # number of cc regfile writes -system.cpu.misc_regfile_reads 217601523 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166188285 # number of cc regfile reads +system.cpu.cc_regfile_writes 376531340 # number of cc regfile writes +system.cpu.misc_regfile_reads 217592371 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817306 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.628303 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168866082 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817818 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.927959 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 501259000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.628303 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817297 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.628265 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168862807 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817809 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.926988 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504720000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.628265 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355259202 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355259202 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114162091 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114162091 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51724043 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51724043 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2789 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2789 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 355255813 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355255813 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114160281 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114160281 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51722579 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51722579 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2790 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2790 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165886134 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165886134 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165888923 # number of overall hits -system.cpu.dcache.overall_hits::total 165888923 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4839586 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4839586 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2515006 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2515006 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 165882860 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165882860 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165885650 # number of overall hits +system.cpu.dcache.overall_hits::total 165885650 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4839703 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4839703 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2516470 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2516470 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7354592 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7354592 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7354602 # number of overall misses -system.cpu.dcache.overall_misses::total 7354602 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58596122500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58596122500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18922626430 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18922626430 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1155000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1155000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 77518748930 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 77518748930 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 77518748930 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 77518748930 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119001677 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119001677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7356173 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7356173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7356185 # number of overall misses +system.cpu.dcache.overall_misses::total 7356185 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63969719500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63969719500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19897650428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19897650428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1356500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1356500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83867369928 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83867369928 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83867369928 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83867369928 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 118999984 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 118999984 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2802 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2802 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173240726 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173240726 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173243525 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173243525 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040668 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040668 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046369 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046369 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003573 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003573 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173239033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173239033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173241835 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173241835 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040670 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046396 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046396 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004283 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004283 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042453 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042453 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042452 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042452 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7523.889180 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7523.889180 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10540.183457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10540.169125 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 907373 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221320 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.099824 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817306 # number of writebacks -system.cpu.dcache.writebacks::total 2817306 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2541564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995189 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1995189 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.042463 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042463 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042462 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042462 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13217.695280 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13217.695280 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7906.969059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7906.969059 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20553.030303 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20553.030303 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11400.951273 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11400.951273 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11400.932675 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11400.932675 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1093581 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221181 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.944281 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817297 # number of writebacks +system.cpu.dcache.writebacks::total 2817297 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541719 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2541719 # number of ReadReq MSHR hits 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-system.cpu.dcache.WriteReq_mshr_misses::total 519817 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817839 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817839 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817848 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817848 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30115234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30115234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603448995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 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latency +system.cpu.icache.demand_avg_miss_latency::total 22622.239699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22622.239699 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 206659 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 2170 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7236 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.559840 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 197.272727 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76619 # number of writebacks +system.cpu.icache.writebacks::total 76619 # number of writebacks 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ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 164027 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 173983 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 164027 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355324 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 529307 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21295211595 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 417500 # number of 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(read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15420241000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 956729500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14463511500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36715452595 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007015 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007015 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129991 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069961 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069961 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060210 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006871 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006871 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129089 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069885 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069885 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060099 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.183259 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15400 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15400 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788969 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893984 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23717 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99826 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99825 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.182839 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59931.813204 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15462.962963 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15462.962963 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128569.417340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128569.417340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96095.771394 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96095.771394 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87274.576166 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87274.576166 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88630.734037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69365.137047 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788910 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893955 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23897 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99240 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2645368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 540001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 397627 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2372941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2643074 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 542116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 402261 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295806 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230958 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453003 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683961 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9841856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360648000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370489856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 788066 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18653632 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3683057 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.033555 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.180083 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 522025 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522025 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295784 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230901 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683871 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360646848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370486400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 791889 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18643712 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3686849 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.033410 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179705 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3559472 96.64% 96.64% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 123584 3.36% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3563674 96.66% 96.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 123174 3.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3683057 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788426505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3686849 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788371005 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115796940 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115765939 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226763956 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226743467 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 821136 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 414105 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 819690 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 413483 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 427040 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291427 # Transaction distribution -system.membus.trans_dist::CleanEvict 98976 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34 # Transaction distribution -system.membus.trans_dist::ReadExReq 3658 # Transaction distribution -system.membus.trans_dist::ReadExResp 3658 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 427041 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1251834 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46216000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46216000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426481 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291274 # Transaction distribution +system.membus.trans_dist::CleanEvict 98320 # Transaction distribution +system.membus.trans_dist::UpgradeReq 32 # Transaction distribution +system.membus.trans_dist::ReadExReq 3582 # Transaction distribution +system.membus.trans_dist::ReadExResp 3582 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 426482 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1249753 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1249753 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46165568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46165568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430733 # Request fanout histogram +system.membus.snoop_fanout::samples 430096 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430733 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430096 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430733 # Request fanout histogram -system.membus.reqLayer0.occupancy 2217216132 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2280002282 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430096 # Request fanout histogram +system.membus.reqLayer0.occupancy 2210866206 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2276438586 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index fb202712b..246d6b579 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -179,7 +179,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,6 +756,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -767,7 +768,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -775,29 +776,36 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -817,6 +825,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -848,9 +857,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 72c2f65ba..94b6c45b2 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,18 +3,18 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18568 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:09:23 +gem5 executing on e108600-lin, pid 17649 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. - Reading the dictionary files: **info: Increasing stack size by one page. info: Increasing stack size by one page. -*********************************************** +info: Increasing stack size by one page. + Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -46,13 +46,6 @@ Echoing of input sentence turned on. - he ran home so quickly that his mother could hardly believe he had called from school - so many people attended that they spilled over into several neighboring fields - voting in favor of the bill were 36 Republicans and 4 moderate Democrats -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. : Grace may not be possible to fix the problem any program as good as ours should be useful biochemically , I think the experiment has a lot of problems @@ -79,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 481957625500 because target called exit() +Exiting @ tick 487015166000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index bc9a5d8a0..97084638c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.482382 # Number of seconds simulated -sim_ticks 482382057000 # Number of ticks simulated -final_tick 482382057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.487015 # Number of seconds simulated +sim_ticks 487015166000 # Number of ticks simulated +final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90853 # Simulator instruction rate (inst/s) -host_op_rate 168124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53003549 # Simulator tick rate (ticks/s) -host_mem_usage 321140 # Number of bytes of host memory used -host_seconds 9100.94 # Real time elapsed on the host +host_inst_rate 125191 # Simulator instruction rate (inst/s) +host_op_rate 231667 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73737953 # Simulator tick rate (ticks/s) +host_mem_usage 321616 # Number of bytes of host memory used +host_seconds 6604.67 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24650752 # Number of bytes read from this memory -system.physmem.bytes_read::total 24805888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory -system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 321604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 51102133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51423737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 321604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 321604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39204244 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39204244 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39204244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 321604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 51102133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 90627981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387592 # Number of read requests accepted -system.physmem.writeReqs 295491 # Number of write requests accepted -system.physmem.readBursts 387592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24786816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue -system.physmem.bytesWritten 18910464 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24805888 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 154176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24645952 # Number of bytes read from this memory +system.physmem.bytes_read::total 24800128 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 154176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 154176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18907840 # Number of bytes written to this memory +system.physmem.bytes_written::total 18907840 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385093 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387502 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295435 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295435 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 316573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 50606128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50922702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 38823924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 38823924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 38823924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50606128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 89746626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387502 # Number of read requests accepted +system.physmem.writeReqs 295435 # Number of write requests accepted +system.physmem.readBursts 387502 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295435 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24780416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19712 # Total number of bytes read from write queue +system.physmem.bytesWritten 18906304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24800128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18907840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 308 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24694 # Per bank write bursts -system.physmem.perBankRdBursts::1 26457 # Per bank write bursts -system.physmem.perBankRdBursts::2 24696 # Per bank write bursts -system.physmem.perBankRdBursts::3 24495 # Per bank write bursts -system.physmem.perBankRdBursts::4 23285 # Per bank write bursts -system.physmem.perBankRdBursts::5 23614 # Per bank write bursts -system.physmem.perBankRdBursts::6 24693 # Per bank write bursts -system.physmem.perBankRdBursts::7 24448 # Per bank write bursts -system.physmem.perBankRdBursts::8 23844 # Per bank write bursts -system.physmem.perBankRdBursts::9 23582 # Per bank write bursts -system.physmem.perBankRdBursts::10 24812 # Per bank write bursts -system.physmem.perBankRdBursts::11 24004 # Per bank write bursts -system.physmem.perBankRdBursts::12 23312 # Per bank write bursts -system.physmem.perBankRdBursts::13 22998 # Per bank write bursts -system.physmem.perBankRdBursts::14 24024 # Per bank write bursts -system.physmem.perBankRdBursts::15 24336 # Per bank write bursts -system.physmem.perBankWrBursts::0 19003 # Per bank write bursts -system.physmem.perBankWrBursts::1 19960 # Per bank write bursts -system.physmem.perBankWrBursts::2 19024 # Per bank write bursts -system.physmem.perBankWrBursts::3 18975 # Per bank write bursts -system.physmem.perBankWrBursts::4 18152 # Per bank write bursts -system.physmem.perBankWrBursts::5 18441 # Per bank write bursts -system.physmem.perBankWrBursts::6 19161 # Per bank write bursts -system.physmem.perBankWrBursts::7 19119 # Per bank write bursts -system.physmem.perBankWrBursts::8 18726 # Per bank write bursts -system.physmem.perBankWrBursts::9 17970 # Per bank write bursts -system.physmem.perBankWrBursts::10 18928 # Per bank write bursts -system.physmem.perBankWrBursts::11 17785 # Per bank write bursts -system.physmem.perBankWrBursts::12 17418 # Per bank write bursts -system.physmem.perBankWrBursts::13 16994 # Per bank write bursts -system.physmem.perBankWrBursts::14 17838 # Per bank write bursts -system.physmem.perBankWrBursts::15 17982 # Per bank write bursts +system.physmem.perBankRdBursts::0 24677 # Per bank write bursts +system.physmem.perBankRdBursts::1 26454 # Per bank write bursts +system.physmem.perBankRdBursts::2 24704 # Per bank write bursts +system.physmem.perBankRdBursts::3 24551 # Per bank write bursts +system.physmem.perBankRdBursts::4 23256 # Per bank write bursts +system.physmem.perBankRdBursts::5 23627 # Per bank write bursts +system.physmem.perBankRdBursts::6 24680 # Per bank write bursts +system.physmem.perBankRdBursts::7 24455 # Per bank write bursts +system.physmem.perBankRdBursts::8 23806 # Per bank write bursts +system.physmem.perBankRdBursts::9 23529 # Per bank write bursts +system.physmem.perBankRdBursts::10 24814 # Per bank write bursts +system.physmem.perBankRdBursts::11 23994 # Per bank write bursts +system.physmem.perBankRdBursts::12 23307 # Per bank write bursts +system.physmem.perBankRdBursts::13 23001 # Per bank write bursts +system.physmem.perBankRdBursts::14 24016 # Per bank write bursts +system.physmem.perBankRdBursts::15 24323 # Per bank write bursts +system.physmem.perBankWrBursts::0 19004 # Per bank write bursts +system.physmem.perBankWrBursts::1 19961 # Per bank write bursts +system.physmem.perBankWrBursts::2 19032 # Per bank write bursts +system.physmem.perBankWrBursts::3 19001 # Per bank write bursts +system.physmem.perBankWrBursts::4 18129 # Per bank write bursts +system.physmem.perBankWrBursts::5 18443 # Per bank write bursts +system.physmem.perBankWrBursts::6 19167 # Per bank write bursts +system.physmem.perBankWrBursts::7 19127 # Per bank write bursts +system.physmem.perBankWrBursts::8 18708 # Per bank write bursts +system.physmem.perBankWrBursts::9 17947 # Per bank write bursts +system.physmem.perBankWrBursts::10 18897 # Per bank write bursts +system.physmem.perBankWrBursts::11 17782 # Per bank write bursts +system.physmem.perBankWrBursts::12 17420 # Per bank write bursts +system.physmem.perBankWrBursts::13 16998 # Per bank write bursts +system.physmem.perBankWrBursts::14 17822 # Per bank write bursts +system.physmem.perBankWrBursts::15 17973 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 482381969500 # Total gap between requests +system.physmem.totGap 487015078500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387592 # Read request sizes (log2) +system.physmem.readPktSize::6 387502 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295435 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,31 +145,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -194,246 +194,258 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.722669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.940489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.258352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52888 36.16% 36.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40462 27.66% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14063 9.61% 73.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7664 5.24% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5102 3.49% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3857 2.64% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2918 1.99% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2773 1.90% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16553 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146280 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17634 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.962913 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.199318 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 216.461189 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17628 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.501363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.437841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.145824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53058 36.25% 36.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40951 27.98% 64.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13535 9.25% 73.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7606 5.20% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5054 3.45% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3741 2.56% 84.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2872 1.96% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2862 1.96% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16670 11.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146349 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.896002 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.141977 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.215491 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17677 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17634 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.755969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.728033 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.977832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10918 61.92% 61.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 278 1.58% 63.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 6268 35.55% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 161 0.91% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 7 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17633 # Writes before turning the bus around for reads -system.physmem.totQLat 4311135000 # Total ticks spent queuing -system.physmem.totMemAccLat 11572897500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1936470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11131.43 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17683 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17683 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.705932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.678736 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.966667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11382 64.37% 64.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 280 1.58% 65.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5890 33.31% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 116 0.66% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 11 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17683 # Writes before turning the bus around for reads +system.physmem.totQLat 9773520500 # Total ticks spent queuing +system.physmem.totMemAccLat 17033408000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1935970000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25241.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29881.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 51.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 39.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 39.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43991.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 38.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.71 # Data bus utilization in percentage +system.physmem.busUtil 0.70 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.28 # Average write queue length when enqueuing -system.physmem.readRowHits 315765 # Number of row buffer hits during reads -system.physmem.writeRowHits 220723 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes -system.physmem.avgGap 706183.54 # Average gap between requests -system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 566682480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309201750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1531779600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 983877840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 69780771990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 228217880250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 332897011590 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.111043 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 379065618250 # Time in different power states -system.physmem_0.memoryStateTime::REF 16107780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87208649000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 539164080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 294186750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1489098000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 930690000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 67080778605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230586295500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 332427030615 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.136751 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 383030551000 # Time in different power states -system.physmem_1.memoryStateTime::REF 16107780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 83243489000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 297919436 # Number of BP lookups -system.cpu.branchPred.condPredicted 297919436 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23611614 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229854393 # Number of BTB lookups +system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.86 # Average write queue length when enqueuing +system.physmem.readRowHits 316194 # Number of row buffer hits during reads +system.physmem.writeRowHits 220049 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.48 # Row buffer hit rate for writes +system.physmem.avgGap 713118.60 # Average gap between requests +system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 536506740 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 285137325 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1402324560 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 792730080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13527611760.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8827375680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 730358400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 36195677160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 16995876480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 84126324885 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 163425034830 # Total energy per rank (pJ) +system.physmem_0.averagePower 335.564568 # Core power per rank (mW) +system.physmem_0.totalIdleTime 465742918500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1151920500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5744978000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 342106910750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44260034250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14374729750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 79376592750 # Time in different power states +system.physmem_1.actEnergy 508517940 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 270257130 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1362240600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 749315340 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13073392800.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8818641570 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 720149760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 34369694130 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16456043520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 85412982225 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 161745926205 # Total energy per rank (pJ) +system.physmem_1.averagePower 332.116816 # Core power per rank (mW) +system.physmem_1.totalIdleTime 465789870750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1150076250 # Time in different power states +system.physmem_1.memoryStateTime::REF 5552712000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 347563722250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 42854288750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14522378750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 75371988000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 298029097 # Number of BP lookups +system.cpu.branchPred.condPredicted 298029097 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23616389 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229942542 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40311454 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4410387 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229854393 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119921311 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 109933082 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11586406 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40333391 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4390674 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229942542 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119860888 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 110081654 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11613915 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 964764115 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 974030333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229640733 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587519909 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297919436 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160232765 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 710474501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48125197 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1838 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31961 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 395431 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 7638 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 229618225 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587637398 # Number of instructions fetch has processed +system.cpu.fetch.Branches 298029097 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160194279 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 719695482 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48136797 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1337 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 32063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 398708 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 8912 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216406816 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6303131 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 216378015 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6307023 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 964614734 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.081549 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.494827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 973823159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.052791 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.491297 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 473031835 49.04% 49.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36413294 3.77% 52.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36207947 3.75% 56.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33239258 3.45% 60.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28476947 2.95% 62.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 30017172 3.11% 66.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40187194 4.17% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37484755 3.89% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249556332 25.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 482221410 49.52% 49.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36458558 3.74% 53.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36184065 3.72% 56.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33102262 3.40% 60.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28599787 2.94% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29969705 3.08% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40168402 4.12% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37465076 3.85% 74.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249653894 25.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 964614734 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308800 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.645501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165560291 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 381637451 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312327895 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81026499 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24062598 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2744008679 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24062598 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201558349 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 194036216 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351418098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 193526223 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626516746 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 906315 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120859920 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 22304361 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 41770089 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707207684 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6591914084 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4206827635 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2574467 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973823159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305975 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.629967 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165565722 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 390830119 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312240973 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81117947 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24068398 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2744223716 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24068398 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201650614 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 200101577 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12340 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351328141 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 196662089 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2626762649 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 653926 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 121379246 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 22369281 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44360312 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707190257 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6592545635 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4207329612 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2546306 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090246112 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1066 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 982 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 368286677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608256588 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244134978 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253265740 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76368619 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419508786 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 132419 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999186857 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3656712 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889558685 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510180986 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 131867 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 964614734 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.072524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106121 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090228685 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1055 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 956 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 369291247 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608349007 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244126939 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253380233 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76614927 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419683470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 114601 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999301644 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3644555 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889715551 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510079207 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 114049 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973823159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053044 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.105688 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 336173556 34.85% 34.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135262022 14.02% 48.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129832579 13.46% 62.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119015920 12.34% 74.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 98090682 10.17% 84.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67084509 6.95% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45576707 4.72% 96.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22663670 2.35% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10915089 1.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 345234545 35.45% 35.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135418864 13.91% 49.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129821558 13.33% 62.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119307207 12.25% 74.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97554322 10.02% 84.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67238440 6.90% 91.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45741413 4.70% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22594403 2.32% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10912407 1.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 964614734 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11249182 43.29% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11894821 45.77% 89.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2844033 10.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11212757 43.22% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11924633 45.96% 89.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2807188 10.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2910415 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333514799 66.70% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358060 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798571 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333663160 66.71% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 357468 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798486 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued @@ -455,82 +467,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471222917 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186382093 9.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471201648 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186365855 9.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999186857 # Type of FU issued -system.cpu.iq.rate 2.072203 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25988036 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012999 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4991322155 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305635589 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923777377 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1311041 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4133688 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 240317 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021708405 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 556073 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179295064 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued +system.cpu.iq.rate 2.052607 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25944578 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012977 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5000714674 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1300906 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021778795 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 552407 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224173511 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 339017 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 636964 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94976783 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 337750 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 639215 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94968744 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31958 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31938 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 869 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24062598 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 144797851 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6250562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419641205 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1306710 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608256824 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244134978 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 45669 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1454928 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3966770 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 636964 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8731316 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20649413 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29380729 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945668790 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456756594 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53518067 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24068398 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149571445 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6693651 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419798071 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1305719 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608349109 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244126939 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39730 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1462244 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4395107 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 639215 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8704418 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20695714 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29400132 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945833568 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456792637 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53468076 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635598570 # number of memory reference insts executed -system.cpu.iew.exec_branches 185172751 # Number of branches executed -system.cpu.iew.exec_stores 178841976 # Number of stores executed -system.cpu.iew.exec_rate 2.016730 # Inst execution rate -system.cpu.iew.wb_sent 1934534562 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924017694 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1456930726 # num instructions producing a value -system.cpu.iew.wb_consumers 2203703226 # num instructions consuming a value -system.cpu.iew.wb_rate 1.994288 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661128 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889633438 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635592905 # number of memory reference insts executed +system.cpu.iew.exec_branches 185215439 # Number of branches executed +system.cpu.iew.exec_stores 178800268 # Number of stores executed +system.cpu.iew.exec_rate 1.997714 # Inst execution rate +system.cpu.iew.wb_sent 1934717341 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924191844 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1457208218 # num instructions producing a value +system.cpu.iew.wb_consumers 2204046368 # num instructions consuming a value +system.cpu.iew.wb_rate 1.975495 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661151 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889791004 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23642184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 831915086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.839229 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.465352 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23647177 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 841074000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.819201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458814 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 352165945 42.33% 42.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184695932 22.20% 64.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57945588 6.97% 71.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87210863 10.48% 81.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30437769 3.66% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26536432 3.19% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10472867 1.26% 90.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9005135 1.08% 91.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73444555 8.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 361210845 42.95% 42.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184795052 21.97% 64.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57840397 6.88% 71.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87376864 10.39% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30415751 3.62% 85.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26609914 3.16% 88.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10385763 1.23% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9066382 1.08% 91.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73373032 8.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 831915086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 841074000 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,496 +588,495 @@ system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73444555 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3178186489 # The number of ROB reads -system.cpu.rob.rob_writes 4973800859 # The number of ROB writes -system.cpu.timesIdled 2058 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 149381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73373032 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3187574492 # The number of ROB reads +system.cpu.rob.rob_writes 4974168269 # The number of ROB writes +system.cpu.timesIdled 2040 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207174 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.166798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.166798 # CPI: Total CPI of All Threads -system.cpu.ipc 0.857046 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.857046 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928420991 # number of integer regfile reads -system.cpu.int_regfile_writes 1576721018 # number of integer regfile writes -system.cpu.fp_regfile_reads 241306 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.cc_regfile_reads 617864492 # number of cc regfile reads -system.cpu.cc_regfile_writes 419924545 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064270268 # number of misc regfile reads +system.cpu.cpi 1.178005 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178005 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848893 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848893 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928663805 # number of integer regfile reads +system.cpu.int_regfile_writes 1576907134 # number of integer regfile writes +system.cpu.fp_regfile_reads 239166 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.cc_regfile_reads 617952960 # number of cc regfile reads +system.cpu.cc_regfile_writes 419967877 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064297744 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2546182 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.922606 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421485651 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550278 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.270473 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1898151500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.922606 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998028 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998028 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2546002 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.987212 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 420920584 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550098 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.060552 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.987212 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 600 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3453 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 852234240 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 852234240 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 273116230 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 273116230 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366946 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366946 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421483176 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421483176 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421483176 # number of overall hits -system.cpu.dcache.overall_hits::total 421483176 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2567540 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2567540 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791265 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791265 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3358805 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3358805 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3358805 # number of overall misses -system.cpu.dcache.overall_misses::total 3358805 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57574934000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57574934000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24743790498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24743790498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 82318724498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 82318724498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 82318724498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 82318724498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275683770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275683770 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 851091222 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 851091222 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 272551011 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272551011 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366737 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366737 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 420917748 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 420917748 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 420917748 # number of overall hits +system.cpu.dcache.overall_hits::total 420917748 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2561340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2561340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791474 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791474 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3352814 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3352814 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3352814 # number of overall misses +system.cpu.dcache.overall_misses::total 3352814 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63063270500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63063270500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26380612500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26380612500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89443883000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89443883000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89443883000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89443883000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275112351 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275112351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424841981 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424841981 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424841981 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424841981 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009313 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009313 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007906 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007906 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007906 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007906 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22424.162428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22424.162428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31271.180323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31271.180323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24508.336893 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24508.336893 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1268 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 857 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.301050 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 105.666667 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337859 # number of writebacks -system.cpu.dcache.writebacks::total 2337859 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 801102 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 801102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5848 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5848 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 806950 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 806950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 806950 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 806950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766438 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766438 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785417 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785417 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551855 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551855 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551855 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551855 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33894644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33894644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23857134999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23857134999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57751778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 57751778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57751778999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 57751778999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19188.131143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19188.131143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30375.119203 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30375.119203 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4041 # number of replacements -system.cpu.icache.tags.tagsinuse 1081.856161 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216396902 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5745 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 37666.997737 # Average number of references to valid blocks. +system.cpu.dcache.demand_accesses::cpu.data 424270562 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424270562 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424270562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424270562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007903 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007903 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007903 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007903 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24621.202378 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24621.202378 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33330.990658 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33330.990658 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26677.257671 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26677.257671 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10639 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11942 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 928 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.464440 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 918.615385 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2338096 # number of writebacks +system.cpu.dcache.writebacks::total 2338096 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794970 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 794970 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5921 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5921 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 800891 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 800891 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 800891 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 800891 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766370 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1766370 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785553 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 785553 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551923 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551923 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551923 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551923 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37596158000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37596158000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25486712000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25486712000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63082870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63082870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63082870000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63082870000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21284.418327 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21284.418327 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32444.293383 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32444.293383 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 3937 # number of replacements +system.cpu.icache.tags.tagsinuse 1075.833508 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216367909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5646 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 38322.335990 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1081.856161 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.528250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.528250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1704 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1075.833508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.525309 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.525309 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.832031 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432820961 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432820961 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216397172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216397172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216397172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216397172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216397172 # number of overall hits -system.cpu.icache.overall_hits::total 216397172 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses -system.cpu.icache.overall_misses::total 9643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 354601499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 354601499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 354601499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 354601499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 354601499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 354601499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216406815 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216406815 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216406815 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216406815 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216406815 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216406815 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432763508 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432763508 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487015166000 # 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mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002740 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002740 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263783 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263783 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.431720 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100955 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100955 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151012 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71443.366766 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71443.366766 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109409 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551871 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7932 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2949 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78151.838778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78151.838778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 127512.660855 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 127512.660855 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92235.946517 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92235.946517 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109342 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551824 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2956 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4041 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268853 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766192 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649892 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666920 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 620608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312840768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313461376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357696 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19018624 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2915207 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004295 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.065414 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1773620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268382 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1825 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1825 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 783958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 783958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7480 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766140 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16997 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649848 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312844416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313453504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357811 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19029440 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2915314 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004397 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.066180 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2902688 99.57% 99.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12516 0.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2902498 99.56% 99.56% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12813 0.44% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2915207 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896659390 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2915314 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896765876 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10998496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11220998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3826206608 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3826059624 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740700 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353605 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 740486 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353479 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180791 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution -system.membus.trans_dist::CleanEvict 57611 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 206801 # Transaction distribution -system.membus.trans_dist::ReadExResp 206801 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180791 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1128292 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43717312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43717312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43717312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180710 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295435 # Transaction distribution +system.membus.trans_dist::CleanEvict 57541 # Transaction distribution +system.membus.trans_dist::UpgradeReq 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 206792 # Transaction distribution +system.membus.trans_dist::ReadExResp 206792 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180710 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127988 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127988 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1127988 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43707968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43707968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43707968 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387598 # Request fanout histogram +system.membus.snoop_fanout::samples 387510 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387598 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387510 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387598 # Request fanout histogram -system.membus.reqLayer0.occupancy 1995849000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387510 # Request fanout histogram +system.membus.reqLayer0.occupancy 1995365000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2051150500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2050434250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini index 00cf13ff8..63271ea71 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout index 33c16c36c..6a622d0db 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4300 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28070 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second @@ -14,4 +14,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.233333 -Exiting @ tick 233525789500 because target called exit() +Exiting @ tick 233641094500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 6b30c3cf1..e0c918d80 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233534 # Number of seconds simulated -sim_ticks 233533887500 # Number of ticks simulated -final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233641 # Number of seconds simulated +sim_ticks 233641094500 # Number of ticks simulated +final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225573 # Simulator instruction rate (inst/s) -host_op_rate 225573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132138421 # Simulator tick rate (ticks/s) -host_mem_usage 260868 # Number of bytes of host memory used -host_seconds 1767.34 # Real time elapsed on the host +host_inst_rate 295188 # Simulator instruction rate (inst/s) +host_op_rate 295188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172997788 # Simulator tick rate (ticks/s) +host_mem_usage 258004 # Number of bytes of host memory used +host_seconds 1350.54 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1066936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1089671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2156607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1066936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1066936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1066936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1089671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2156607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233533785500 # Total gap between requests +system.physmem.totGap 233641000500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 79 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.totQLat 53440000 # Total ticks spent queuing -system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.298625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 196.524272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.958390 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 522 34.18% 34.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 350 22.92% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 181 11.85% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 6.88% 75.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 64 4.19% 80.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 46 3.01% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 1.96% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 42 2.75% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 12.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation +system.physmem.totQLat 179319500 # Total ticks spent queuing +system.physmem.totMemAccLat 326938250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst +system.physmem.avgQLat 22776.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41526.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,53 +217,63 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6327 # Number of row buffer hits during reads +system.physmem.readRowHits 6337 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29662617.24 # Average gap between requests -system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29676235.30 # Average gap between requests +system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6326040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3347190 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 31444560 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.682165 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 242168160.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 105016230 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 11391840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 673376340 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 320465280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 55494876360 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 56888412000 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.486327 # Core power per rank (mW) +system.physmem_0.totalIdleTime 233381065000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 19761500 # Time in different power states +system.physmem_0.memoryStateTime::REF 102860000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 231069881000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 834517500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 137354250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1476720250 # Time in different power states +system.physmem_1.actEnergy 4641000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2447775 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 24768660 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.481917 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states -system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912940 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 215124000.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84187860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12227040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 535263060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 280836480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 55611059460 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 56770555335 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.981892 # Core power per rank (mW) +system.physmem_1.totalIdleTime 233423818750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23567500 # Time in different power states +system.physmem_1.memoryStateTime::REF 91510000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 231519465750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 731339000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101377500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1173834750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 45912950 # Number of BP lookups +system.cpu.branchPred.condPredicted 26702746 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25186743 # Number of BTB lookups system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 74.689212 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2249876 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 13973 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -275,17 +285,17 @@ system.cpu.dtb.read_misses 116 # DT system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 95338572 # DTB read accesses system.cpu.dtb.write_hits 73578378 # DTB write hits -system.cpu.dtb.write_misses 849 # DTB write misses +system.cpu.dtb.write_misses 847 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73579227 # DTB write accesses +system.cpu.dtb.write_accesses 73579225 # DTB write accesses system.cpu.dtb.data_hits 168916834 # DTB hits -system.cpu.dtb.data_misses 965 # DTB misses +system.cpu.dtb.data_misses 963 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917799 # DTB accesses -system.cpu.itb.fetch_hits 96959232 # ITB hits +system.cpu.dtb.data_accesses 168917797 # DTB accesses +system.cpu.itb.fetch_hits 96959253 # ITB hits system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960471 # ITB accesses +system.cpu.itb.fetch_accesses 96960492 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467067775 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 467282189 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664651 # Number of instructions committed system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.171581 # CPI: cycles per instruction -system.cpu.ipc 0.853548 # IPC: instructions per cycle +system.cpu.cpi 1.172118 # CPI: cycles per instruction +system.cpu.ipc 0.853156 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction @@ -344,18 +354,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 455741730 # Number of cycles that the object actually ticked +system.cpu.idleCycles 11540459 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.586193 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167817015 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40292.200480 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.586193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803610 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -363,41 +373,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits -system.cpu.dcache.overall_hits::total 167817024 # number of overall hits +system.cpu.dcache.tags.tag_accesses 335652183 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 335652183 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 94302219 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94302219 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514796 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514796 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167817015 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167817015 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167817015 # number of overall hits +system.cpu.dcache.overall_hits::total 167817015 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses -system.cpu.dcache.overall_misses::total 6989 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5933 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5933 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6994 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6994 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6994 # number of overall misses +system.cpu.dcache.overall_misses::total 6994 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 94695000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 94695000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 540363000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 540363000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 635058000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 635058000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 635058000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 635058000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94303280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94303280 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167824013 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167824013 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167824013 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167824013 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 167824009 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167824009 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167824009 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167824009 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses @@ -406,14 +416,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 90800.400343 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 90800.400343 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2737 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2737 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2829 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2829 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2829 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2829 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86354000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86354000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 303749000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 303749000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 390103000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 390103000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 390103000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 390103000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -454,139 +464,139 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3193 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 3194 # number of replacements +system.cpu.icache.tags.tagsinuse 1919.615846 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96954081 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5172 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18745.955336 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.615846 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937312 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937312 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits -system.cpu.icache.overall_hits::total 96954061 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses -system.cpu.icache.overall_misses::total 5171 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959232 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959232 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959232 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959232 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959232 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 193923678 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193923678 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 96954081 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96954081 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96954081 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96954081 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 96954081 # number of overall hits +system.cpu.icache.overall_hits::total 96954081 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5172 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5172 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5172 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5172 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5172 # number of overall misses +system.cpu.icache.overall_misses::total 5172 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 373067500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 373067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 373067500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 373067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 373067500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 96959253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 96959253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 96959253 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 96959253 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 96959253 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 96959253 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62260.394508 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62260.394508 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62260.394508 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62260.394508 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72132.153906 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72132.153906 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72132.153906 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72132.153906 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3193 # number of writebacks -system.cpu.icache.writebacks::total 3193 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5171 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5171 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5171 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 316777500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 316777500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 316777500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 316777500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 316777500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 316777500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 3194 # number of writebacks +system.cpu.icache.writebacks::total 3194 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5172 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5172 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5172 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5172 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5172 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5172 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 367895500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 367895500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 367895500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 367895500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 367895500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 367895500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71132.153906 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71132.153906 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 7128.160045 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 7128.397001 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5429 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.689318 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.689572 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.137560 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3717.022485 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104100 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113435 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.217534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.799627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.597374 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104120 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113422 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.217541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7186 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.tag_accesses 114289 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114289 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3193 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3194 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3194 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1276 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1276 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1277 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1277 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1276 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1277 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1276 # number of overall hits +system.cpu.l2cache.demand_hits::total 1464 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1277 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits -system.cpu.l2cache.overall_hits::total 1463 # number of overall hits +system.cpu.l2cache.overall_hits::total 1464 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3895 # number of ReadCleanReq misses @@ -599,58 +609,58 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 237071000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 237071000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 295621500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 295621500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 70008000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 70008000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 295621500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 307079000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 602700500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 295621500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 307079000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 602700500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 298441000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 298441000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 346727500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 346727500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 83414000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 83414000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 346727500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 381855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 728582500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 346727500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 381855000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 728582500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3193 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3194 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3194 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5171 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5171 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5172 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5172 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5171 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5172 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9336 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5171 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9337 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5172 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9336 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9337 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753239 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753239 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753094 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753094 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753239 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753094 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.843295 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.843204 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753094 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.843204 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95135.798534 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95135.798534 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89018.613607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89018.613607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99184.304400 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99184.304400 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 92541.915407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 92541.915407 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -669,79 +679,79 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 267071000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 267071000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307777500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307777500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 75004000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 75004000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307777500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 342075000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 649852500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307777500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 342075000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 649852500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753239 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753094 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843204 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85135.798534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85135.798534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79018.613607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79018.613607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89184.304400 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89184.304400 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 13302 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3965 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3194 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5172 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13535 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13538 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 843712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 843840 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 9336 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9337 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 9336 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 9337 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9336 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9337 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10499000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7758000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) @@ -751,7 +761,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution @@ -772,9 +782,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9215000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41791500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index e7c466732..c2a5884c8 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 02658fe82..ee5bfc401 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4299 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28057 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -14,4 +14,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.050000 -Exiting @ tick 64188759000 because target called exit() +Exiting @ tick 64255452000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 71e9e3432..1a8043b05 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064159 # Number of seconds simulated -sim_ticks 64159445000 # Number of ticks simulated -final_tick 64159445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064255 # Number of seconds simulated +sim_ticks 64255452000 # Number of ticks simulated +final_tick 64255452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 223776 # Simulator instruction rate (inst/s) -host_op_rate 223776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38227708 # Simulator tick rate (ticks/s) -host_mem_usage 261380 # Number of bytes of host memory used -host_seconds 1678.35 # Real time elapsed on the host +host_inst_rate 260947 # Simulator instruction rate (inst/s) +host_op_rate 260947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44644346 # Simulator tick rate (ticks/s) +host_mem_usage 259540 # Number of bytes of host memory used +host_seconds 1439.27 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 220736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory system.physmem.bytes_read::total 476096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220736 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3440429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3980084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7420513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3440429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3440429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3440429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3980084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7420513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3436284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3973141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7409426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3436284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3436284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3436284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3973141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7409426 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7439 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue @@ -43,20 +43,20 @@ system.physmem.servicedByWrQ 0 # Nu system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 524 # Per bank write bursts -system.physmem.perBankRdBursts::1 652 # Per bank write bursts +system.physmem.perBankRdBursts::1 651 # Per bank write bursts system.physmem.perBankRdBursts::2 450 # Per bank write bursts system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts system.physmem.perBankRdBursts::5 454 # Per bank write bursts system.physmem.perBankRdBursts::6 513 # Per bank write bursts -system.physmem.perBankRdBursts::7 523 # Per bank write bursts +system.physmem.perBankRdBursts::7 524 # Per bank write bursts system.physmem.perBankRdBursts::8 438 # Per bank write bursts system.physmem.perBankRdBursts::9 408 # Per bank write bursts system.physmem.perBankRdBursts::10 339 # Per bank write bursts -system.physmem.perBankRdBursts::11 305 # Per bank write bursts +system.physmem.perBankRdBursts::11 306 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 540 # Per bank write bursts -system.physmem.perBankRdBursts::14 453 # Per bank write bursts +system.physmem.perBankRdBursts::14 452 # Per bank write bursts system.physmem.perBankRdBursts::15 380 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64159334500 # Total gap between requests +system.physmem.totGap 64255349500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -188,28 +188,28 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 352.640474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.024877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.175025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 440 32.62% 32.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 302 22.39% 55.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 154 11.42% 66.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 83 6.15% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 53 3.93% 76.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 50 3.71% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 2.67% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 35 2.59% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.644181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.715239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.080632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 429 31.80% 31.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 311 23.05% 54.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 151 11.19% 66.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 87 6.45% 72.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 5.04% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.89% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 38 2.82% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 2.22% 85.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation -system.physmem.totQLat 63577500 # Total ticks spent queuing -system.physmem.totMemAccLat 203058750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 165053250 # Total ticks spent queuing +system.physmem.totMemAccLat 304534500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8546.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 22187.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27296.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 40937.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.42 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.41 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage @@ -217,75 +217,85 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6088 # Number of row buffer hits during reads +system.physmem.readRowHits 6085 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.84 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8624725.70 # Average gap between requests -system.physmem.pageHitRate 81.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5821200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3176250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 8637632.68 # Average gap between requests +system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5454960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2880405 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29716680 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1995176700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36745221000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42972346350 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.779347 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61126318750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2142400000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 890255000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4377240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2388375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25560600 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 128459760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63558420 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 5463840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 397888500 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 152192640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15095921460 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15881536665 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.162475 # Core power per rank (mW) +system.physmem_0.totalIdleTime 64101767750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 8572500 # Time in different power states +system.physmem_0.memoryStateTime::REF 54520000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62832935750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 396328750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 90536500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 872558500 # Time in different power states +system.physmem_1.actEnergy 4212600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2239050 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 23397780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1859740425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36864024750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42946625790 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.378459 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61324552000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2142400000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 692021750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 47856205 # Number of BP lookups -system.cpu.branchPred.condPredicted 27886274 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 572784 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 23348714 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19574502 # Number of BTB hits +system.physmem_1.refreshEnergy 172713840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 67790100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 10409760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 394655460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 234464640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 15065735460 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15975618690 # Total energy per rank (pJ) +system.physmem_1.averagePower 248.626662 # Core power per rank (mW) +system.physmem_1.totalIdleTime 64079571000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 20607500 # Time in different power states +system.physmem_1.memoryStateTime::REF 73504000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 62603628000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 610590500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 81643000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 865479000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 47858833 # Number of BP lookups +system.cpu.branchPred.condPredicted 27887840 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 573531 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 23350857 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19575248 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.835461 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8687459 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1418 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2338624 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2308001 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 30623 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111239 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 83.830962 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8687752 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1405 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2338807 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2307668 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 31139 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 111329 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 98829712 # DTB read hits -system.cpu.dtb.read_misses 28367 # DTB read misses -system.cpu.dtb.read_acv 845 # DTB read access violations -system.cpu.dtb.read_accesses 98858079 # DTB read accesses -system.cpu.dtb.write_hits 75499203 # DTB write hits -system.cpu.dtb.write_misses 1454 # DTB write misses +system.cpu.dtb.read_hits 98831063 # DTB read hits +system.cpu.dtb.read_misses 28342 # DTB read misses +system.cpu.dtb.read_acv 849 # DTB read access violations +system.cpu.dtb.read_accesses 98859405 # DTB read accesses +system.cpu.dtb.write_hits 75501441 # DTB write hits +system.cpu.dtb.write_misses 1449 # DTB write misses system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 75500657 # DTB write accesses -system.cpu.dtb.data_hits 174328915 # DTB hits -system.cpu.dtb.data_misses 29821 # DTB misses -system.cpu.dtb.data_acv 848 # DTB access violations -system.cpu.dtb.data_accesses 174358736 # DTB accesses -system.cpu.itb.fetch_hits 46955913 # ITB hits -system.cpu.itb.fetch_misses 420 # ITB misses -system.cpu.itb.fetch_acv 7 # ITB acv -system.cpu.itb.fetch_accesses 46956333 # ITB accesses +system.cpu.dtb.write_accesses 75502890 # DTB write accesses +system.cpu.dtb.data_hits 174332504 # DTB hits +system.cpu.dtb.data_misses 29791 # DTB misses +system.cpu.dtb.data_acv 852 # DTB access violations +system.cpu.dtb.data_accesses 174362295 # DTB accesses +system.cpu.itb.fetch_hits 46958874 # ITB hits +system.cpu.itb.fetch_misses 432 # ITB misses +system.cpu.itb.fetch_acv 5 # ITB acv +system.cpu.itb.fetch_accesses 46959306 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,141 +309,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 128318893 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 128510907 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 47425719 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 424811206 # Number of instructions fetch has processed -system.cpu.fetch.Branches 47856205 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 30569962 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 79950349 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1246202 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 47429437 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 424837073 # Number of instructions fetch has processed +system.cpu.fetch.Branches 47858833 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 30570668 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80085665 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1247776 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13187 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 46955913 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 225768 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128012699 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.318508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 297 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13295 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 46958874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 226146 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128152674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.315086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.349633 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53041219 41.43% 41.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4325218 3.38% 44.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6711253 5.24% 50.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5104898 3.99% 54.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10968142 8.57% 62.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7524114 5.88% 68.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5300788 4.14% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1845614 1.44% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33191453 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53168247 41.49% 41.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4330315 3.38% 44.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6713619 5.24% 50.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5107106 3.99% 54.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10970093 8.56% 62.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7524949 5.87% 68.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5303300 4.14% 72.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1847075 1.44% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33187970 25.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128012699 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372947 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.310590 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42125446 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13481218 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67948873 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3838220 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 618942 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 8882912 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4201 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 421902807 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 618942 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43678343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3058028 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 517106 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70134710 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10005570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419884966 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 437260 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2526892 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2765017 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3520699 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 273968908 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 552151473 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 393698766 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 158452706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 128152674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372411 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.305844 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42097840 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13659925 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 67904561 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3870622 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 619726 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 8883416 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4205 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 421920314 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 13831 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 619726 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43662514 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3075430 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 529984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70109441 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10155579 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 419899923 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 443686 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2538434 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2849903 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3565226 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 273976095 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 552171720 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 393714640 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 158457079 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14436589 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37562 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 14443776 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37564 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15635470 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 99735139 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 76519296 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11859955 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9294086 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392181792 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 15805009 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 99734698 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 76520876 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11857010 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9264279 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392184083 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 389203558 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 195886 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16607287 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7664931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 389210637 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 196187 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16609578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7664570 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128012699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.040351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.180919 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 128152674 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.037086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.181467 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17224377 13.46% 13.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19358192 15.12% 28.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22001472 17.19% 45.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17955910 14.03% 59.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19066405 14.89% 74.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13282652 10.38% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8794829 6.87% 91.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6104058 4.77% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4224804 3.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17313559 13.51% 13.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19411245 15.15% 28.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22012922 17.18% 45.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17948678 14.01% 59.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19074074 14.88% 74.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13271943 10.36% 85.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8797733 6.87% 91.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6095055 4.76% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4227465 3.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128012699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128152674 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 256922 1.42% 1.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 1.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138470 0.76% 2.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 78848 0.44% 2.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3339 0.02% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3443164 19.01% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1648895 9.10% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8039924 44.38% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4505956 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 253970 1.40% 1.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 1.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138834 0.77% 2.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 79013 0.44% 2.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3443745 19.00% 21.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1647907 9.09% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8047413 44.40% 75.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4509145 24.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 146986421 37.77% 37.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128250 0.55% 38.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 146989472 37.77% 37.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128309 0.55% 38.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 36418938 9.36% 47.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7355017 1.89% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2800646 0.72% 50.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556809 4.25% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584153 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 36418443 9.36% 47.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7355119 1.89% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2800065 0.72% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556449 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1584163 0.41% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued @@ -455,82 +465,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99502900 25.57% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 75836843 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99502948 25.57% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 75842088 19.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 389203558 # Type of FU issued -system.cpu.iq.rate 3.033096 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18115520 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046545 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 592493180 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 242176639 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 227925873 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332238041 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166682962 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158291544 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 234723560 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172561937 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19352464 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 389210637 # Type of FU issued +system.cpu.iq.rate 3.028619 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18123623 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046565 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 592644502 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 242185048 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 227933309 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 332249256 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 166679024 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158288157 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 234729597 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172571082 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19364531 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4980653 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 92349 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 70589 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2998568 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4980212 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 92962 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 70485 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3000148 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 383293 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3853 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 382479 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3666 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 618942 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1854909 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 149633 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 415904338 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108226 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 99735139 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 76519296 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 619726 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1854972 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162334 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 415907776 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 109026 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 99734698 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 76520876 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7462 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 141873 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 70589 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 411438 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230495 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 641933 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 387616397 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98858950 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1587161 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8920 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 152322 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 70485 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 412161 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230865 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 643026 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 387624331 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98860283 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1586306 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 23722256 # number of nop insts executed -system.cpu.iew.exec_refs 174359643 # number of memory reference insts executed -system.cpu.iew.exec_branches 45862472 # Number of branches executed -system.cpu.iew.exec_stores 75500693 # Number of stores executed -system.cpu.iew.exec_rate 3.020727 # Inst execution rate -system.cpu.iew.wb_sent 386480663 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 386217417 # cumulative count of insts written-back -system.cpu.iew.wb_producers 192328787 # num instructions producing a value -system.cpu.iew.wb_consumers 273868663 # num instructions consuming a value -system.cpu.iew.wb_rate 3.009825 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.702266 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17240745 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 23723403 # number of nop insts executed +system.cpu.iew.exec_refs 174363211 # number of memory reference insts executed +system.cpu.iew.exec_branches 45864022 # Number of branches executed +system.cpu.iew.exec_stores 75502928 # Number of stores executed +system.cpu.iew.exec_rate 3.016276 # Inst execution rate +system.cpu.iew.wb_sent 386484413 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 386221466 # cumulative count of insts written-back +system.cpu.iew.wb_producers 192314001 # num instructions producing a value +system.cpu.iew.wb_consumers 273852153 # num instructions consuming a value +system.cpu.iew.wb_rate 3.005359 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.702255 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17244606 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568625 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125549188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.175366 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.248155 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 569369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125687681 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.171867 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.248348 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42020703 33.47% 33.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17522364 13.96% 47.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 8729636 6.95% 54.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9062074 7.22% 61.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6240745 4.97% 66.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4112376 3.28% 69.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4753795 3.79% 73.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2410879 1.92% 75.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30696616 24.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42136978 33.53% 33.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17569311 13.98% 47.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 8725420 6.94% 54.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9050963 7.20% 61.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6228783 4.96% 66.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4113989 3.27% 69.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4743327 3.77% 73.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2404790 1.91% 75.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30714120 24.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125549188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125687681 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664569 # Number of instructions committed system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,33 +586,33 @@ system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction -system.cpu.commit.bw_lim_events 30696616 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 510754909 # The number of ROB reads -system.cpu.rob.rob_writes 834280363 # The number of ROB writes -system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 306194 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30714120 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 510879759 # The number of ROB reads +system.cpu.rob.rob_writes 834289662 # The number of ROB writes +system.cpu.timesIdled 3136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 358233 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.341660 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.341660 # CPI: Total CPI of All Threads -system.cpu.ipc 2.926886 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.926886 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 385442521 # number of integer regfile reads -system.cpu.int_regfile_writes 165246956 # number of integer regfile writes -system.cpu.fp_regfile_reads 154535424 # number of floating regfile reads -system.cpu.fp_regfile_writes 102076666 # number of floating regfile writes +system.cpu.cpi 0.342171 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.342171 # CPI: Total CPI of All Threads +system.cpu.ipc 2.922513 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.922513 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 385452576 # number of integer regfile reads +system.cpu.int_regfile_writes 165252743 # number of integer regfile writes +system.cpu.fp_regfile_reads 154537274 # number of floating regfile reads +system.cpu.fp_regfile_writes 102070951 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 779 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.925722 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 152589979 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4179 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36513.514956 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 774 # number of replacements +system.cpu.dcache.tags.tagsinuse 3291.451205 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 152580730 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36555.038333 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.925722 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.451205 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803577 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803577 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -610,304 +620,304 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 305227185 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 305227185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 79088959 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79088959 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501014 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501014 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 305207642 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 305207642 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 79079190 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79079190 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501534 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501534 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 152589973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152589973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152589973 # number of overall hits -system.cpu.dcache.overall_hits::total 152589973 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 152580724 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152580724 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152580724 # number of overall hits +system.cpu.dcache.overall_hits::total 152580724 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19714 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19714 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21524 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21524 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21524 # number of overall misses -system.cpu.dcache.overall_misses::total 21524 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128203000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128203000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1194602455 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1194602455 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1322805455 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1322805455 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1322805455 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1322805455 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79090769 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79090769 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 19194 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19194 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21004 # number of overall misses +system.cpu.dcache.overall_misses::total 21004 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 137671000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 137671000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1331646003 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1331646003 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1469317003 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1469317003 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1469317003 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1469317003 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79081000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79081000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 152611497 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 152611497 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 152611497 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 152611497 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 152601728 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 152601728 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 152601728 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 152601728 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000141 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000141 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000141 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70830.386740 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70830.386740 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60596.654915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60596.654915 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61457.231695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61457.231695 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 49869 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 741 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76061.325967 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76061.325967 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69378.243357 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69378.243357 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69954.151733 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69954.151733 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 57813 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 94 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 689 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.299595 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 658 # number of writebacks -system.cpu.dcache.writebacks::total 658 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16524 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16524 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17345 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17345 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17345 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17345 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4179 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4179 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4179 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4179 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 76039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 251163000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 251163000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 327202500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 327202500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 327202500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 327202500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.908563 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 94 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 655 # number of writebacks +system.cpu.dcache.writebacks::total 655 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16830 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16830 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16830 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16830 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 83512000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 83512000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 299984000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 299984000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 383496000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 383496000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 383496000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 383496000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76885.237614 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76885.237614 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78734.482759 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78734.482759 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2131 # number of replacements -system.cpu.icache.tags.tagsinuse 1829.791655 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 46950265 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4058 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11569.804091 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84697.768763 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84697.768763 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94097.867001 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94097.867001 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91877.335889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 91877.335889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91877.335889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 91877.335889 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2132 # number of replacements +system.cpu.icache.tags.tagsinuse 1829.599220 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 46953196 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4059 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11567.675782 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1829.791655 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.893453 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.893453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1829.599220 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.893359 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.893359 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1342 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 93915884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 93915884 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 46950265 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 46950265 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 46950265 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 46950265 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 46950265 # number of overall hits -system.cpu.icache.overall_hits::total 46950265 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5648 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5648 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5648 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5648 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5648 # number of overall misses -system.cpu.icache.overall_misses::total 5648 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 373323999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 373323999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 373323999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 373323999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 373323999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 373323999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 46955913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 46955913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 46955913 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 46955913 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 46955913 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 46955913 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000120 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000120 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000120 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000120 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000120 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000120 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66098.441749 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66098.441749 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66098.441749 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66098.441749 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 575 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 93921805 # Number of tag accesses +system.cpu.icache.tags.data_accesses 93921805 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 46953196 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 46953196 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 46953196 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 46953196 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 46953196 # number of overall hits +system.cpu.icache.overall_hits::total 46953196 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5677 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5677 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5677 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5677 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5677 # number of overall misses +system.cpu.icache.overall_misses::total 5677 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 436957499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 436957499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 436957499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 436957499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 436957499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 436957499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 46958873 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 46958873 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 46958873 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 46958873 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 46958873 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 46958873 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000121 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000121 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000121 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000121 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000121 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000121 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76969.790206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76969.790206 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76969.790206 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76969.790206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76969.790206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76969.790206 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 896 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.888889 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.733333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2131 # number of writebacks -system.cpu.icache.writebacks::total 2131 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1590 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1590 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1590 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1590 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1590 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1590 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4058 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4058 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4058 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4058 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4058 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4058 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 277954000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 277954000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 277954000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 277954000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 277954000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 277954000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 2132 # number of writebacks +system.cpu.icache.writebacks::total 2132 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1618 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1618 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1618 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1618 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1618 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1618 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4059 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4059 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4059 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4059 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4059 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4059 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323146500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 323146500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323146500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 323146500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323146500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 323146500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68495.317891 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68495.317891 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68495.317891 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68495.317891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68495.317891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68495.317891 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79612.342942 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79612.342942 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79612.342942 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79612.342942 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79612.342942 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79612.342942 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6688.615033 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3708 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6685.408988 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3700 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7439 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.498454 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.497379 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2966.248754 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3722.366279 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090523 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113598 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.204120 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2964.630490 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.778498 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090473 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113549 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.204022 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 7439 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6758 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6755 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.227020 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 96615 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 96615 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 658 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 658 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2131 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2131 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 62 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 62 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 96551 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 96551 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2132 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 609 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 127 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 127 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 125 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 125 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 609 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 189 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 798 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 185 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 794 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 609 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 189 # number of overall hits -system.cpu.l2cache.overall_hits::total 798 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 185 # number of overall hits +system.cpu.l2cache.overall_hits::total 794 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 3128 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3128 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3449 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3449 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 862 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 862 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3449 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3990 # number of demand (read+write) misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3450 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3450 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 861 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 861 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3450 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3989 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3449 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3990 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 3450 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses system.cpu.l2cache.overall_misses::total 7439 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 245628000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 245628000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 265369000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 265369000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 73132500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 73132500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 265369000 # 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mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.873225 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903559 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903559 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84140.664962 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84140.664962 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80020.144928 # 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Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4058 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 989 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9137 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 705664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4059 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 986 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10250 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19372 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 705280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 8237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8237 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8233 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8237 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8362500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8233 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8356500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6087499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6088500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6268500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6261000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -1008,7 +1018,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4311 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution @@ -1029,9 +1039,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7439 # Request fanout histogram -system.membus.reqLayer0.occupancy 9245500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9229500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39234750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39165500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini index 76d7daa42..3e9f2ae1c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout index ab196f487..feeb32deb 100755 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23074 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:47:28 +gem5 executing on e108600-lin, pid 17426 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second @@ -16,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.220000 -Exiting @ tick 225030243000 because target called exit() +Exiting @ tick 225206521000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index a1a985a56..c3dd06017 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.225041 # Number of seconds simulated -sim_ticks 225040911000 # Number of ticks simulated -final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225207 # Number of seconds simulated +sim_ticks 225206521000 # Number of ticks simulated +final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161529 # Simulator instruction rate (inst/s) -host_op_rate 193933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133133968 # Simulator tick rate (ticks/s) -host_mem_usage 280148 # Number of bytes of host memory used -host_seconds 1690.33 # Real time elapsed on the host +host_inst_rate 132189 # Simulator instruction rate (inst/s) +host_op_rate 158707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 109031633 # Simulator tick rate (ticks/s) +host_mem_usage 278744 # Number of bytes of host memory used +host_seconds 2065.52 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory system.physmem.bytes_read::total 485568 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 219136 # Nu system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7587 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 225040663000 # Total gap between requests +system.physmem.totGap 225206267000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation -system.physmem.totQLat 55497500 # Total ticks spent queuing -system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation +system.physmem.totQLat 232482000 # Total ticks spent queuing +system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst +system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,56 +217,66 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6044 # Number of row buffer hits during reads +system.physmem.readRowHits 6073 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29661350.07 # Average gap between requests -system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29683177.41 # Average gap between requests +system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.691134 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.071438 # Core power per rank (mW) +system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states +system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states +system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.800930 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32430292 # Number of BP lookups -system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.505361 # Core power per rank (mW) +system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states +system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32430299 # Number of BP lookups +system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 450081822 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450413042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037855 # Number of instructions committed system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.648423 # CPI: cycles per instruction -system.cpu.ipc 0.606640 # IPC: instructions per cycle +system.cpu.cpi 1.649636 # CPI: cycles per instruction +system.cpu.ipc 0.606194 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction @@ -432,62 +442,62 @@ system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits -system.cpu.dcache.overall_hits::total 168632429 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits +system.cpu.dcache.overall_hits::total 168632415 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses -system.cpu.dcache.overall_misses::total 6935 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses +system.cpu.dcache.overall_misses::total 6945 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +506,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -510,14 +520,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,12 +538,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -544,16 +554,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -564,72 +574,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits -system.cpu.icache.overall_hits::total 69819782 # number of overall hits +system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits +system.cpu.icache.overall_hits::total 69819801 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,46 +654,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126 system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits @@ -712,18 +722,18 @@ system.cpu.l2cache.demand_misses::total 7630 # nu system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) @@ -752,18 +762,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.170931 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,18 +802,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7587 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses @@ -816,25 +826,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution @@ -874,7 +884,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution @@ -895,9 +905,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 7f3ecc8dc..3870e90de 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index c5508bf05..5ac8e5d82 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12223 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:51:10 +gem5 executing on e108600-lin, pid 17461 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -15,5 +15,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.110000 -Exiting @ tick 111753553500 because target called exit() +OO-style eon Time= 0.120000 +Exiting @ tick 122177531500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 3bab29953..9802024db 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.120480 # Number of seconds simulated -sim_ticks 120480458500 # Number of ticks simulated -final_tick 120480458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.122178 # Number of seconds simulated +sim_ticks 122177531500 # Number of ticks simulated +final_tick 122177531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129515 # Simulator instruction rate (inst/s) -host_op_rate 155497 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57149813 # Simulator tick rate (ticks/s) -host_mem_usage 293332 # Number of bytes of host memory used -host_seconds 2108.15 # Real time elapsed on the host +host_inst_rate 120262 # Simulator instruction rate (inst/s) +host_op_rate 144388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53814187 # Simulator tick rate (ticks/s) +host_mem_usage 292180 # Number of bytes of host memory used +host_seconds 2270.36 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1888064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14651392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 167808 # Number of bytes read from this memory -system.physmem.bytes_read::total 16707264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1888064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1888064 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2622 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261051 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15671122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 121608037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1392823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138671982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15671122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15671122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15671122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 121608037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1392823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138671982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261052 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1888192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14650048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169280 # Number of bytes read from this memory +system.physmem.bytes_read::total 16707520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1888192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1888192 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2645 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261055 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15454495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 119907874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1385525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136747893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15454495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15454495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15454495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 119907874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1385525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 136747893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261056 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261056 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16707328 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16707584 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16707328 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16707584 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::0 1259 # Per bank write bursts system.physmem.perBankRdBursts::1 69992 # Per bank write bursts system.physmem.perBankRdBursts::2 1296 # Per bank write bursts -system.physmem.perBankRdBursts::3 10757 # Per bank write bursts +system.physmem.perBankRdBursts::3 10759 # Per bank write bursts system.physmem.perBankRdBursts::4 42908 # Per bank write bursts -system.physmem.perBankRdBursts::5 121820 # Per bank write bursts +system.physmem.perBankRdBursts::5 121819 # Per bank write bursts system.physmem.perBankRdBursts::6 160 # Per bank write bursts -system.physmem.perBankRdBursts::7 266 # Per bank write bursts -system.physmem.perBankRdBursts::8 224 # Per bank write bursts +system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::8 228 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts system.physmem.perBankRdBursts::10 7776 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts system.physmem.perBankRdBursts::12 1213 # Per bank write bursts system.physmem.perBankRdBursts::13 743 # Per bank write bursts -system.physmem.perBankRdBursts::14 656 # Per bank write bursts -system.physmem.perBankRdBursts::15 609 # Per bank write bursts +system.physmem.perBankRdBursts::14 662 # Per bank write bursts +system.physmem.perBankRdBursts::15 610 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 120480449000 # Total gap between requests +system.physmem.totGap 122177522000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261052 # Read request sizes (log2) +system.physmem.readPktSize::6 261056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12075 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,86 +191,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.160415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.717328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 205.520754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18369 27.40% 27.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21159 31.56% 58.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11457 17.09% 76.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6629 9.89% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4618 6.89% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2220 3.31% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1372 2.05% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 491 0.73% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 730 1.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67045 # Bytes accessed per row activation -system.physmem.totQLat 2500931533 # Total ticks spent queuing -system.physmem.totMemAccLat 7395656533 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305260000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9580.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 248.480388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.727737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.056429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18253 27.15% 27.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21438 31.89% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11486 17.08% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6691 9.95% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4636 6.90% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2199 3.27% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1378 2.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 426 0.63% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 722 1.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67229 # Bytes accessed per row activation +system.physmem.totQLat 4621160381 # Total ticks spent queuing +system.physmem.totMemAccLat 9515960381 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17701.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28330.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 138.67 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36451.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 136.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 138.67 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 136.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.08 # Data bus utilization in percentage -system.physmem.busUtilRead 1.08 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.07 # Data bus utilization in percentage +system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193998 # Number of row buffer hits during reads +system.physmem.readRowHits 193817 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 461518.97 # Average gap between requests -system.physmem.pageHitRate 74.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 469687680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 256278000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1937777400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 468012.69 # Average gap between requests +system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 445443180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 236747280 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773933000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73664414550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7668236250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 91865342760 # Total energy per rank (pJ) -system.physmem_0.averagePower 762.514125 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12350213739 # Time in different power states -system.physmem_0.memoryStateTime::REF 4022980000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 104104852261 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 37134720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 20262000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 98069400 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9531222480.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4632019500 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 224464800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45099806190 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3562907040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 919525950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 66426265230 # Total energy per rank (pJ) +system.physmem_0.averagePower 543.686420 # Core power per rank (mW) +system.physmem_0.totalIdleTime 111434381144 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 154081000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4033332000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3253133750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9278182481 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6555604606 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 98903197663 # Time in different power states +system.physmem_1.actEnergy 34636140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18382980 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 89999700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 16939770435 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 57426696000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 82390881435 # Total energy per rank (pJ) -system.physmem_1.averagePower 683.872818 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 95444315624 # Time in different power states -system.physmem_1.memoryStateTime::REF 4022980000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21009739880 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971487 # Number of BP lookups -system.cpu.branchPred.condPredicted 19266966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984300 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894295 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923321 # Number of BTB hits +system.physmem_1.refreshEnergy 3038165520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 716380560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 121415040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10108537890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3723173760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 21583783695 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 39434924925 # Total energy per rank (pJ) +system.physmem_1.averagePower 322.767403 # Core power per rank (mW) +system.physmem_1.totalIdleTime 120289757500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 194586000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1289158000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 88425719250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9695988513 # Time in different power states +system.physmem_1.memoryStateTime::ACT 404030000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22168049737 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35971486 # Number of BP lookups +system.cpu.branchPred.condPredicted 19267078 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984296 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17894197 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923261 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.808715 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 77.808806 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6951889 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517210 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2517219 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43855 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128902 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 43864 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128904 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,97 +401,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 240960918 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 244355064 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12852393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309387545 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971487 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348567 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 224289895 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1990323 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1871 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 12854090 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309386185 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35971486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348505 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 227028352 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1990311 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1601 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3026 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82204082 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34266 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 238142439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.562665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.293284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3162 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82203694 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 240882453 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.544883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296552 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77933727 32.73% 32.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40203358 16.88% 49.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28082672 11.79% 61.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91922682 38.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 80675861 33.49% 33.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40201773 16.69% 50.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28081031 11.66% 61.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91923788 38.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 238142439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.149283 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.283974 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26809492 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 87975457 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98235303 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24260898 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 861289 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686645 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134215 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348536073 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3411178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 861289 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43087679 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34729777 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 287359 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105264108 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53912227 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344595535 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1451317 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7117459 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85486 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7456793 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27429966 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3277218 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394867605 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218081796 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335910446 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192911530 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 240882453 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.147210 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.266134 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 26812973 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 90710528 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 98252382 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 24245286 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 861284 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6686689 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134210 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348538542 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3411137 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 861284 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43083632 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37000044 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289266 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 105269732 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 54378495 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344597413 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1451618 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7112089 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 85489 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7460814 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27903739 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3277402 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394869828 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2218091968 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335911643 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192912802 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22637557 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22639780 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11573 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57394706 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89984018 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84392471 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1976841 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1898355 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343274386 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22623 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339465004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 967637 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15485409 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37250778 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 238142439 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.425470 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.136916 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 11574 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57375410 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89984183 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84392474 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977179 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1898949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343275804 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22622 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339466020 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 967573 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15486826 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 37253539 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 502 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 240882453 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.409260 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.140571 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 57979720 24.35% 24.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76155774 31.98% 56.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59457503 24.97% 81.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34550396 14.51% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9286722 3.90% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 677796 0.28% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34528 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 60724616 25.21% 25.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76160793 31.62% 56.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59430978 24.67% 81.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34569007 14.35% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9283720 3.85% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 678664 0.28% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34675 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 238142439 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 240882453 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9217758 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7319 0.01% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9218221 7.75% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7322 0.01% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available @@ -500,22 +510,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 238781 0.20% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 238834 0.20% 7.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 138932 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70694 0.06% 8.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68373 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 637081 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 296736 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 541785 0.46% 9.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51510154 43.32% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56187310 47.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 138891 0.12% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 70679 0.06% 8.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68365 0.06% 8.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 640804 0.54% 8.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 296732 0.25% 8.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 541759 0.46% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51504063 43.31% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56187426 47.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108183295 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148337 0.63% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108184064 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148340 0.63% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued @@ -534,91 +544,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792696 2.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6792701 2.00% 34.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8634939 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210556 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8634973 2.54% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3210554 0.95% 37.99% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20863290 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7179112 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141893 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20863316 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7179113 2.11% 46.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141894 2.10% 48.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90024001 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518602 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 90024187 26.52% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 83518595 24.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339465004 # Type of FU issued -system.cpu.iq.rate 1.408797 # Inst issue rate -system.cpu.iq.fu_busy_cnt 118914923 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350301 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 753593457 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235149136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219170609 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283361550 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123645361 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116917491 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293630516 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164749411 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5409371 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339466020 # Type of FU issued +system.cpu.iq.rate 1.389233 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118913096 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.350295 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756328552 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235151256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219171646 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283366610 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123646075 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116917582 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 293624810 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 164754306 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5408815 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4251743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7382 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 4251908 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7378 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2016854 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 2016857 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126951 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613385 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 126936 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 613330 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 861289 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1346418 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1223561 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343298428 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 861284 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1350225 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1508994 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343299844 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89984018 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84392471 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7654 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1216581 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 89984183 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84392474 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11589 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7652 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1502014 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 438027 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454511 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892538 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337435973 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89435470 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2029031 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 438026 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454508 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892534 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337437017 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89435625 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2029003 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1419 # number of nop insts executed -system.cpu.iew.exec_refs 172563167 # number of memory reference insts executed -system.cpu.iew.exec_branches 31555788 # Number of branches executed -system.cpu.iew.exec_stores 83127697 # Number of stores executed -system.cpu.iew.exec_rate 1.400376 # Inst execution rate -system.cpu.iew.wb_sent 336234414 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336088100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151781597 # num instructions producing a value -system.cpu.iew.wb_consumers 263546089 # num instructions consuming a value -system.cpu.iew.wb_rate 1.394783 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575921 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14163176 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1418 # number of nop insts executed +system.cpu.iew.exec_refs 172563316 # number of memory reference insts executed +system.cpu.iew.exec_branches 31556143 # Number of branches executed +system.cpu.iew.exec_stores 83127691 # Number of stores executed +system.cpu.iew.exec_rate 1.380929 # Inst execution rate +system.cpu.iew.wb_sent 336235772 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336089228 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151786231 # num instructions producing a value +system.cpu.iew.wb_consumers 263562514 # num instructions consuming a value +system.cpu.iew.wb_rate 1.375413 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575902 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14164375 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850428 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 235953046 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.389311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.042233 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850425 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 238692959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.373364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.035708 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 104793604 44.41% 44.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67594704 28.65% 73.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20883417 8.85% 81.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13239055 5.61% 87.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8655759 3.67% 91.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4517031 1.91% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3019754 1.28% 94.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2590982 1.10% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10658740 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 107534765 45.05% 45.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 67583251 28.31% 73.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20880103 8.75% 82.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13256001 5.55% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8658859 3.63% 91.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4515867 1.89% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3014415 1.26% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2598093 1.09% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10651605 4.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 235953046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 238692959 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,96 +674,96 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 10658740 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 567267171 # The number of ROB reads -system.cpu.rob.rob_writes 686142351 # The number of ROB writes -system.cpu.timesIdled 39413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2818479 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10651605 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 570015418 # The number of ROB reads +system.cpu.rob.rob_writes 686144847 # The number of ROB writes +system.cpu.timesIdled 39403 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3472611 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.882520 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.882520 # CPI: Total CPI of All Threads -system.cpu.ipc 1.133118 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.133118 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325162337 # number of integer regfile reads -system.cpu.int_regfile_writes 134093699 # number of integer regfile writes -system.cpu.fp_regfile_reads 186638060 # number of floating regfile reads -system.cpu.fp_regfile_writes 131662989 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279404689 # number of cc regfile reads -system.cpu.cc_regfile_writes 80058303 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056730531 # number of misc regfile reads +system.cpu.cpi 0.894951 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.894951 # CPI: Total CPI of All Threads +system.cpu.ipc 1.117379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.117379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325163205 # number of integer regfile reads +system.cpu.int_regfile_writes 134094196 # number of integer regfile writes +system.cpu.fp_regfile_reads 186638267 # number of floating regfile reads +system.cpu.fp_regfile_writes 131663703 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279409265 # number of cc regfile reads +system.cpu.cc_regfile_writes 80058845 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056731782 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542807 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.846983 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162052499 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543319 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.002594 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 87321000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.846983 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999701 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999701 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542799 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.841241 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 162053309 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543311 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 105.003664 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.841241 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999690 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333478959 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333478959 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81039652 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81039652 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921351 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921351 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69633 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69633 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 333480485 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333480485 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 81040424 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81040424 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921391 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921391 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69631 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69631 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161961003 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161961003 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162030636 # number of overall hits -system.cpu.dcache.overall_hits::total 162030636 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2784011 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2784011 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131348 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131348 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161961815 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161961815 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 162031446 # number of overall hits +system.cpu.dcache.overall_hits::total 162031446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784008 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784008 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131308 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131308 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915359 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915359 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915377 # number of overall misses -system.cpu.dcache.overall_misses::total 3915377 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45256653500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45256653500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9138834402 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9138834402 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54395487902 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54395487902 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54395487902 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54395487902 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83823663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83823663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3915316 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3915316 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3915334 # number of overall misses +system.cpu.dcache.overall_misses::total 3915334 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47872980500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47872980500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9172353414 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9172353414 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 57045333914 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 57045333914 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 57045333914 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 57045333914 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83824432 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83824432 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69651 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69649 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69649 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165876362 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165876362 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165946013 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165946013 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033213 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165877131 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165877131 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165946780 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165946780 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses @@ -764,54 +774,54 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8077.827867 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8077.827867 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 46000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 46000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13892.848115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13892.784246 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.705077 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.705077 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8107.742024 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8107.742024 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14569.790513 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14569.790513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14569.723532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14569.723532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1086145 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1090477 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136219 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136210 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.973521 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542807 # number of writebacks -system.cpu.dcache.writebacks::total 1542807 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461430 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1461430 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910604 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910604 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.005851 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542799 # number of writebacks +system.cpu.dcache.writebacks::total 1542799 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461435 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1461435 # number of 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access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 50 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 50 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 36 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 36 # number of ReadSharedReq MSHR hits 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miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206471258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19355381258 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040634 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172520 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172520 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113878 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172525 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172525 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113870 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137742 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137871 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3790.758771 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4537857 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268434 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51535 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51534 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88424.657534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88424.657534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83022.895201 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83022.895201 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72903.283416 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72903.283416 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74102.534335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61862.391277 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4537831 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268421 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51822 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51821 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2048700 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300147 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55525 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2048687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300143 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55841 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177753 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6807232 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197512064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290416512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55606 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322572 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177738 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6807193 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92903808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290414848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55922 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2324982 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131629 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2325285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131736 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338205 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2018948 86.84% 86.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 306033 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018962 86.83% 86.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306322 13.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2324982 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4537328500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1089458442 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2325285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537302500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089460423 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2315007958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2314997455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261068 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253748 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 261072 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253753 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260294 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260325 # Transaction distribution system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 757 # Transaction distribution -system.membus.trans_dist::ReadExResp 757 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522119 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522119 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16707264 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 730 # Transaction distribution +system.membus.trans_dist::ReadExResp 730 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260326 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522127 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522127 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16707520 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261068 # Request fanout histogram +system.membus.snoop_fanout::samples 261072 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261068 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261072 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261068 # Request fanout histogram -system.membus.reqLayer0.occupancy 329929457 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261072 # Request fanout histogram +system.membus.reqLayer0.occupancy 329884354 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1377865586 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1377672131 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini index ca9122542..1dc6d91c8 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout index b5d01fab2..c97afb693 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4301 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28059 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second @@ -650,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 508215534000 because target called exit() +Exiting @ tick 521167228000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index cfec5db38..40d44c1cb 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.508441 # Number of seconds simulated -sim_ticks 508441445000 # Number of ticks simulated -final_tick 508441445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.521167 # Number of seconds simulated +sim_ticks 521167228000 # Number of ticks simulated +final_tick 521167228000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 272638 # Simulator instruction rate (inst/s) -host_op_rate 272638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 149248503 # Simulator tick rate (ticks/s) -host_mem_usage 263860 # Number of bytes of host memory used -host_seconds 3406.68 # Real time elapsed on the host +host_inst_rate 258077 # Simulator instruction rate (inst/s) +host_op_rate 258077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 144813393 # Simulator tick rate (ticks/s) +host_mem_usage 260992 # Number of bytes of host memory used +host_seconds 3598.89 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185856 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 185984 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185856 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18706880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 185984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 185984 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2906 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292293 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292295 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 365541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36426802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36792343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 365541 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 365541 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8393714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8393714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8393714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 365541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36426802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 45186057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292293 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 356861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35537338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 35894199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 356861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 356861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8188757 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8188757 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8188757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 356861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35537338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44082956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292295 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292293 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292295 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18685888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706752 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18686976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18706880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18028 # Per bank write bursts -system.physmem.perBankRdBursts::1 18361 # Per bank write bursts -system.physmem.perBankRdBursts::2 18399 # Per bank write bursts -system.physmem.perBankRdBursts::3 18347 # Per bank write bursts -system.physmem.perBankRdBursts::4 18249 # Per bank write bursts -system.physmem.perBankRdBursts::5 18247 # Per bank write bursts -system.physmem.perBankRdBursts::6 18319 # Per bank write bursts -system.physmem.perBankRdBursts::7 18291 # Per bank write bursts -system.physmem.perBankRdBursts::8 18230 # Per bank write bursts -system.physmem.perBankRdBursts::9 18239 # Per bank write bursts -system.physmem.perBankRdBursts::10 18229 # Per bank write bursts -system.physmem.perBankRdBursts::11 18377 # Per bank write bursts +system.physmem.perBankRdBursts::1 18369 # Per bank write bursts +system.physmem.perBankRdBursts::2 18396 # Per bank write bursts +system.physmem.perBankRdBursts::3 18341 # Per bank write bursts +system.physmem.perBankRdBursts::4 18255 # Per bank write bursts +system.physmem.perBankRdBursts::5 18258 # Per bank write bursts +system.physmem.perBankRdBursts::6 18325 # Per bank write bursts +system.physmem.perBankRdBursts::7 18297 # Per bank write bursts +system.physmem.perBankRdBursts::8 18227 # Per bank write bursts +system.physmem.perBankRdBursts::9 18235 # Per bank write bursts +system.physmem.perBankRdBursts::10 18232 # Per bank write bursts +system.physmem.perBankRdBursts::11 18375 # Per bank write bursts system.physmem.perBankRdBursts::12 18268 # Per bank write bursts -system.physmem.perBankRdBursts::13 18136 # Per bank write bursts +system.physmem.perBankRdBursts::13 18134 # Per bank write bursts system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18190 # Per bank write bursts -system.physmem.perBankWrBursts::0 4125 # Per bank write bursts +system.physmem.perBankRdBursts::15 18187 # Per bank write bursts +system.physmem.perBankWrBursts::0 4123 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4223 # Per bank write bursts -system.physmem.perBankWrBursts::3 4160 # Per bank write bursts -system.physmem.perBankWrBursts::4 4142 # Per bank write bursts -system.physmem.perBankWrBursts::5 4099 # Per bank write bursts -system.physmem.perBankWrBursts::6 4262 # Per bank write bursts -system.physmem.perBankWrBursts::7 4226 # Per bank write bursts +system.physmem.perBankWrBursts::2 4221 # Per bank write bursts +system.physmem.perBankWrBursts::3 4157 # Per bank write bursts +system.physmem.perBankWrBursts::4 4141 # Per bank write bursts +system.physmem.perBankWrBursts::5 4097 # Per bank write bursts +system.physmem.perBankWrBursts::6 4260 # Per bank write bursts +system.physmem.perBankWrBursts::7 4224 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4188 # Per bank write bursts +system.physmem.perBankWrBursts::9 4192 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 508441362500 # Total gap between requests +system.physmem.totGap 521167139500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292293 # Read request sizes (log2) +system.physmem.readPktSize::6 292295 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4055 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,102 +194,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103424 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 221.899134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.895688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.440022 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37597 36.35% 36.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43798 42.35% 78.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9078 8.78% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 804 0.78% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1585 1.53% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1026 0.99% 90.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 543 0.53% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 660 0.64% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8333 8.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103424 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.164816 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.696519 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 767.230213 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 95989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 239.106731 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.105135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 271.560992 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28950 30.16% 30.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41784 43.53% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11694 12.18% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2599 2.71% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 913 0.95% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 756 0.79% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 331 0.34% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 447 0.47% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8515 8.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95989 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.753823 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.637200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 730.740597 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.448063 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.427763 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.835172 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3146 77.62% 77.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 906 22.35% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads -system.physmem.totQLat 2452616250 # Total ticks spent queuing -system.physmem.totMemAccLat 7926997500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8400.32 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.441539 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.421503 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.829633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3159 77.92% 77.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 895 22.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads +system.physmem.totQLat 15194551500 # Total ticks spent queuing +system.physmem.totMemAccLat 20669251500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459920000 # Total ticks spent in databus transfers +system.physmem.avgQLat 52038.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27150.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.75 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.39 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70788.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 35.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 35.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage -system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.34 # Data bus utilization in percentage +system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing -system.physmem.readRowHits 203097 # Number of row buffer hits during reads -system.physmem.writeRowHits 52099 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes -system.physmem.avgGap 1416365.89 # Average gap between requests -system.physmem.pageHitRate 71.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 390353040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 212990250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140196200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103170345705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214560479250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 352899262365 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.089734 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 356274409500 # Time in different power states -system.physmem_0.memoryStateTime::REF 16977740000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 135182501000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 391426560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 213576000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136460000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103438175310 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 214325517750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 352929159300 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.148589 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 355878371250 # Time in different power states -system.physmem_1.memoryStateTime::REF 16977740000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135579179250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851654 # Number of BP lookups -system.cpu.branchPred.condPredicted 79872946 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 686743 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066133 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190143 # Number of BTB hits +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 210474 # Number of row buffer hits during reads +system.physmem.writeRowHits 52167 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes +system.physmem.avgGap 1451808.02 # Average gap between requests +system.physmem.pageHitRate 73.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341770380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 181632495 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1044360660 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174280140 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 28691395200.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8105258640 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1605839040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 57337999170 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 51043667520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 64046185080 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 212592411075 # Total energy per rank (pJ) +system.physmem_0.averagePower 407.915916 # Core power per rank (mW) +system.physmem_0.totalIdleTime 499165974500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3167480750 # Time in different power states +system.physmem_0.memoryStateTime::REF 12206580000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 240498579500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 132926079750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6626927000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 125741581000 # Time in different power states +system.physmem_1.actEnergy 343648200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 182645760 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1040405100 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 173653740 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 28803874320.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8196268830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1616284320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 57528037740 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 51141308640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 63870409695 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 212914803135 # Total energy per rank (pJ) +system.physmem_1.averagePower 408.534516 # Core power per rank (mW) +system.physmem_1.totalIdleTime 498942805750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3183963500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12254448000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 239604631750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 133180372750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6785962500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 126157849500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 123851675 # Number of BP lookups +system.cpu.branchPred.condPredicted 79872959 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 686742 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 102066154 # Number of BTB lookups +system.cpu.branchPred.BTBHits 68190152 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.809764 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697398 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 11224 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14052177 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14048616 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3561 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11655 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 66.809759 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18697401 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 11223 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14052181 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14048615 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3566 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11656 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -299,18 +308,18 @@ system.cpu.dtb.read_hits 237539296 # DT system.cpu.dtb.read_misses 195211 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305021 # DTB write hits +system.cpu.dtb.write_hits 98305023 # DTB write hits system.cpu.dtb.write_misses 7170 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312191 # DTB write accesses -system.cpu.dtb.data_hits 335844317 # DTB hits +system.cpu.dtb.write_accesses 98312193 # DTB write accesses +system.cpu.dtb.data_hits 335844319 # DTB hits system.cpu.dtb.data_misses 202381 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046698 # DTB accesses -system.cpu.itb.fetch_hits 286584411 # ITB hits +system.cpu.dtb.data_accesses 336046700 # DTB accesses +system.cpu.itb.fetch_hits 286584578 # ITB hits system.cpu.itb.fetch_misses 119 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584530 # ITB accesses +system.cpu.itb.fetch_accesses 286584697 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,16 +333,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 508441445000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1016882890 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 521167228000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1042334456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319599 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 319598 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.094848 # CPI: cycles per instruction -system.cpu.ipc 0.913369 # IPC: instructions per cycle +system.cpu.cpi 1.122251 # CPI: cycles per instruction +system.cpu.ipc 0.891066 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction @@ -369,60 +378,60 @@ system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962815783 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54067107 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 962817000 # Number of cycles that the object actually ticked +system.cpu.idleCycles 79517456 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.323693 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318732 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.209717 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320318705 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320477 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 911974500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.323693 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999102 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999102 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 410.320442 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 968708500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.209717 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999075 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999075 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1491 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 957 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1349 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115727 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115727 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154683 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154683 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164049 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164049 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318732 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318732 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318732 # number of overall hits -system.cpu.dcache.overall_hits::total 320318732 # number of overall hits +system.cpu.dcache.tags.tag_accesses 643115675 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 643115675 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 222154657 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 222154657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164048 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164048 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 320318705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320318705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320318705 # number of overall hits +system.cpu.dcache.overall_hits::total 320318705 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137151 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137151 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 848804 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 848804 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 848804 # number of overall misses -system.cpu.dcache.overall_misses::total 848804 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24607511500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24607511500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10163393500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10163393500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34770905000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34770905000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34770905000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34770905000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866336 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137152 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137152 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 848805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 848805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 848805 # number of overall misses +system.cpu.dcache.overall_misses::total 848805 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36922839000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36922839000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10957317000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10957317000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 47880156000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 47880156000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 47880156000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 47880156000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 222866310 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 222866310 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167536 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167536 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167536 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167536 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 321167510 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 321167510 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 321167510 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 321167510 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -431,14 +440,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34577.963558 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34577.963558 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74103.677698 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74103.677698 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40964.586642 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40964.586642 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51883.205720 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51883.205720 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79891.777007 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79891.777007 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56408.899571 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56408.899571 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,12 +458,12 @@ system.cpu.dcache.writebacks::writebacks 88440 # nu system.cpu.dcache.writebacks::total 88440 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68140 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68140 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68149 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68149 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68149 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68149 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68141 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68141 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68150 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68150 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68150 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68150 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711644 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711644 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -463,14 +472,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780655 system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23895183000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23895183000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5097981500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5097981500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28993164500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28993164500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993164500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28993164500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36210490500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36210490500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5501688000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5501688000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41712178500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41712178500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41712178500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41712178500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -479,24 +488,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33577.439000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33577.439000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73872.013157 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73872.013157 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10578 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.178313 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572086 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12324 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23253.171535 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50882.871913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50882.871913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79721.899407 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79721.899407 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 10581 # number of replacements +system.cpu.icache.tags.tagsinuse 1690.101724 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 286572250 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12327 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23247.525756 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1690.178313 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825282 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825282 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1690.101724 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.825245 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.825245 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id @@ -504,181 +513,181 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181146 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181146 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572086 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572086 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572086 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286572086 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286572086 # number of overall hits -system.cpu.icache.overall_hits::total 286572086 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12325 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12325 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12325 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12325 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12325 # number of overall misses -system.cpu.icache.overall_misses::total 12325 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 354631500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 354631500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 354631500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 354631500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 354631500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 354631500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286584411 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286584411 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286584411 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286584411 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286584411 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286584411 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 573181483 # Number of tag accesses +system.cpu.icache.tags.data_accesses 573181483 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 286572250 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 286572250 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 286572250 # number of demand (read+write) hits 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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74568.159652 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77422.203098 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77422.203098 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79437.632439 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79437.632439 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78307.329264 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78307.329264 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.368603 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80625.725861 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80625.725861 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85018.059856 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85018.059856 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134726.706443 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134726.706443 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 121897.030750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 121897.030750 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,126 +700,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2905 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2905 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2907 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2907 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2905 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2907 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292294 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2905 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292296 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2907 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292294 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4303145000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4303145000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195871500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195871500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15466816000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15466816000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195871500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19769961000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19965832500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195871500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19769961000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19965832500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 292296 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4706851500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4706851500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 218087500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 218087500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27782125500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27782125500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218087500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32488977000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32707064500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218087500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32488977000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32707064500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235805 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368602 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368603 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368602 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64568.159652 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64568.159652 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67425.645439 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67425.645439 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69437.632439 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69437.632439 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580117 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787137 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368603 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70625.725861 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70625.725861 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75021.499828 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75021.499828 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124726.706443 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124726.706443 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1580123 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787140 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2095 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723968 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 723971 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881420 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12328 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35227 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35236 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373096 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2373105 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1466112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57087808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259981 # Total snoops (count) +system.cpu.toL2Bus.pkt_size::total 57088192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259984 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052961 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001990 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044561 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1052967 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001991 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044571 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050866 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2095 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050871 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2096 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052961 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889076500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052967 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889082500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18486000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18490500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170982999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170982500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 550179 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257886 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 550183 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257888 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225648 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225650 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191203 # Transaction distribution +system.membus.trans_dist::CleanEvict 191205 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225648 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842472 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22974464 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225650 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842478 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842478 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22974592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292293 # Request fanout histogram +system.membus.snoop_fanout::samples 292295 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292293 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292295 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292293 # Request fanout histogram -system.membus.reqLayer0.occupancy 925378500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292295 # Request fanout histogram +system.membus.reqLayer0.occupancy 925387500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556878500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1555624500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 0e87d435d..49d14f26b 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 8e7b7a0be..2bef733aa 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4303 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28086 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -650,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 174766258500 because target called exit() +Exiting @ tick 180964610500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index c74410070..d1e4abf0c 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.175004 # Number of seconds simulated -sim_ticks 175004412500 # Number of ticks simulated -final_tick 175004412500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.180965 # Number of seconds simulated +sim_ticks 180964610500 # Number of ticks simulated +final_tick 180964610500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 244500 # Simulator instruction rate (inst/s) -host_op_rate 244500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50794673 # Simulator tick rate (ticks/s) -host_mem_usage 265392 # Number of bytes of host memory used -host_seconds 3445.33 # Real time elapsed on the host +host_inst_rate 216717 # Simulator instruction rate (inst/s) +host_op_rate 216717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46556270 # Simulator tick rate (ticks/s) +host_mem_usage 262532 # Number of bytes of host memory used +host_seconds 3887.01 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18525120 # Number of bytes read from this memory -system.physmem.bytes_read::total 18699072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18525056 # Number of bytes read from this memory +system.physmem.bytes_read::total 18699008 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289455 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292173 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289454 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292172 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 993986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 105855160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106849146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 993986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 993986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24385945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24385945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24385945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 993986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 105855160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 131235091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292173 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 961249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 102368391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103329640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 961249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 961249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 23582777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 23582777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 23582777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 961249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 102368391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 126912416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292172 # Number of read requests accepted system.physmem.writeReqs 66682 # Number of write requests accepted -system.physmem.readBursts 292173 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292172 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18679488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18699072 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18678912 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266048 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18699008 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18012 # Per bank write bursts +system.physmem.perBankRdBursts::0 18010 # Per bank write bursts system.physmem.perBankRdBursts::1 18337 # Per bank write bursts -system.physmem.perBankRdBursts::2 18383 # Per bank write bursts -system.physmem.perBankRdBursts::3 18348 # Per bank write bursts -system.physmem.perBankRdBursts::4 18239 # Per bank write bursts -system.physmem.perBankRdBursts::5 18237 # Per bank write bursts -system.physmem.perBankRdBursts::6 18320 # Per bank write bursts -system.physmem.perBankRdBursts::7 18308 # Per bank write bursts -system.physmem.perBankRdBursts::8 18229 # Per bank write bursts -system.physmem.perBankRdBursts::9 18225 # Per bank write bursts -system.physmem.perBankRdBursts::10 18220 # Per bank write bursts -system.physmem.perBankRdBursts::11 18382 # Per bank write bursts +system.physmem.perBankRdBursts::2 18388 # Per bank write bursts +system.physmem.perBankRdBursts::3 18350 # Per bank write bursts +system.physmem.perBankRdBursts::4 18232 # Per bank write bursts +system.physmem.perBankRdBursts::5 18236 # Per bank write bursts +system.physmem.perBankRdBursts::6 18319 # Per bank write bursts +system.physmem.perBankRdBursts::7 18311 # Per bank write bursts +system.physmem.perBankRdBursts::8 18232 # Per bank write bursts +system.physmem.perBankRdBursts::9 18232 # Per bank write bursts +system.physmem.perBankRdBursts::10 18215 # Per bank write bursts +system.physmem.perBankRdBursts::11 18381 # Per bank write bursts system.physmem.perBankRdBursts::12 18250 # Per bank write bursts -system.physmem.perBankRdBursts::13 18123 # Per bank write bursts -system.physmem.perBankRdBursts::14 18058 # Per bank write bursts -system.physmem.perBankRdBursts::15 18196 # Per bank write bursts +system.physmem.perBankRdBursts::13 18122 # Per bank write bursts +system.physmem.perBankRdBursts::14 18054 # Per bank write bursts +system.physmem.perBankRdBursts::15 18189 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4261 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4191 # Per bank write bursts +system.physmem.perBankWrBursts::9 4182 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 175004322000 # Total gap between requests +system.physmem.totGap 180964514000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292173 # Read request sizes (log2) +system.physmem.readPktSize::6 292172 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,12 +98,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 214643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -145,25 +145,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -194,126 +194,136 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96708 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.268147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.455294 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 282.430006 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 31632 32.71% 32.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41779 43.20% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11320 11.71% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 443 0.46% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 357 0.37% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 304 0.31% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 669 0.69% 89.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1569 1.62% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8635 8.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96708 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.658609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.711074 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 765.890247 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4045 99.78% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 95105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.251837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.294089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.548448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30650 32.23% 32.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40922 43.03% 75.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11798 12.41% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 210 0.22% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 215 0.23% 88.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 192 0.20% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 361 0.38% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1740 1.83% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9017 9.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95105 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4055 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.502343 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.667312 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 739.938886 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4047 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.444499 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.424176 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.836057 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3157 77.87% 77.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 892 22.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads -system.physmem.totQLat 3688779750 # Total ticks spent queuing -system.physmem.totMemAccLat 9161286000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12638.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4055 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4055 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.438224 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.418308 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.827243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3164 78.03% 78.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.17% 78.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 882 21.75% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4055 # Writes before turning the bus around for reads +system.physmem.totQLat 10146386000 # Total ticks spent queuing +system.physmem.totMemAccLat 15618723500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459290000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34764.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31388.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.74 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 24.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 24.39 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53514.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 23.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 23.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.19 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.99 # Data bus utilization in percentage +system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.18 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 209722 # Number of row buffer hits during reads -system.physmem.writeRowHits 52099 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes -system.physmem.avgGap 487674.19 # Average gap between requests -system.physmem.pageHitRate 73.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 365095080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 199208625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140180600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 11430394560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63710720865 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 49115814750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 126177846480 # Total energy per rank (pJ) -system.physmem_0.averagePower 720.999703 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81290875500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5843760000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87869398250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 366002280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 199703625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136311800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215563680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 11430394560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64026816075 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48838535250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 126213327270 # Total energy per rank (pJ) -system.physmem_1.averagePower 721.202467 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 80826473000 # Time in different power states -system.physmem_1.memoryStateTime::REF 5843760000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 88334018000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 129267773 # Number of BP lookups -system.cpu.branchPred.condPredicted 83048997 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 145228 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93512308 # Number of BTB lookups -system.cpu.branchPred.BTBHits 70602709 # Number of BTB hits +system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing +system.physmem.readRowHits 211326 # Number of row buffer hits during reads +system.physmem.writeRowHits 52079 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.41 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.10 # Row buffer hit rate for writes +system.physmem.avgGap 504284.51 # Average gap between requests +system.physmem.pageHitRate 73.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 339192840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 180273885 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1043746620 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174348000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 16047635760.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5505974850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 757646880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 38977794150 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 26263488480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 5833398105 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 95148801450 # Total energy per rank (pJ) +system.physmem_0.averagePower 525.786736 # Core power per rank (mW) +system.physmem_0.totalIdleTime 166860797500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1403220500 # Time in different power states +system.physmem_0.memoryStateTime::REF 6819966000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 12988477500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 68394436250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5880505500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 85478004750 # Time in different power states +system.physmem_1.actEnergy 339892560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 180649590 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1040119500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 173601540 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 16056240720.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5469389970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 750054720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 39161701800 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 26293456800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 5720767110 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 95209751490 # Total energy per rank (pJ) +system.physmem_1.averagePower 526.123579 # Core power per rank (mW) +system.physmem_1.totalIdleTime 166963691000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1377166250 # Time in different power states +system.physmem_1.memoryStateTime::REF 6823618000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 12610325250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 68472559500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5800086000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 85880855500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 129261099 # Number of BP lookups +system.cpu.branchPred.condPredicted 83045520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 145257 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93509067 # Number of BTB lookups +system.cpu.branchPred.BTBHits 70599314 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 75.500980 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19428222 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1139 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14846516 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14819690 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 26826 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4927 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 75.499966 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19428116 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1153 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14846448 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14825593 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 20855 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 243602594 # DTB read hits -system.cpu.dtb.read_misses 267810 # DTB read misses +system.cpu.dtb.read_hits 243608266 # DTB read hits +system.cpu.dtb.read_misses 267709 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 243870404 # DTB read accesses -system.cpu.dtb.write_hits 101634629 # DTB write hits -system.cpu.dtb.write_misses 39603 # DTB write misses +system.cpu.dtb.read_accesses 243875975 # DTB read accesses +system.cpu.dtb.write_hits 101634051 # DTB write hits +system.cpu.dtb.write_misses 39619 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 101674232 # DTB write accesses -system.cpu.dtb.data_hits 345237223 # DTB hits -system.cpu.dtb.data_misses 307413 # DTB misses +system.cpu.dtb.write_accesses 101673670 # DTB write accesses +system.cpu.dtb.data_hits 345242317 # DTB hits +system.cpu.dtb.data_misses 307328 # DTB misses system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 345544636 # DTB accesses -system.cpu.itb.fetch_hits 116218491 # ITB hits -system.cpu.itb.fetch_misses 1583 # ITB misses +system.cpu.dtb.data_accesses 345549645 # DTB accesses +system.cpu.itb.fetch_hits 116218000 # ITB hits +system.cpu.itb.fetch_misses 1612 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 116220074 # ITB accesses +system.cpu.itb.fetch_accesses 116219612 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -327,99 +337,99 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 175004412500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 350008826 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 180964610500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 361929222 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 116537595 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973721565 # Number of instructions fetch has processed -system.cpu.fetch.Branches 129267773 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 104850621 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 232833162 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 756818 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12983 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 116540326 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 973682349 # Number of instructions fetch has processed +system.cpu.fetch.Branches 129261099 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 104853023 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 244730119 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 756754 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 840 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 15490 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 116218491 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 171000 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 349762998 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.783947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.089679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 116218000 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 168019 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 361665180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.692220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.078693 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 153044218 43.76% 43.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 21853200 6.25% 50.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15619262 4.47% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24569789 7.02% 61.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 38589030 11.03% 72.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15690779 4.49% 77.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 12536762 3.58% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3989777 1.14% 81.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63870181 18.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 164951201 45.61% 45.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 21852654 6.04% 51.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15621060 4.32% 55.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24569981 6.79% 62.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 38586382 10.67% 73.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15690881 4.34% 77.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12539815 3.47% 81.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3986839 1.10% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 63866367 17.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 349762998 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369327 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.781991 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85730052 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86245168 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158924333 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18491829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371616 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11931982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7013 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 968682189 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25467 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371616 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93247100 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12146615 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14284 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 169253997 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 74729386 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 966801753 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1559 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25162616 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40511587 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7290496 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 666571567 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1151541399 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114502328 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 37039070 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 361665180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.357145 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.690256 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85732697 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98146269 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158921683 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18492948 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 371583 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11928940 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7011 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 968666226 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25451 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 371583 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93249960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12380390 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15406 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 169252258 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86395583 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 966785843 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1367 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25166874 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 51736906 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7729074 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 666569704 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1151545318 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114509565 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 37035752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27604409 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1367 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 27602546 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 87953522 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 245057905 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 102624371 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35358842 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4732178 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 877945283 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 77 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 871653931 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 10631 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35563330 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10945081 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 349762998 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.492127 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.135671 # Number of insts issued each cycle +system.cpu.rename.skidInsts 87961020 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 245059340 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 102632582 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35344831 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4698812 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 877945756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 74 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 871651299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 10628 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35563800 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10965429 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 361665180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.410106 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.146787 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75990310 21.73% 21.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 61353138 17.54% 39.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 57501132 16.44% 55.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51071612 14.60% 70.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45054201 12.88% 83.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20633149 5.90% 89.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18143842 5.19% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10286820 2.94% 97.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9728794 2.78% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 87893149 24.30% 24.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 61352794 16.96% 41.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 57499290 15.90% 57.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51081168 14.12% 71.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45042350 12.45% 83.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20636672 5.71% 89.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18146014 5.02% 94.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10282367 2.84% 97.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9731376 2.69% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 349762998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 361665180 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3589530 19.39% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3586644 19.39% 19.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 19.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 19.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.39% # attempts to use FU when none available @@ -448,16 +458,16 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.39% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11797020 63.73% 83.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3124042 16.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11792491 63.74% 83.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3122167 16.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 505112247 57.95% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7850 0.00% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 505104722 57.95% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7855 0.00% 57.95% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13300875 1.53% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826555 0.44% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13297886 1.53% 59.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826557 0.44% 59.91% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued @@ -482,82 +492,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 244260355 28.02% 88.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 101804963 11.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 244265808 28.02% 88.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 101807385 11.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 871653931 # Type of FU issued -system.cpu.iq.rate 2.490377 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18510592 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021236 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2042303381 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 876767032 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 835994185 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69288702 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36778589 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34169846 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855062076 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35101171 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65597395 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 871651299 # Type of FU issued +system.cpu.iq.rate 2.408347 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18501302 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2054197029 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 876768256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 835988686 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 69282679 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36778231 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34166819 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 855053167 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35098158 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 65597237 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7547308 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5161 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37165 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4323171 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7548743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37089 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4331382 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2714 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4324 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2716 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4307 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371616 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4020858 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 620837 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 966016228 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16689 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 245057905 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 102624371 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 77 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 538553 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 95932 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37165 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128220 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 15953 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 144173 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 871032011 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 243870521 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 621920 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 371583 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4257057 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 608088 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 966007295 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16673 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 245059340 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 102632582 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 74 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 538259 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83477 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37089 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 128251 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 15992 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 144243 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 871026557 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 243876094 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 624742 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88070868 # number of nop insts executed -system.cpu.iew.exec_refs 345545074 # number of memory reference insts executed -system.cpu.iew.exec_branches 127159833 # Number of branches executed -system.cpu.iew.exec_stores 101674553 # Number of stores executed -system.cpu.iew.exec_rate 2.488600 # Inst execution rate -system.cpu.iew.wb_sent 870625746 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 870164031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 525002727 # num instructions producing a value -system.cpu.iew.wb_consumers 821961915 # num instructions consuming a value -system.cpu.iew.wb_rate 2.486120 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.638719 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 31814193 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 88061465 # number of nop insts executed +system.cpu.iew.exec_refs 345550079 # number of memory reference insts executed +system.cpu.iew.exec_branches 127153600 # Number of branches executed +system.cpu.iew.exec_stores 101673985 # Number of stores executed +system.cpu.iew.exec_rate 2.406621 # Inst execution rate +system.cpu.iew.wb_sent 870617196 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 870155505 # cumulative count of insts written-back +system.cpu.iew.wb_producers 525001925 # num instructions producing a value +system.cpu.iew.wb_consumers 821956019 # num instructions consuming a value +system.cpu.iew.wb_rate 2.404215 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.638723 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 31805123 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 138436 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 345634386 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.686618 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.059575 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 138464 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 357537289 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.597177 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.046569 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 109896722 31.80% 31.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 81929003 23.70% 55.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 29947850 8.66% 64.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19779542 5.72% 69.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17820096 5.16% 75.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7961930 2.30% 77.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3040428 0.88% 78.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3978823 1.15% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71279992 20.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121797842 34.07% 34.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 81929888 22.92% 56.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29949089 8.38% 65.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19779772 5.53% 70.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17819434 4.98% 75.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7962754 2.23% 78.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3039675 0.85% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3979990 1.11% 80.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71278845 19.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 345634386 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 357537289 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,127 +613,127 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 71279992 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1232135077 # The number of ROB reads -system.cpu.rob.rob_writes 1924934508 # The number of ROB writes -system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 245828 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 71278845 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1244030057 # The number of ROB reads +system.cpu.rob.rob_writes 1924915650 # The number of ROB writes +system.cpu.timesIdled 3145 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 264042 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.415499 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.415499 # CPI: Total CPI of All Threads -system.cpu.ipc 2.406745 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.406745 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1104178752 # number of integer regfile reads -system.cpu.int_regfile_writes 635595888 # number of integer regfile writes -system.cpu.fp_regfile_reads 36406844 # number of floating regfile reads -system.cpu.fp_regfile_writes 24680552 # number of floating regfile writes +system.cpu.cpi 0.429650 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.429650 # CPI: Total CPI of All Threads +system.cpu.ipc 2.327477 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.327477 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1104175341 # number of integer regfile reads +system.cpu.int_regfile_writes 635597274 # number of integer regfile writes +system.cpu.fp_regfile_reads 36400867 # number of floating regfile reads +system.cpu.fp_regfile_writes 24677538 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776667 # number of replacements -system.cpu.dcache.tags.tagsinuse 4091.035125 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 273851714 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780763 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 350.748837 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 374790500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4091.035125 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998788 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998788 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 776666 # number of replacements +system.cpu.dcache.tags.tagsinuse 4090.964650 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 273860034 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780762 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 350.759942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 396630500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4090.964650 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998771 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1013 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2527 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 553380005 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 553380005 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 176443372 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 176443372 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408329 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408329 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 553391630 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 553391630 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 176451824 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176451824 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97408197 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97408197 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 273851701 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 273851701 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 273851701 # number of overall hits -system.cpu.dcache.overall_hits::total 273851701 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1555036 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1555036 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 892871 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 892871 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2447907 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2447907 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2447907 # number of overall misses -system.cpu.dcache.overall_misses::total 2447907 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84877374000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84877374000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62367572330 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62367572330 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 147244946330 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 147244946330 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 147244946330 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 147244946330 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177998408 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177998408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 273860021 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 273860021 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 273860021 # number of overall hits +system.cpu.dcache.overall_hits::total 273860021 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1552397 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1552397 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 893003 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 893003 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2445400 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2445400 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2445400 # number of overall misses +system.cpu.dcache.overall_misses::total 2445400 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 96567477000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 96567477000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 65926918364 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 65926918364 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 162494395364 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 162494395364 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 162494395364 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 162494395364 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 178004221 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 178004221 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 276299608 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 276299608 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 276299608 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 276299608 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008736 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008736 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008860 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008860 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008860 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008860 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54582.256617 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54582.256617 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69850.596928 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69850.596928 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60151.364545 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60151.364545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60151.364545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60151.364545 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 63758 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 349 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 520 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.358166 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 122.611538 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88567 # number of writebacks -system.cpu.dcache.writebacks::total 88567 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842892 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 842892 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824252 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 824252 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1667144 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1667144 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1667144 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1667144 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712144 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712144 # number of ReadReq MSHR misses +system.cpu.dcache.demand_accesses::cpu.data 276305421 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 276305421 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 276305421 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 276305421 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008721 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008721 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009084 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009084 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008850 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008850 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008850 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008850 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62205.400423 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62205.400423 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73826.088338 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73826.088338 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66449.004402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66449.004402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66449.004402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66449.004402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25561 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 192860 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 308 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.990260 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 371.599229 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88570 # number of writebacks +system.cpu.dcache.writebacks::total 88570 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840254 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 840254 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824384 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 824384 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1664638 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1664638 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1664638 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1664638 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712143 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712143 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68619 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 68619 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780763 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780763 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780763 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780763 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24487996000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24487996000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5721430497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5721430497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30209426497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30209426497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30209426497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 30209426497 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 780762 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780762 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780762 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780762 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30603980500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30603980500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6049145998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6049145998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36653126498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36653126498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36653126498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36653126498 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses @@ -732,212 +742,212 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34386.298277 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34386.298277 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83379.683426 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83379.683426 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38692.185077 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38692.185077 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38692.185077 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38692.185077 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4616 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.876124 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 116210243 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18384.787692 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42974.487568 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42974.487568 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88155.554555 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88155.554555 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46945.325846 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46945.325846 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46945.325846 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46945.325846 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 4618 # number of replacements +system.cpu.icache.tags.tagsinuse 1647.809929 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 116209747 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6323 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18378.894038 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.876124 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804627 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804627 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.809929 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804595 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1545 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 232443303 # Number of tag accesses -system.cpu.icache.tags.data_accesses 232443303 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 116210243 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 116210243 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 116210243 # number of demand (read+write) hits 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(read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 116218000 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 116218000 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43066.864573 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43066.864573 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43066.864573 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43066.864573 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43066.864573 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43066.864573 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 726 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46351.144917 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46351.144917 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46351.144917 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46351.144917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46351.144917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46351.144917 # average overall miss latency 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number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1926 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1926 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1926 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1926 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6322 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6322 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6322 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6322 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6322 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 265463000 # number of ReadReq MSHR miss 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MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1929 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1929 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6324 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6324 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6324 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6324 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6324 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6324 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 282422000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 282422000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 282422000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 282422000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 282422000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 282422000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41990.351155 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41990.351155 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41990.351155 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41990.351155 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41990.351155 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41990.351155 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259809 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32656.861347 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1275789 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292577 # Sample count of references to valid blocks. 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of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -948,128 +958,128 @@ system.cpu.l2cache.writebacks::writebacks 66682 # n system.cpu.l2cache.writebacks::total 66682 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66625 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66625 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66626 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66626 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2719 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2719 # number of ReadCleanReq MSHR misses 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-system.cpu.toL2Bus.snoop_filter.hit_single_requests 781283 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970956 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970956 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.429949 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312898 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312898 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370733 # mshr miss rate for demand accesses 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of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2008 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2012 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 718465 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881227 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 718466 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881222 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 68619 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 68619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712144 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338193 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2355452 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55637120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56337088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259809 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6324 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712143 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2355455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55637248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56337472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259808 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267648 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 1046894 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001918 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043754 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001922 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043797 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1044886 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2008 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1044882 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2012 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1046894 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877367000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 877373000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9481500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9484500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171144500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 549975 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257802 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 1171143000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 549969 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257797 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225548 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225546 # Transaction distribution system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution -system.membus.trans_dist::CleanEvict 191120 # Transaction distribution -system.membus.trans_dist::ReadExReq 66625 # Transaction distribution -system.membus.trans_dist::ReadExResp 66625 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225548 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842148 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22966720 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 191115 # Transaction distribution +system.membus.trans_dist::ReadExReq 66626 # Transaction distribution +system.membus.trans_dist::ReadExResp 66626 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225546 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842141 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842141 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22966656 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292173 # Request fanout histogram +system.membus.snoop_fanout::samples 292172 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292173 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292172 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292173 # Request fanout histogram -system.membus.reqLayer0.occupancy 877549500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292172 # Request fanout histogram +system.membus.reqLayer0.occupancy 877590500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551106000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551176250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini index 4149684ba..bcc7e805c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout index 99e686564..2e501adb4 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:40:10 -gem5 executing on e108600-lin, pid 23109 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:05:24 +gem5 executing on e108600-lin, pid 17596 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second @@ -650,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 512588680500 because target called exit() +Exiting @ tick 525654485500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 228ad0113..d38edd9f8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.512877 # Number of seconds simulated -sim_ticks 512876814500 # Number of ticks simulated -final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.525654 # Number of seconds simulated +sim_ticks 525654485500 # Number of ticks simulated +final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169706 # Simulator instruction rate (inst/s) -host_op_rate 208931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 135858559 # Simulator tick rate (ticks/s) -host_mem_usage 281524 # Number of bytes of host memory used -host_seconds 3775.08 # Real time elapsed on the host +host_inst_rate 213828 # Simulator instruction rate (inst/s) +host_op_rate 263250 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175444467 # Simulator tick rate (ticks/s) +host_mem_usage 278324 # Number of bytes of host memory used +host_seconds 2996.13 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory @@ -26,64 +26,64 @@ system.physmem.num_reads::cpu.data 288664 # Nu system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291229 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18285 # Per bank write bursts -system.physmem.perBankRdBursts::1 18130 # Per bank write bursts -system.physmem.perBankRdBursts::2 18219 # Per bank write bursts -system.physmem.perBankRdBursts::3 18177 # Per bank write bursts +system.physmem.perBankRdBursts::0 18281 # Per bank write bursts +system.physmem.perBankRdBursts::1 18133 # Per bank write bursts +system.physmem.perBankRdBursts::2 18221 # Per bank write bursts +system.physmem.perBankRdBursts::3 18176 # Per bank write bursts system.physmem.perBankRdBursts::4 18285 # Per bank write bursts -system.physmem.perBankRdBursts::5 18413 # Per bank write bursts -system.physmem.perBankRdBursts::6 18173 # Per bank write bursts -system.physmem.perBankRdBursts::7 17985 # Per bank write bursts -system.physmem.perBankRdBursts::8 18026 # Per bank write bursts -system.physmem.perBankRdBursts::9 18055 # Per bank write bursts -system.physmem.perBankRdBursts::10 18102 # Per bank write bursts -system.physmem.perBankRdBursts::11 18206 # Per bank write bursts -system.physmem.perBankRdBursts::12 18220 # Per bank write bursts -system.physmem.perBankRdBursts::13 18274 # Per bank write bursts -system.physmem.perBankRdBursts::14 18073 # Per bank write bursts -system.physmem.perBankRdBursts::15 18262 # Per bank write bursts +system.physmem.perBankRdBursts::5 18412 # Per bank write bursts +system.physmem.perBankRdBursts::6 18178 # Per bank write bursts +system.physmem.perBankRdBursts::7 17990 # Per bank write bursts +system.physmem.perBankRdBursts::8 18034 # Per bank write bursts +system.physmem.perBankRdBursts::9 18056 # Per bank write bursts +system.physmem.perBankRdBursts::10 18101 # Per bank write bursts +system.physmem.perBankRdBursts::11 18200 # Per bank write bursts +system.physmem.perBankRdBursts::12 18218 # Per bank write bursts +system.physmem.perBankRdBursts::13 18271 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18258 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts -system.physmem.perBankWrBursts::1 4098 # Per bank write bursts -system.physmem.perBankWrBursts::2 4134 # Per bank write bursts +system.physmem.perBankWrBursts::1 4099 # Per bank write bursts +system.physmem.perBankWrBursts::2 4135 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4223 # Per bank write bursts +system.physmem.perBankWrBursts::4 4224 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4092 # Per bank write bursts -system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4095 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4138 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 512876719500 # Total gap between requests +system.physmem.totGap 525654384500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,91 +194,101 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads -system.physmem.totQLat 2756382250 # Total ticks spent queuing -system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads +system.physmem.totQLat 15538679500 # Total ticks spent queuing +system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers +system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.busUtil 0.34 # Data bus utilization in percentage system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing -system.physmem.readRowHits 194946 # Number of row buffer hits during reads -system.physmem.writeRowHits 51576 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes -system.physmem.avgGap 1435314.77 # Average gap between requests -system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.111511 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states -system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.035798 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states -system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 147261658 # Number of BP lookups +system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing +system.physmem.readRowHits 202495 # Number of row buffer hits during reads +system.physmem.writeRowHits 51707 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes +system.physmem.avgGap 1471073.79 # Average gap between requests +system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ) +system.physmem_0.averagePower 407.411950 # Core power per rank (mW) +system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states +system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ) +system.physmem_1.averagePower 406.546781 # Core power per rank (mW) +system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states +system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 147261657 # Number of BP lookups system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups -system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits +system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups +system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. @@ -288,7 +298,7 @@ system.cpu.branchPred.indirectHits 15988941 # Nu system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -318,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -348,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -378,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,16 +419,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1025753629 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1051308971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.601101 # CPI: cycles per instruction -system.cpu.ipc 0.624570 # IPC: instructions per cycle +system.cpu.cpi 1.640991 # CPI: cycles per instruction +system.cpu.ipc 0.609388 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction @@ -454,28 +464,28 @@ system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778100 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits @@ -500,14 +510,14 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -532,14 +542,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -566,16 +576,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057 system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -586,70 +596,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24885 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses -system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits -system.cpu.icache.overall_hits::total 257789646 # number of overall hits +system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses +system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits +system.cpu.icache.overall_hits::total 257789639 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses system.cpu.icache.overall_misses::total 26637 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -664,48 +674,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 26637 system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 258837 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits @@ -734,18 +744,18 @@ system.cpu.l2cache.demand_misses::total 291260 # nu system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses system.cpu.l2cache.overall_misses::total 291260 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) @@ -774,18 +784,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.360099 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -816,18 +826,18 @@ system.cpu.l2cache.demand_mshr_misses::total 291230 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses @@ -840,25 +850,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution @@ -898,7 +908,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 225138 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution system.membus.trans_dist::CleanEvict 190702 # Transaction distribution @@ -921,9 +931,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 291229 # Request fanout histogram -system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 2ff40d14a..155d03811 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 0920df90d..4ad08cdbb 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:20:09 -gem5 executing on e108600-lin, pid 12407 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:55:26 +gem5 executing on e108600-lin, pid 17505 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -650,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 326731324000 because target called exit() +Exiting @ tick 339012932000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2975218ad..0a89473ad 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.327896 # Number of seconds simulated -sim_ticks 327895638000 # Number of ticks simulated -final_tick 327895638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.339013 # Number of seconds simulated +sim_ticks 339012932000 # Number of ticks simulated +final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125299 # Simulator instruction rate (inst/s) -host_op_rate 154259 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64130088 # Simulator tick rate (ticks/s) -host_mem_usage 277300 # Number of bytes of host memory used -host_seconds 5112.98 # Real time elapsed on the host +host_inst_rate 140345 # Simulator instruction rate (inst/s) +host_op_rate 172783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74266222 # Simulator tick rate (ticks/s) +host_mem_usage 275384 # Number of bytes of host memory used +host_seconds 4564.83 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 266368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48003200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12980224 # Number of bytes read from this memory -system.physmem.bytes_read::total 61249792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 266368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 266368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244096 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202816 # Number of read requests responded to by this memory -system.physmem.num_reads::total 957028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66314 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66314 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 812356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146397800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 39586449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186796605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812356 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812356 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12943435 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12943435 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12943435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146397800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 39586449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 199740040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 957029 # Number of read requests accepted -system.physmem.writeReqs 66314 # Number of write requests accepted -system.physmem.readBursts 957029 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66314 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61231232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue -system.physmem.bytesWritten 4237440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61249856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 72 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 269632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48043328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12965504 # Number of bytes read from this memory +system.physmem.bytes_read::total 61278464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 269632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 269632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4245696 # Number of bytes written to this memory +system.physmem.bytes_written::total 4245696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4213 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750677 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202586 # Number of read requests responded to by this memory +system.physmem.num_reads::total 957476 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66339 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66339 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 795344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141715325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 38244866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 180755535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 795344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 795344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12523699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12523699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12523699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 795344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141715325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 38244866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193279235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 957477 # Number of read requests accepted +system.physmem.writeReqs 66339 # Number of write requests accepted +system.physmem.readBursts 957477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66339 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61258752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19776 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61278528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4245696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 309 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 54 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19913 # Per bank write bursts -system.physmem.perBankRdBursts::1 19609 # Per bank write bursts -system.physmem.perBankRdBursts::2 657177 # Per bank write bursts -system.physmem.perBankRdBursts::3 20974 # Per bank write bursts -system.physmem.perBankRdBursts::4 19738 # Per bank write bursts -system.physmem.perBankRdBursts::5 20841 # Per bank write bursts -system.physmem.perBankRdBursts::6 19544 # Per bank write bursts -system.physmem.perBankRdBursts::7 20056 # Per bank write bursts -system.physmem.perBankRdBursts::8 19527 # Per bank write bursts -system.physmem.perBankRdBursts::9 20071 # Per bank write bursts -system.physmem.perBankRdBursts::10 19467 # Per bank write bursts -system.physmem.perBankRdBursts::11 19786 # Per bank write bursts -system.physmem.perBankRdBursts::12 19618 # Per bank write bursts -system.physmem.perBankRdBursts::13 21115 # Per bank write bursts -system.physmem.perBankRdBursts::14 19501 # Per bank write bursts -system.physmem.perBankRdBursts::15 19801 # Per bank write bursts -system.physmem.perBankWrBursts::0 4241 # Per bank write bursts -system.physmem.perBankWrBursts::1 4104 # Per bank write bursts -system.physmem.perBankWrBursts::2 4141 # Per bank write bursts -system.physmem.perBankWrBursts::3 4151 # Per bank write bursts -system.physmem.perBankWrBursts::4 4245 # Per bank write bursts -system.physmem.perBankWrBursts::5 4233 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankRdBursts::0 19910 # Per bank write bursts +system.physmem.perBankRdBursts::1 19533 # Per bank write bursts +system.physmem.perBankRdBursts::2 657271 # Per bank write bursts +system.physmem.perBankRdBursts::3 20982 # Per bank write bursts +system.physmem.perBankRdBursts::4 19710 # Per bank write bursts +system.physmem.perBankRdBursts::5 21143 # Per bank write bursts +system.physmem.perBankRdBursts::6 19634 # Per bank write bursts +system.physmem.perBankRdBursts::7 20055 # Per bank write bursts +system.physmem.perBankRdBursts::8 19495 # Per bank write bursts +system.physmem.perBankRdBursts::9 20079 # Per bank write bursts +system.physmem.perBankRdBursts::10 19428 # Per bank write bursts +system.physmem.perBankRdBursts::11 19728 # Per bank write bursts +system.physmem.perBankRdBursts::12 19649 # Per bank write bursts +system.physmem.perBankRdBursts::13 21208 # Per bank write bursts +system.physmem.perBankRdBursts::14 19490 # Per bank write bursts +system.physmem.perBankRdBursts::15 19853 # Per bank write bursts +system.physmem.perBankWrBursts::0 4286 # Per bank write bursts +system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.perBankWrBursts::2 4145 # Per bank write bursts +system.physmem.perBankWrBursts::3 4153 # Per bank write bursts +system.physmem.perBankWrBursts::4 4249 # Per bank write bursts +system.physmem.perBankWrBursts::5 4230 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::10 4094 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4151 # Per bank write bursts +system.physmem.perBankWrBursts::15 4149 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 327895627500 # Total gap between requests +system.physmem.totGap 339012921500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 957029 # Read request sizes (log2) +system.physmem.readPktSize::6 957477 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66314 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 765529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 621 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66339 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 764538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,175 +149,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming 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req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 194181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 337.148207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.280987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 364.158297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 64676 33.31% 33.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60636 31.23% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15729 8.10% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3217 1.66% 74.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3574 1.84% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2317 1.19% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2364 1.22% 78.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21831 11.24% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19837 10.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 194181 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 177.226065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.842577 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1813.556545 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 3969 99.47% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 4 0.10% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 2 0.05% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-32767 2 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::86016-90111 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.593985 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.513577 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.886226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3332 83.51% 83.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 5 0.13% 83.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 452 11.33% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 50 1.25% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 19 0.48% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 17 0.43% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.25% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 19 0.48% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.30% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 15 0.38% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.40% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.38% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 9 0.23% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.13% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.10% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.08% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 3 0.08% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3990 # Writes before turning the bus around for reads -system.physmem.totQLat 12587538724 # Total ticks spent queuing -system.physmem.totMemAccLat 30526376224 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4783690000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13156.72 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 195212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 335.517735 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.597798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.506182 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 64341 32.96% 32.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60661 31.07% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15753 8.07% 72.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3211 1.64% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3578 1.83% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2458 1.26% 76.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2478 1.27% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34211 17.53% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8521 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 195212 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3994 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 204.692539 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.349556 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2360.542955 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3971 99.42% 99.42% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 10 0.25% 99.67% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 5 0.13% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 1 0.03% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-32767 1 0.03% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::69632-73727 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::98304-102399 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3994 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3994 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.589634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.506417 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.926291 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3368 84.33% 84.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 17 0.43% 84.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 396 9.91% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 46 1.15% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.60% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.43% 96.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.53% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.45% 97.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 15 0.38% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.43% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.33% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 10 0.25% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.18% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 8 0.20% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 8 0.20% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 4 0.10% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3994 # Writes before turning the bus around for reads +system.physmem.totQLat 27473404757 # Total ticks spent queuing +system.physmem.totMemAccLat 45420304757 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4785840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28702.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31906.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 186.74 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 186.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 12.94 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47452.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 180.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.51 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 180.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.56 # Data bus utilization in percentage -system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing -system.physmem.readRowHits 805843 # Number of row buffer hits during reads -system.physmem.writeRowHits 22921 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.60 # Row buffer hit rate for writes -system.physmem.avgGap 320416.15 # Average gap between requests -system.physmem.pageHitRate 81.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 934317720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 509796375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6223237800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216334800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 220944760020 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2925699000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 253170624435 # Total energy per rank (pJ) -system.physmem_0.averagePower 772.109253 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3595093339 # Time in different power states -system.physmem_0.memoryStateTime::REF 10949120000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 313351421161 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 533690640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 291200250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1239209400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88116969465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 119441319000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 231251573475 # Total energy per rank (pJ) -system.physmem_1.averagePower 705.261391 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 198129163855 # Time in different power states -system.physmem_1.memoryStateTime::REF 10949120000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 118816573145 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174659739 # Number of BP lookups -system.cpu.branchPred.condPredicted 119113225 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015668 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720974 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67755362 # Number of BTB hits +system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing +system.physmem.readRowHits 805066 # Number of row buffer hits during reads +system.physmem.writeRowHits 23137 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.91 # Row buffer hit rate for writes +system.physmem.avgGap 331126.81 # Average gap between requests +system.physmem.pageHitRate 80.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 894020820 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 475164360 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5699412180 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174541140 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27331811520.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14462317590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 674820000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 138340924320 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 704060640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 673701120.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 189477322380 # Total energy per rank (pJ) +system.physmem_0.averagePower 558.908824 # Core power per rank (mW) +system.physmem_0.totalIdleTime 305437641889 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 528629764 # Time in different power states +system.physmem_0.memoryStateTime::REF 11569144000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 223118500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1833570381 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21477516347 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 303380953008 # Time in different power states +system.physmem_1.actEnergy 499878540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 265665180 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134760200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171330840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 25420895760.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7011060990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1362065280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 70491607590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 31027049280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 25487678070 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 162872491950 # Total energy per rank (pJ) +system.physmem_1.averagePower 480.431501 # Core power per rank (mW) +system.physmem_1.totalIdleTime 320089357075 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2604072271 # Time in different power states +system.physmem_1.memoryStateTime::REF 10809446000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 84703185250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 80799625521 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5510033904 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 154586569054 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174656775 # Number of BP lookups +system.cpu.branchPred.condPredicted 119110803 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015685 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96721345 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67754534 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.052398 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18785155 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716286 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16701799 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14487 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279501 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 70.051274 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18785121 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299599 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16716580 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16702336 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14244 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279516 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -347,7 +359,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -377,7 +389,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -407,7 +419,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -438,85 +450,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 655791277 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678025865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 34353189 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824276690 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174659739 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103242316 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 616975428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 34354212 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824273790 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174656775 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103241991 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 639159762 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068079 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2457 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3170 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247740649 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12515 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 655368010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.551156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.253828 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3206 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247740942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12520 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 677553693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.500365 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.263651 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 193301276 29.50% 29.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148337850 22.63% 52.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72946568 11.13% 63.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240782316 36.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 215486043 31.80% 31.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148340760 21.89% 53.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72943473 10.77% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240783417 35.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 655368010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.266334 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.256919 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75112130 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 236493276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277761287 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61980307 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021010 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20809608 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13112 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924575224 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11804312 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021010 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118055519 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 135785787 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 212608 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 294557237 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102735849 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906541412 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891100 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27959034 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218150 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49337765 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 468731 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980926815 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4318009248 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001835221 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457086 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 677553693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257596 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215697 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75112537 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258679606 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277758053 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61982472 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021025 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20810112 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13117 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924576668 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11804380 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021025 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118056358 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 157938220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 213059 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 294555904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102769127 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906541450 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6890856 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27990855 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2220094 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49338949 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 500517 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980921468 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318014727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001837715 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106148585 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6844 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6835 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138814111 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271882035 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160585921 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6159068 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12159693 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899827224 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12580 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860029296 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216848 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111114846 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244387313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 655368010 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.312285 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.094624 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106143238 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6838 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138815476 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271882151 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160587217 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6164479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12153288 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899827421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860030622 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216880 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111115045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244388609 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 677553693 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.269317 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101593 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 192710599 29.40% 29.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182406257 27.83% 57.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 175554116 26.79% 84.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 92275656 14.08% 98.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12419071 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 214894884 31.72% 31.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182407403 26.92% 58.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 175555467 25.91% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 92273782 13.62% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12419846 1.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -524,9 +536,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 655368010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66605310 24.62% 24.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66603323 24.62% 24.62% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available @@ -555,13 +567,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 134121363 49.58% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69112589 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 134116736 49.58% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69116750 25.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413090005 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187656 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413090046 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187659 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -583,88 +595,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550150 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478194 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 266665504 31.01% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 157232585 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 266665907 31.01% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 157233466 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860029296 # Type of FU issued -system.cpu.iq.rate 1.311438 # Inst issue rate -system.cpu.iq.fu_busy_cnt 270494293 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314518 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2597595667 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980331886 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820082893 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 57542076 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued +system.cpu.iq.rate 1.268433 # Inst issue rate +system.cpu.iq.fu_busy_cnt 270491840 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2619781164 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 57542493 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878673 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1098503163 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32020426 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13986768 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1098501615 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32020847 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19641097 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18820 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31605425 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 120 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18827 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31606721 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17201 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918912 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17820 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021010 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10590461 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6281 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899849934 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021025 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10591534 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6199 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899849877 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271882035 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160585921 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6840 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 959 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3423 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18820 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295129 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290187 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585316 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850173752 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263373804 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271882151 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160587217 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 967 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18827 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295145 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3289956 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585101 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850175089 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263374398 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855533 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10130 # number of nop insts executed -system.cpu.iew.exec_refs 416063188 # number of memory reference insts executed -system.cpu.iew.exec_branches 143381327 # Number of branches executed -system.cpu.iew.exec_stores 152689384 # Number of stores executed -system.cpu.iew.exec_rate 1.296409 # Inst execution rate -system.cpu.iew.wb_sent 846297655 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844961566 # cumulative count of insts written-back -system.cpu.iew.wb_producers 487343298 # num instructions producing a value -system.cpu.iew.wb_consumers 808106626 # num instructions consuming a value -system.cpu.iew.wb_rate 1.288461 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.603068 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103169122 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9874 # number of nop insts executed +system.cpu.iew.exec_refs 416064413 # number of memory reference insts executed +system.cpu.iew.exec_branches 143381564 # Number of branches executed +system.cpu.iew.exec_stores 152690015 # Number of stores executed +system.cpu.iew.exec_rate 1.253898 # Inst execution rate +system.cpu.iew.wb_sent 846298256 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844962326 # cumulative count of insts written-back +system.cpu.iew.wb_producers 487342605 # num instructions producing a value +system.cpu.iew.wb_consumers 808106527 # num instructions consuming a value +system.cpu.iew.wb_rate 1.246210 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.603067 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103169288 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002654 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 640787345 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.230876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.070419 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002671 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 662973012 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.047483 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 350447626 54.69% 54.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137241088 21.42% 76.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51341072 8.01% 84.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28220230 4.40% 88.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14380949 2.24% 90.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774505 2.31% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871971 1.23% 94.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561231 1.02% 95.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29948673 4.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 372633677 56.21% 56.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137240232 20.70% 76.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51341106 7.74% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28220443 4.26% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14381462 2.17% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774618 2.23% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871678 1.19% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561077 0.99% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29948719 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 640787345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 662973012 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -710,82 +722,82 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29948673 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1502729113 # The number of ROB reads -system.cpu.rob.rob_writes 1798382436 # The number of ROB writes -system.cpu.timesIdled 10485 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 423267 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29948719 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1524914900 # The number of ROB reads +system.cpu.rob.rob_writes 1798382781 # The number of ROB writes +system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 472172 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.023635 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.023635 # CPI: Total CPI of All Threads -system.cpu.ipc 0.976910 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.976910 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868461212 # number of integer regfile reads -system.cpu.int_regfile_writes 500699124 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616064 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959493 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322386264 # number of cc regfile reads -system.cpu.cc_regfile_writes 369207629 # number of cc regfile writes -system.cpu.misc_regfile_reads 606832888 # number of misc regfile reads +system.cpu.cpi 1.058342 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.058342 # CPI: Total CPI of All Threads +system.cpu.ipc 0.944874 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944874 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868463326 # number of integer regfile reads +system.cpu.int_regfile_writes 500698648 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616063 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959490 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322389826 # number of cc regfile reads +system.cpu.cc_regfile_writes 369207773 # number of cc regfile writes +system.cpu.misc_regfile_reads 606833337 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756458 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.912011 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371050492 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756970 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.586336 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 274880000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.912011 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999828 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999828 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756453 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.911144 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371050846 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756965 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.586709 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 285699000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.911144 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751746846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751746846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243126867 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243126867 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907624 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907624 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751747893 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751747893 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243127355 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243127355 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907428 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907428 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371034491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371034491 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371037648 # number of overall hits -system.cpu.dcache.overall_hits::total 371037648 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1043853 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1043853 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371034783 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371034783 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371037940 # number of overall hits +system.cpu.dcache.overall_hits::total 371037940 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401348 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401348 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044049 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044049 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3445163 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3445163 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3445810 # number of overall misses -system.cpu.dcache.overall_misses::total 3445810 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 69278020000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 69278020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9882341350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9882341350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 168500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 168500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 79160361350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 79160361350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 79160361350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 79160361350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245528177 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245528177 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3445397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3445397 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3446044 # number of overall misses +system.cpu.dcache.overall_misses::total 3446044 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80462385500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80462385500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10017236850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10017236850 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90479622350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90479622350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90479622350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90479622350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245528703 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245528703 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -794,469 +806,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374479654 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374479654 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374483458 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374483458 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 374480180 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374480180 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374483984 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374483984 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008096 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008096 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9467.177227 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9467.177227 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22977.247042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22972.932736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22972.932736 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 322646 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4628 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 69.716076 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756458 # number of writebacks -system.cpu.dcache.writebacks::total 2756458 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365828 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365828 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322833 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 322833 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 688661 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 688661 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 688661 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 688661 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035482 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035482 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721020 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721020 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9594.604133 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9594.604133 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26261.015015 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26256.084470 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 71 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 355259 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4691 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 75.732040 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2756453 # number of writebacks +system.cpu.dcache.writebacks::total 2756453 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365871 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 365871 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323013 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323013 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 688884 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 688884 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 688884 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 688884 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5940509850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5561000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5561000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 70043445850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 70043445850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 70049006850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 70049006850 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756513 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756513 # number of demand (read+write) MSHR misses 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(read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81183120850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 81183120850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31492.755033 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31492.755033 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8239.036157 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8239.036157 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8661.993769 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8661.993769 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25410.264839 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25410.264839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25406.365010 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25406.365010 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8264.530273 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8264.530273 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9279.595016 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9279.595016 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1979522 # number of replacements -system.cpu.icache.tags.tagsinuse 510.874726 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245757404 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 510.550232 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245757624 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.117895 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 264413500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.874726 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997802 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy +system.cpu.icache.tags.avg_refs 124.118006 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 275112500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.550232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997168 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997168 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id 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accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247740617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247740617 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247740617 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247740617 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247740617 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 497462038 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497462038 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 245757684 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245757684 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245757684 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245757684 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245757684 # number of overall hits +system.cpu.icache.overall_hits::total 245757684 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1983224 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1983224 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1983224 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1983224 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1983224 # number of overall misses +system.cpu.icache.overall_misses::total 1983224 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16215368926 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16215368926 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16215368926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16215368926 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16215368926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16215368926 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247740908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247740908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247740908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247740908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247740908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247740908 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses 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overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70376.529625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70376.529625 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003033 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003033 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002129 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002129 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368503 # miss rate for ReadSharedReq accesses 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83388.849348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85035.583008 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85035.583008 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85042.132660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85042.132660 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3678 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 66314 # number of writebacks -system.cpu.l2cache.writebacks::total 66314 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 742 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 742 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 3567 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 66339 # number of writebacks +system.cpu.l2cache.writebacks::total 66339 # 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ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749290 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4214 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 750677 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 754891 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4214 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 750677 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202675 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 957566 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20310287954 # number of HardPFReq MSHR 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cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59387200500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59713345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 326144500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59387200500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80023632954 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 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miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002128 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for demand accesses 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overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9473332 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736180 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 642769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202146 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9473354 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736191 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 89 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 88 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016330 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801859 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 230920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 258553 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4016341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 802291 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000023 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 230984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 255300 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 190 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036124 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270746 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14210509 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14210542 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606270912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 555960 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4255168 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5293139 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.121491 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.326697 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606270272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 552812 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4257792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5290002 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121634 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.326863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4650072 87.85% 87.85% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 643066 12.15% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4646559 87.84% 87.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 643442 12.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5293139 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9472646000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2970310996 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5290002 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9472652000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2970335495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135552978 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1254437 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 940010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 4135554975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1254990 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 940467 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 955666 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66314 # Transaction distribution -system.membus.trans_dist::CleanEvict 230920 # Transaction distribution -system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 1362 # Transaction distribution -system.membus.trans_dist::ReadExResp 1362 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 955667 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211465 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2211465 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65493888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65493888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 956088 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66339 # Transaction distribution +system.membus.trans_dist::CleanEvict 230984 # Transaction distribution +system.membus.trans_dist::UpgradeReq 190 # Transaction distribution +system.membus.trans_dist::ReadExReq 1387 # Transaction distribution +system.membus.trans_dist::ReadExResp 1387 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 956090 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2212465 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2212465 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65524096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65524096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957203 # Request fanout histogram +system.membus.snoop_fanout::samples 957667 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957203 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 957667 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957203 # Request fanout histogram -system.membus.reqLayer0.occupancy 1755655982 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 957667 # Request fanout histogram +system.membus.reqLayer0.occupancy 1758860478 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5035261795 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5031633569 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini index 4117f093b..46094eb94 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout index dcc24233a..a86af0918 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4306 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28063 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 60000593000 because target called exit() +Exiting @ tick 61709224000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 58628a22b..4a990b700 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060094 # Number of seconds simulated -sim_ticks 60093931000 # Number of ticks simulated -final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061709 # Number of seconds simulated +sim_ticks 61709224000 # Number of ticks simulated +final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 276952 # Simulator instruction rate (inst/s) -host_op_rate 276952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188189933 # Simulator tick rate (ticks/s) -host_mem_usage 264524 # Number of bytes of host memory used -host_seconds 319.33 # Real time elapsed on the host +host_inst_rate 242211 # Simulator instruction rate (inst/s) +host_op_rate 242211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 169006859 # Simulator tick rate (ticks/s) +host_mem_usage 262168 # Number of bytes of host memory used +host_seconds 365.13 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory -system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory -system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165736 # Number of read requests accepted -system.physmem.writeReqs 115250 # Number of write requests accepted -system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory +system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory +system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165740 # Number of read requests accepted +system.physmem.writeReqs 115251 # Number of write requests accepted +system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue +system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10345 # Per bank write bursts -system.physmem.perBankRdBursts::1 10388 # Per bank write bursts +system.physmem.perBankRdBursts::1 10387 # Per bank write bursts system.physmem.perBankRdBursts::2 10224 # Per bank write bursts -system.physmem.perBankRdBursts::3 10067 # Per bank write bursts +system.physmem.perBankRdBursts::3 10068 # Per bank write bursts system.physmem.perBankRdBursts::4 10353 # Per bank write bursts system.physmem.perBankRdBursts::5 10360 # Per bank write bursts system.physmem.perBankRdBursts::6 9794 # Per bank write bursts -system.physmem.perBankRdBursts::7 10229 # Per bank write bursts +system.physmem.perBankRdBursts::7 10230 # Per bank write bursts system.physmem.perBankRdBursts::8 10568 # Per bank write bursts system.physmem.perBankRdBursts::9 10626 # Per bank write bursts -system.physmem.perBankRdBursts::10 10567 # Per bank write bursts +system.physmem.perBankRdBursts::10 10568 # Per bank write bursts system.physmem.perBankRdBursts::11 10241 # Per bank write bursts -system.physmem.perBankRdBursts::12 10307 # Per bank write bursts -system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::12 10306 # Per bank write bursts +system.physmem.perBankRdBursts::13 10592 # Per bank write bursts system.physmem.perBankRdBursts::14 10494 # Per bank write bursts system.physmem.perBankRdBursts::15 10573 # Per bank write bursts system.physmem.perBankWrBursts::0 7166 # Per bank write bursts -system.physmem.perBankWrBursts::1 7280 # Per bank write bursts +system.physmem.perBankWrBursts::1 7281 # Per bank write bursts system.physmem.perBankWrBursts::2 7303 # Per bank write bursts -system.physmem.perBankWrBursts::3 7011 # Per bank write bursts -system.physmem.perBankWrBursts::4 7144 # Per bank write bursts -system.physmem.perBankWrBursts::5 7304 # Per bank write bursts +system.physmem.perBankWrBursts::3 7012 # Per bank write bursts +system.physmem.perBankWrBursts::4 7145 # Per bank write bursts +system.physmem.perBankWrBursts::5 7305 # Per bank write bursts system.physmem.perBankWrBursts::6 6890 # Per bank write bursts -system.physmem.perBankWrBursts::7 7170 # Per bank write bursts -system.physmem.perBankWrBursts::8 7244 # Per bank write bursts -system.physmem.perBankWrBursts::9 7072 # Per bank write bursts -system.physmem.perBankWrBursts::10 7215 # Per bank write bursts +system.physmem.perBankWrBursts::7 7164 # Per bank write bursts +system.physmem.perBankWrBursts::8 7246 # Per bank write bursts +system.physmem.perBankWrBursts::9 7071 # Per bank write bursts +system.physmem.perBankWrBursts::10 7213 # Per bank write bursts system.physmem.perBankWrBursts::11 7126 # Per bank write bursts system.physmem.perBankWrBursts::12 7072 # Per bank write bursts system.physmem.perBankWrBursts::13 7397 # Per bank write bursts -system.physmem.perBankWrBursts::14 7353 # Per bank write bursts +system.physmem.perBankWrBursts::14 7351 # Per bank write bursts system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60093907500 # Total gap between requests +system.physmem.totGap 61709200500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165736 # Read request sizes (log2) +system.physmem.readPktSize::6 165740 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115250 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115251 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6962 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,124 +194,134 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads -system.physmem.totQLat 1892978500 # Total ticks spent queuing -system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads +system.physmem.totQLat 3617300750 # Total ticks spent queuing +system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.34 # Data bus utilization in percentage -system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing -system.physmem.readRowHits 144145 # Number of row buffer hits during reads -system.physmem.writeRowHits 89685 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes -system.physmem.avgGap 213867.98 # Average gap between requests -system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ) -system.physmem_0.averagePower 711.117850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ) -system.physmem_1.averagePower 713.246634 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14696108 # Number of BP lookups -system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits +system.physmem.busUtil 2.28 # Data bus utilization in percentage +system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing +system.physmem.readRowHits 144262 # Number of row buffer hits during reads +system.physmem.writeRowHits 89468 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes +system.physmem.avgGap 219612.73 # Average gap between requests +system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ) +system.physmem_0.averagePower 393.299410 # Core power per rank (mW) +system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states +system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ) +system.physmem_1.averagePower 400.858918 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14696527 # Number of BP lookups +system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20579333 # DTB read hits -system.cpu.dtb.read_misses 95423 # DTB read misses +system.cpu.dtb.read_hits 20579387 # DTB read hits +system.cpu.dtb.read_misses 95377 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674756 # DTB read accesses -system.cpu.dtb.write_hits 14666035 # DTB write hits +system.cpu.dtb.read_accesses 20674764 # DTB read accesses +system.cpu.dtb.write_hits 14666029 # DTB write hits system.cpu.dtb.write_misses 8840 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674875 # DTB write accesses -system.cpu.dtb.data_hits 35245368 # DTB hits -system.cpu.dtb.data_misses 104263 # DTB misses +system.cpu.dtb.write_accesses 14674869 # DTB write accesses +system.cpu.dtb.data_hits 35245416 # DTB hits +system.cpu.dtb.data_misses 104217 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35349631 # DTB accesses -system.cpu.itb.fetch_hits 25649355 # ITB hits -system.cpu.itb.fetch_misses 5175 # ITB misses +system.cpu.dtb.data_accesses 35349633 # DTB accesses +system.cpu.itb.fetch_hits 25650137 # ITB hits +system.cpu.itb.fetch_misses 5179 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25654530 # ITB accesses +system.cpu.itb.fetch_accesses 25655316 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,16 +335,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120187862 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 123418448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359006 # CPI: cycles per instruction -system.cpu.ipc 0.735832 # IPC: instructions per cycle +system.cpu.cpi 1.395535 # CPI: cycles per instruction +system.cpu.ipc 0.716571 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -370,106 +380,106 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked -system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200806 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy +system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked +system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200809 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits -system.cpu.dcache.overall_hits::total 34648172 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses -system.cpu.dcache.overall_misses::total 341638 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits +system.cpu.dcache.overall_hits::total 34647996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses +system.cpu.dcache.overall_misses::total 341611 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168116 # number of writebacks -system.cpu.dcache.writebacks::total 168116 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 194 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136542 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136736 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136736 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136736 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136736 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61335 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61335 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168117 # number of writebacks +system.cpu.dcache.writebacks::total 168117 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136509 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136509 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 136706 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 136706 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 136706 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 136706 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61338 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61338 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204902 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204902 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204902 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204902 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2722762000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2722762000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994246500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994246500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13717008500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13717008500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13717008500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13717008500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3088657500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1033 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 801 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 156011 # number of overall misses +system.cpu.icache.overall_misses::total 156011 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2690499000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2690499000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2690499000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2690499000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2690499000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2690499000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25650137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25650137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25650137 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17245.572428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17245.572428 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153916 # number of writebacks -system.cpu.icache.writebacks::total 153916 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155965 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155965 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155965 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155965 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2362957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2362957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2362957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2362957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2362957000 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 135276 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31728.322423 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 547427 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168044 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.257641 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13928082000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 716.089195 # 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mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16245.578837 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16245.578837 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16245.578837 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135276 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135280 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34828 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution -system.membus.trans_dist::CleanEvict 15883 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34832 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution +system.membus.trans_dist::CleanEvict 15886 # Transaction distribution system.membus.trans_dist::ReadExReq 130908 # Transaction distribution system.membus.trans_dist::ReadExResp 130908 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165736 # Request fanout histogram +system.membus.snoop_fanout::samples 165740 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165736 # Request fanout histogram -system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +system.membus.snoop_fanout::total 165740 # Request fanout histogram +system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index d19d770e5..42d282c4a 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index e4880ad37..03964c60a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4308 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28054 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 22275010500 because target called exit() +Exiting @ tick 22819771500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 4f7e5b26f..6ed69f426 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022294 # Number of seconds simulated -sim_ticks 22293541500 # Number of ticks simulated -final_tick 22293541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022820 # Number of seconds simulated +sim_ticks 22819771500 # Number of ticks simulated +final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 223643 # Simulator instruction rate (inst/s) -host_op_rate 223643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62642230 # Simulator tick rate (ticks/s) -host_mem_usage 265292 # Number of bytes of host memory used -host_seconds 355.89 # Real time elapsed on the host +host_inst_rate 186519 # Simulator instruction rate (inst/s) +host_op_rate 186519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53476835 # Simulator tick rate (ticks/s) +host_mem_usage 263708 # Number of bytes of host memory used +host_seconds 426.72 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 413888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10171008 # Number of bytes read from this memory -system.physmem.bytes_read::total 10584896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 413888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 413888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 7372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158922 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165389 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115200 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18565377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 456231147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 474796523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18565377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18565377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 330714615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 330714615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 330714615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18565377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 456231147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 805511139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165389 # Number of read requests accepted -system.physmem.writeReqs 115200 # Number of write requests accepted -system.physmem.readBursts 165389 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115200 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10584320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7371392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10584896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7372800 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 414016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10170944 # Number of bytes read from this memory +system.physmem.bytes_read::total 10584960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 414016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 414016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 7372608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158921 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18142864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 445707530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 463850394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18142864 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18142864 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 323079835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 323079835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 323079835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18142864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 445707530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 786930228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165390 # Number of read requests accepted +system.physmem.writeReqs 115197 # Number of write requests accepted +system.physmem.readBursts 165390 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115197 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10584512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7370752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10584960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7372608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10310 # Per bank write bursts -system.physmem.perBankRdBursts::1 10350 # Per bank write bursts +system.physmem.perBankRdBursts::1 10353 # Per bank write bursts system.physmem.perBankRdBursts::2 10221 # Per bank write bursts -system.physmem.perBankRdBursts::3 10037 # Per bank write bursts +system.physmem.perBankRdBursts::3 10036 # Per bank write bursts system.physmem.perBankRdBursts::4 10349 # Per bank write bursts -system.physmem.perBankRdBursts::5 10325 # Per bank write bursts +system.physmem.perBankRdBursts::5 10326 # Per bank write bursts system.physmem.perBankRdBursts::6 9802 # Per bank write bursts -system.physmem.perBankRdBursts::7 10210 # Per bank write bursts -system.physmem.perBankRdBursts::8 10556 # Per bank write bursts -system.physmem.perBankRdBursts::9 10619 # Per bank write bursts +system.physmem.perBankRdBursts::7 10209 # Per bank write bursts +system.physmem.perBankRdBursts::8 10557 # Per bank write bursts +system.physmem.perBankRdBursts::9 10617 # Per bank write bursts system.physmem.perBankRdBursts::10 10516 # Per bank write bursts -system.physmem.perBankRdBursts::11 10224 # Per bank write bursts -system.physmem.perBankRdBursts::12 10277 # Per bank write bursts -system.physmem.perBankRdBursts::13 10556 # Per bank write bursts +system.physmem.perBankRdBursts::11 10223 # Per bank write bursts +system.physmem.perBankRdBursts::12 10279 # Per bank write bursts +system.physmem.perBankRdBursts::13 10557 # Per bank write bursts system.physmem.perBankRdBursts::14 10475 # Per bank write bursts system.physmem.perBankRdBursts::15 10553 # Per bank write bursts system.physmem.perBankWrBursts::0 7167 # Per bank write bursts -system.physmem.perBankWrBursts::1 7278 # Per bank write bursts +system.physmem.perBankWrBursts::1 7277 # Per bank write bursts system.physmem.perBankWrBursts::2 7300 # Per bank write bursts system.physmem.perBankWrBursts::3 7008 # Per bank write bursts -system.physmem.perBankWrBursts::4 7143 # Per bank write bursts -system.physmem.perBankWrBursts::5 7301 # Per bank write bursts +system.physmem.perBankWrBursts::4 7142 # Per bank write bursts +system.physmem.perBankWrBursts::5 7300 # Per bank write bursts system.physmem.perBankWrBursts::6 6892 # Per bank write bursts -system.physmem.perBankWrBursts::7 7161 # Per bank write bursts -system.physmem.perBankWrBursts::8 7241 # Per bank write bursts -system.physmem.perBankWrBursts::9 7068 # Per bank write bursts +system.physmem.perBankWrBursts::7 7158 # Per bank write bursts +system.physmem.perBankWrBursts::8 7240 # Per bank write bursts +system.physmem.perBankWrBursts::9 7069 # Per bank write bursts system.physmem.perBankWrBursts::10 7202 # Per bank write bursts -system.physmem.perBankWrBursts::11 7125 # Per bank write bursts +system.physmem.perBankWrBursts::11 7121 # Per bank write bursts system.physmem.perBankWrBursts::12 7069 # Per bank write bursts system.physmem.perBankWrBursts::13 7390 # Per bank write bursts system.physmem.perBankWrBursts::14 7350 # Per bank write bursts system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22293510500 # Total gap between requests +system.physmem.totGap 22819740500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165389 # Read request sizes (log2) +system.physmem.readPktSize::6 165390 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115200 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 42842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115197 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,125 +194,136 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 44806 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 400.727760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.628821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.162466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13215 29.49% 29.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8315 18.56% 48.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5340 11.92% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2750 6.14% 66.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2605 5.81% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1593 3.56% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1654 3.69% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1106 2.47% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8228 18.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 44806 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.298957 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.933264 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 317.077516 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7097 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 44648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 402.130084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 240.586732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 367.720381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13091 29.32% 29.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8315 18.62% 47.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5360 12.01% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2692 6.03% 65.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2549 5.71% 71.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1575 3.53% 75.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1705 3.82% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1125 2.52% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8236 18.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 44648 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.304961 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.955367 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 317.126574 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7095 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7098 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.226824 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.209944 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.780993 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6477 91.25% 91.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 22 0.31% 91.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 336 4.73% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 168 2.37% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 66 0.93% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 27 0.38% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7098 # Writes before turning the bus around for reads -system.physmem.totQLat 5599085250 # Total ticks spent queuing -system.physmem.totMemAccLat 8699960250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33855.88 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7096 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.229989 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.211978 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.816035 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6480 91.32% 91.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.25% 91.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 334 4.71% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 161 2.27% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 74 1.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 24 0.34% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7096 # Writes before turning the bus around for reads +system.physmem.totQLat 7131716500 # Total ticks spent queuing +system.physmem.totMemAccLat 10232647750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43122.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52605.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 474.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 330.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 474.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 330.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 61872.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 463.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 323.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 463.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 323.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.29 # Data bus utilization in percentage -system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.58 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.72 # Average write queue length when enqueuing -system.physmem.readRowHits 145830 # Number of row buffer hits during reads -system.physmem.writeRowHits 89913 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes -system.physmem.avgGap 79452.55 # Average gap between requests -system.physmem.pageHitRate 84.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 163424520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 89170125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636441000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 370882800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6110627715 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8015176500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16841729940 # Total energy per rank (pJ) -system.physmem_0.averagePower 755.495604 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 13256940500 # Time in different power states -system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8290987000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 175218120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 95605125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 653343600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 375366960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6480752940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7690505250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16926799275 # Total energy per rank (pJ) -system.physmem_1.averagePower 759.311692 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12714890500 # Time in different power states -system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8833037000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16464676 # Number of BP lookups -system.cpu.branchPred.condPredicted 10658312 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 322373 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8884191 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7232535 # Number of BTB hits +system.physmem.busUtil 6.15 # Data bus utilization in percentage +system.physmem.busUtilRead 3.62 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 145971 # Number of row buffer hits during reads +system.physmem.writeRowHits 89923 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes +system.physmem.avgGap 81328.57 # Average gap between requests +system.physmem.pageHitRate 84.07 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153103020 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 81361005 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 582666840 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 298813680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1398920640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1820142240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 87895200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 2523555300 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1884269760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 2191410645 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11023267740 # Total energy per rank (pJ) +system.physmem_0.averagePower 483.057740 # Core power per rank (mW) +system.physmem_0.totalIdleTime 18596850000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 135529000 # Time in different power states +system.physmem_0.memoryStateTime::REF 594334000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 8155766000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 4906976500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3493009750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 5534156250 # Time in different power states +system.physmem_1.actEnergy 165747960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 88078155 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 598167780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 302363280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1429652640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1911531480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 82258560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 2724848520 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1880202720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 2026371015 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11210189940 # Total energy per rank (pJ) +system.physmem_1.averagePower 491.248979 # Core power per rank (mW) +system.physmem_1.totalIdleTime 18411251500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 119903000 # Time in different power states +system.physmem_1.memoryStateTime::REF 607208000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 7539541250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 4896374750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3681289750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 5975454750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16458678 # Number of BP lookups +system.cpu.branchPred.condPredicted 10655092 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 320474 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8794743 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7227596 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.409044 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1975403 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3321 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39323 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31540 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7783 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2655 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 82.180866 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1974394 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3324 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39317 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31522 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7795 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2656 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22505585 # DTB read hits -system.cpu.dtb.read_misses 226699 # DTB read misses +system.cpu.dtb.read_hits 22495361 # DTB read hits +system.cpu.dtb.read_misses 227004 # DTB read misses system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22732284 # DTB read accesses -system.cpu.dtb.write_hits 15808846 # DTB write hits -system.cpu.dtb.write_misses 44546 # DTB write misses +system.cpu.dtb.read_accesses 22722365 # DTB read accesses +system.cpu.dtb.write_hits 15803250 # DTB write hits +system.cpu.dtb.write_misses 44602 # DTB write misses system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15853392 # DTB write accesses -system.cpu.dtb.data_hits 38314431 # DTB hits -system.cpu.dtb.data_misses 271245 # DTB misses +system.cpu.dtb.write_accesses 15847852 # DTB write accesses +system.cpu.dtb.data_hits 38298611 # DTB hits +system.cpu.dtb.data_misses 271606 # DTB misses system.cpu.dtb.data_acv 22 # DTB access violations -system.cpu.dtb.data_accesses 38585676 # DTB accesses -system.cpu.itb.fetch_hits 13724143 # ITB hits -system.cpu.itb.fetch_misses 29345 # ITB misses +system.cpu.dtb.data_accesses 38570217 # DTB accesses +system.cpu.itb.fetch_hits 13713928 # ITB hits +system.cpu.itb.fetch_misses 29641 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13753488 # ITB accesses +system.cpu.itb.fetch_accesses 13743569 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,101 +337,101 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44587088 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 45639548 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15537600 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105003279 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16464676 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9239478 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27573681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 883330 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 330450 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13724143 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187041 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15527632 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104958165 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16458678 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9233512 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 28526394 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 879432 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1335 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 342280 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 91 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13713928 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 186437 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43888428 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.392505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.127693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 44842161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.340613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.113400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24387762 55.57% 55.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1515251 3.45% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1377134 3.14% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1500310 3.42% 65.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4190997 9.55% 75.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1825571 4.16% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669926 1.53% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050385 2.39% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7371092 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25352844 56.54% 56.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1513864 3.38% 59.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1375551 3.07% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1499198 3.34% 66.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4186922 9.34% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1824752 4.07% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 669001 1.49% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050081 2.34% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7369948 16.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43888428 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369270 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.355015 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14897050 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9776190 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18280655 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 589828 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 344705 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3701787 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98635 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103032848 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312916 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 344705 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15240775 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4552016 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97125 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18511621 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5142186 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102032260 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5895 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 92509 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 354670 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4626637 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61342957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123044735 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122725402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319332 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44842161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.360623 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.299720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14899514 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10738608 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18272960 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 588305 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 342774 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3699945 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98528 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 102994976 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312859 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 342774 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15240271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5029380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97820 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18506228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5625688 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102003977 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6871 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 88609 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 422499 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5043111 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61324692 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123005722 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122686459 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319262 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8796076 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5684 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5736 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2358572 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23134576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16358313 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246652 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 504576 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90719727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88603709 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 68043 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11133526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4439018 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 973 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43888428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018840 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8777811 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5683 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5735 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2339310 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23131891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16353716 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1249387 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 502474 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90699211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88573949 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67838 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11113012 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4439512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 975 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44842161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.975238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.240795 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17434377 39.72% 39.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5720394 13.03% 52.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5103914 11.63% 64.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4383916 9.99% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4317842 9.84% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2637316 6.01% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1940633 4.42% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1378295 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 971741 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18402096 41.04% 41.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5711089 12.74% 53.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5105714 11.39% 65.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4382501 9.77% 74.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4313150 9.62% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2637224 5.88% 90.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1940283 4.33% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1377321 3.07% 97.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 972783 2.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43888428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44842161 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 241284 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 241463 9.57% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available @@ -449,19 +460,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1166228 46.24% 55.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1114848 44.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168337 46.29% 55.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1114013 44.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49379489 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44005 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49366935 55.74% 55.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43991 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121171 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120707 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39092 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -483,82 +494,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22899221 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15999870 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22887844 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15994084 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88603709 # Type of FU issued -system.cpu.iq.rate 1.987206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2522360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223074890 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101458980 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86835527 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611359 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420488 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299878 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90820238 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305831 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1672227 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued +system.cpu.iq.rate 1.940728 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2523813 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028494 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223970382 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611328 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90791946 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305816 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2857938 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5878 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20874 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1744936 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5856 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20836 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3021 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 200758 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3017 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 190756 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 344705 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1315985 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2729229 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100214269 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 118431 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23134576 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16358313 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5556 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3898 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2727794 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20874 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 113179 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 152389 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 265568 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87909421 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22732927 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 694288 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 342774 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1435868 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3107979 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100192818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 116708 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23131891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16353716 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5558 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3773 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3106841 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20836 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 111267 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 152585 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 263852 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87883972 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22722991 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 689977 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9488986 # number of nop insts executed -system.cpu.iew.exec_refs 38586655 # number of memory reference insts executed -system.cpu.iew.exec_branches 15119960 # Number of branches executed -system.cpu.iew.exec_stores 15853728 # Number of stores executed -system.cpu.iew.exec_rate 1.971634 # Inst execution rate -system.cpu.iew.wb_sent 87537444 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87135405 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33842966 # num instructions producing a value -system.cpu.iew.wb_consumers 44247648 # num instructions consuming a value -system.cpu.iew.wb_rate 1.954274 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764853 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8653815 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9488049 # number of nop insts executed +system.cpu.iew.exec_refs 38571182 # number of memory reference insts executed +system.cpu.iew.exec_branches 15118040 # Number of branches executed +system.cpu.iew.exec_stores 15848191 # Number of stores executed +system.cpu.iew.exec_rate 1.925610 # Inst execution rate +system.cpu.iew.wb_sent 87519959 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87118018 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33843453 # num instructions producing a value +system.cpu.iew.wb_consumers 44250497 # num instructions consuming a value +system.cpu.iew.wb_rate 1.908827 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764815 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8632074 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 225413 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42617548 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.072871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.885939 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 223532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43575084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.027321 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.870724 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21149374 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6281932 14.74% 64.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2908445 6.82% 71.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1738602 4.08% 75.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1681485 3.95% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1121192 2.63% 81.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1200701 2.82% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 796598 1.87% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5739219 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22117259 50.76% 50.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6277727 14.41% 65.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2900957 6.66% 71.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1737731 3.99% 75.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1677521 3.85% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1124025 2.58% 82.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1202727 2.76% 85.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 795829 1.83% 86.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5741308 13.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42617548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43575084 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,471 +615,471 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5739219 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132555474 # The number of ROB reads -system.cpu.rob.rob_writes 195263120 # The number of ROB writes -system.cpu.timesIdled 45271 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 698660 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5741308 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 133489180 # The number of ROB reads +system.cpu.rob.rob_writes 195215826 # The number of ROB writes +system.cpu.timesIdled 45373 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 797387 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.560197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.560197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.785085 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.785085 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116363135 # number of integer regfile reads -system.cpu.int_regfile_writes 57669565 # number of integer regfile writes -system.cpu.fp_regfile_reads 255561 # number of floating regfile reads -system.cpu.fp_regfile_writes 240404 # number of floating regfile writes -system.cpu.misc_regfile_reads 38263 # number of misc regfile reads +system.cpu.cpi 0.573421 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.573421 # CPI: Total CPI of All Threads +system.cpu.ipc 1.743921 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.743921 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116327818 # number of integer regfile reads +system.cpu.int_regfile_writes 57658172 # number of integer regfile writes +system.cpu.fp_regfile_reads 255578 # number of floating regfile reads +system.cpu.fp_regfile_writes 240399 # number of floating regfile writes +system.cpu.misc_regfile_reads 38260 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201400 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.443451 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33984025 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205496 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.375603 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 232048500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.443451 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993761 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993761 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 201413 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.948439 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33978122 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205509 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.336418 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244590500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.948439 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993640 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2488 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1533 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70817108 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70817108 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20422994 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20422994 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13560978 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13560978 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33983972 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33983972 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33983972 # number of overall hits -system.cpu.dcache.overall_hits::total 33983972 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269382 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269382 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052399 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052399 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321781 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321781 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321781 # number of overall misses -system.cpu.dcache.overall_misses::total 1321781 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18043068500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18043068500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88421559159 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88421559159 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106464627659 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106464627659 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106464627659 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106464627659 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20692376 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20692376 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70808789 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70808789 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20418812 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20418812 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13559258 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13559258 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33978070 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33978070 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33978070 # number of overall hits +system.cpu.dcache.overall_hits::total 33978070 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269399 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269399 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1054119 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1054119 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1323518 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1323518 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1323518 # number of overall misses +system.cpu.dcache.overall_misses::total 1323518 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19371317500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19371317500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 94432641988 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 94432641988 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113803959488 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113803959488 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113803959488 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113803959488 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20688211 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20688211 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35305753 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35305753 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35305753 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35305753 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072016 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072016 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037438 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037438 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037438 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037438 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80546.344409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80546.344409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6874865 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 86609 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35301588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35301588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35301588 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35301588 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072134 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072134 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037492 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037492 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037492 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037492 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71905.677081 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71905.677081 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89584.422620 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89584.422620 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85985.955225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85985.955225 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7415690 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 299 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 82797 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.378182 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 139.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168502 # number of writebacks -system.cpu.dcache.writebacks::total 168502 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207279 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207279 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 909006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 909006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1116285 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1116285 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1116285 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1116285 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205496 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205496 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205496 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205496 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3336459000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3336459000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14128429272 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14128429272 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17464888272 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17464888272 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17464888272 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17464888272 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005820 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005820 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90436 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.490065 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13619166 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92484 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.259699 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18779712500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1916.490065 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935786 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935786 # Average percentage of cache occupancy +system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.564719 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 149.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168510 # number of writebacks +system.cpu.dcache.writebacks::total 168510 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207284 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207284 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910725 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910725 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1118009 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1118009 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1118009 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1118009 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62115 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62115 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205509 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205509 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205509 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205509 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3617431500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3617431500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15283982713 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15283982713 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18901414213 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18901414213 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18901414213 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18901414213 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005822 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005822 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58237.647911 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58237.647911 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106587.323828 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106587.323828 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 90457 # number of replacements +system.cpu.icache.tags.tagsinuse 1914.919853 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13608920 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 92505 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.115507 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19216549500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1914.919853 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935019 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935019 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1460 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 389 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1462 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27540768 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27540768 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 13619166 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13619166 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13619166 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13619166 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13619166 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115201 # number of writebacks -system.cpu.l2cache.writebacks::total 115201 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 112 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 112 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130811 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130811 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2881682000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2881682000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 582406000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16506565000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17088971000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 582406000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16506565000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17088971000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452666 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452666 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589817 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291836 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912264 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912264 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452498 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452498 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.554975 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.554975 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 104153.827925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 104153.827925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90016.383308 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90016.383308 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102529.068526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102529.068526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 589885 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291870 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4239 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4237 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4237 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52571 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887797 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11706880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23935872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35642752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134874 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7372864 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 432855 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009793 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098475 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 154618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62113 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275468 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612431 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11709568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23937216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35646784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134872 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7372672 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 432887 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009788 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098448 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 428616 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4239 0.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428650 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4237 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432855 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553846500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138734483 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432887 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553909500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 138764985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308248491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308272981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130746 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_requests 130745 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34578 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115200 # Transaction distribution -system.membus.trans_dist::CleanEvict 15546 # Transaction distribution -system.membus.trans_dist::ReadExReq 130811 # Transaction distribution -system.membus.trans_dist::ReadExResp 130811 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34578 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 461524 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17957696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34575 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115197 # Transaction distribution +system.membus.trans_dist::CleanEvict 15548 # Transaction distribution +system.membus.trans_dist::ReadExReq 130815 # Transaction distribution +system.membus.trans_dist::ReadExResp 130815 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 461525 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17957568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165389 # Request fanout histogram +system.membus.snoop_fanout::samples 165390 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165390 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165389 # Request fanout histogram -system.membus.reqLayer0.occupancy 780841500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 854544750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.8 # Layer utilization (%) +system.membus.snoop_fanout::total 165390 # Request fanout histogram +system.membus.reqLayer0.occupancy 779827500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 851966000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini index 7debe9727..3119a9994 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout index 9e5ee29fe..9fd7ec0be 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:05:27 -gem5 executing on e108600-lin, pid 24209 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:42:59 +gem5 executing on e108600-lin, pid 17323 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 58768125500 because target called exit() +Exiting @ tick 60130734500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 7abf225fd..feef465f0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058750 # Number of seconds simulated -sim_ticks 58750410500 # Number of ticks simulated -final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060131 # Number of seconds simulated +sim_ticks 60130734500 # Number of ticks simulated +final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179920 # Simulator instruction rate (inst/s) -host_op_rate 230092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 149057017 # Simulator tick rate (ticks/s) -host_mem_usage 281832 # Number of bytes of host memory used -host_seconds 394.15 # Real time elapsed on the host +host_inst_rate 142105 # Simulator instruction rate (inst/s) +host_op_rate 181732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120494644 # Simulator tick rate (ticks/s) +host_mem_usage 279144 # Number of bytes of host memory used +host_seconds 499.03 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.physmem.num_reads::cpu.data 124041 # Nu system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128515 # Number of read requests accepted system.physmem.writeReqs 86552 # Number of write requests accepted system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8086 # Per bank write bursts @@ -57,24 +57,24 @@ system.physmem.perBankRdBursts::4 8301 # Pe system.physmem.perBankRdBursts::5 8413 # Per bank write bursts system.physmem.perBankRdBursts::6 8070 # Per bank write bursts system.physmem.perBankRdBursts::7 7917 # Per bank write bursts -system.physmem.perBankRdBursts::8 8053 # Per bank write bursts -system.physmem.perBankRdBursts::9 7612 # Per bank write bursts +system.physmem.perBankRdBursts::8 8054 # Per bank write bursts +system.physmem.perBankRdBursts::9 7613 # Per bank write bursts system.physmem.perBankRdBursts::10 7771 # Per bank write bursts system.physmem.perBankRdBursts::11 7825 # Per bank write bursts system.physmem.perBankRdBursts::12 7888 # Per bank write bursts system.physmem.perBankRdBursts::13 7870 # Per bank write bursts system.physmem.perBankRdBursts::14 7981 # Per bank write bursts system.physmem.perBankRdBursts::15 7974 # Per bank write bursts -system.physmem.perBankWrBursts::0 5399 # Per bank write bursts +system.physmem.perBankWrBursts::0 5400 # Per bank write bursts system.physmem.perBankWrBursts::1 5549 # Per bank write bursts -system.physmem.perBankWrBursts::2 5476 # Per bank write bursts -system.physmem.perBankWrBursts::3 5348 # Per bank write bursts +system.physmem.perBankWrBursts::2 5475 # Per bank write bursts +system.physmem.perBankWrBursts::3 5349 # Per bank write bursts system.physmem.perBankWrBursts::4 5387 # Per bank write bursts -system.physmem.perBankWrBursts::5 5588 # Per bank write bursts +system.physmem.perBankWrBursts::5 5586 # Per bank write bursts system.physmem.perBankWrBursts::6 5325 # Per bank write bursts system.physmem.perBankWrBursts::7 5260 # Per bank write bursts system.physmem.perBankWrBursts::8 5187 # Per bank write bursts -system.physmem.perBankWrBursts::9 5136 # Per bank write bursts +system.physmem.perBankWrBursts::9 5135 # Per bank write bursts system.physmem.perBankWrBursts::10 5306 # Per bank write bursts system.physmem.perBankWrBursts::11 5279 # Per bank write bursts system.physmem.perBankWrBursts::12 5541 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 5706 # Pe system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58750379000 # Total gap between requests +system.physmem.totGap 60130703000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -98,11 +98,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86552 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,104 +194,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads -system.physmem.totQLat 1552277750 # Total ticks spent queuing -system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads +system.physmem.totQLat 3048956750 # Total ticks spent queuing +system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.83 # Data bus utilization in percentage -system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.79 # Data bus utilization in percentage +system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing -system.physmem.readRowHits 112029 # Number of row buffer hits during reads -system.physmem.writeRowHits 70027 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes -system.physmem.avgGap 273172.45 # Average gap between requests -system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ) -system.physmem_0.averagePower 705.717335 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ) -system.physmem_1.averagePower 704.382975 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827613 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits +system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing +system.physmem.readRowHits 112228 # Number of row buffer hits during reads +system.physmem.writeRowHits 69923 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes +system.physmem.avgGap 279590.56 # Average gap between requests +system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ) +system.physmem_0.averagePower 386.883743 # Core power per rank (mW) +system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states +system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ) +system.physmem_1.averagePower 383.200220 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14827796 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -321,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -412,16 +423,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117500821 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120261469 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.656921 # CPI: cycles per instruction -system.cpu.ipc 0.603529 # IPC: instructions per cycle +system.cpu.cpi 1.695850 # CPI: cycles per instruction +system.cpu.ipc 0.589675 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -457,106 +468,106 @@ system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked +system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 156451 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits -system.cpu.dcache.overall_hits::total 42605646 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses -system.cpu.dcache.overall_misses::total 299891 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits +system.cpu.dcache.overall_hits::total 42605457 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses +system.cpu.dcache.overall_misses::total 299788 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks system.cpu.dcache.writebacks::total 128145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses @@ -567,92 +578,92 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136566 system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 43545 # number of replacements -system.cpu.icache.tags.tagsinuse 1854.190293 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25047618 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 549.446509 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1854.190293 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.905366 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.905366 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits -system.cpu.icache.overall_hits::total 25047618 # number of overall hits +system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits +system.cpu.icache.overall_hits::total 25048343 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses system.cpu.icache.overall_misses::total 45588 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 918433000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 918433000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 918433000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 918433000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 918433000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 918433000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20146.376239 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20146.376239 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20146.376239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20146.376239 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -667,88 +678,88 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 45588 system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 872846000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 872846000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 872846000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 872846000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 872846000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 872846000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 97176 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31328.460689 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 268173 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.063758 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10596662000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 480.299456 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1381.968758 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29466.192474 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.014658 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042174 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.899237 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.956069 # Average percentage of cache occupancy +system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.954966 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13615 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17003 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12834 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17840 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41100 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 41100 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41101 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 41101 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 41100 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 41101 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77546 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 41100 # number of overall hits +system.cpu.l2cache.demand_hits::total 77547 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 41101 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits -system.cpu.l2cache.overall_hits::total 77546 # number of overall hits +system.cpu.l2cache.overall_hits::total 77547 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4488 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 4488 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4487 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4487 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4488 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 4487 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128589 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4488 # number of overall misses +system.cpu.l2cache.demand_misses::total 128588 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses -system.cpu.l2cache.overall_misses::total 128589 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8191072500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8191072500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 369038000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 369038000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1957896000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1957896000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 369038000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10148968500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10518006500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 369038000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10148968500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10518006500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 128588 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) @@ -767,28 +778,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 160547 system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098447 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098447 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098425 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098425 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098447 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098425 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.623810 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098447 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.623805 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.623810 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80055.831387 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80055.831387 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82227.718360 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82227.718360 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89877.708410 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89877.708410 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -797,16 +808,16 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks system.cpu.l2cache.writebacks::total 86552 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses @@ -821,18 +832,18 @@ system.cpu.l2cache.demand_mshr_misses::total 128516 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7167902500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7167902500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 323146000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 323146000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1736095500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1736095500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 323146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8903998000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9227144000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 323146000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8903998000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9227144000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses @@ -847,25 +858,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution @@ -895,7 +906,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 2 # system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) @@ -905,7 +916,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 26198 # Transaction distribution system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution system.membus.trans_dist::CleanEvict 7237 # Transaction distribution @@ -928,9 +939,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 128515 # Request fanout histogram -system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 8b084cbe5..e2ac8f237 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 1832c357f..77b319c20 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12236 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:59:48 +gem5 executing on e108600-lin, pid 17544 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 33524756000 because target called exit() +Exiting @ tick 37982056000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 7d5e42cd5..6270a4a24 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.037283 # Number of seconds simulated -sim_ticks 37283333000 # Number of ticks simulated -final_tick 37283333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037982 # Number of seconds simulated +sim_ticks 37982056000 # Number of ticks simulated +final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125888 # Simulator instruction rate (inst/s) -host_op_rate 160996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66191855 # Simulator tick rate (ticks/s) -host_mem_usage 284264 # Number of bytes of host memory used -host_seconds 563.26 # Real time elapsed on the host +host_inst_rate 105525 # Simulator instruction rate (inst/s) +host_op_rate 134954 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56525025 # Simulator tick rate (ticks/s) +host_mem_usage 282344 # Number of bytes of host memory used +host_seconds 671.95 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2379328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5690752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6174592 # Number of bytes read from this memory -system.physmem.bytes_read::total 14244672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2379328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2379328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6224768 # Number of bytes written to this memory -system.physmem.bytes_written::total 6224768 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 37177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 88918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96478 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222573 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97262 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97262 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 63817470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 152635281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 165612661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 382065412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 63817470 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 63817470 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166958464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166958464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166958464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 63817470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 152635281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 165612661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 549023876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222574 # Number of read requests accepted -system.physmem.writeReqs 97262 # Number of write requests accepted -system.physmem.readBursts 222574 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97262 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14235136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 6223360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14244736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6224768 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2372544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5696640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6178368 # Number of bytes read from this memory +system.physmem.bytes_read::total 14247552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2372544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2372544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6227072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6227072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37071 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 89010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222618 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97298 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 62464865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 149982402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 162665444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 375112711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 62464865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 62464865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163947734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163947734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163947734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 62464865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 149982402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 162665444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 539060445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222619 # Number of read requests accepted +system.physmem.writeReqs 97298 # Number of write requests accepted +system.physmem.readBursts 222619 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97298 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14237568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue +system.physmem.bytesWritten 6225984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14247616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6227072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9684 # Per bank write bursts -system.physmem.perBankRdBursts::1 9951 # Per bank write bursts -system.physmem.perBankRdBursts::2 12571 # Per bank write bursts -system.physmem.perBankRdBursts::3 25345 # Per bank write bursts -system.physmem.perBankRdBursts::4 17391 # Per bank write bursts -system.physmem.perBankRdBursts::5 22070 # Per bank write bursts -system.physmem.perBankRdBursts::6 11722 # Per bank write bursts -system.physmem.perBankRdBursts::7 14054 # Per bank write bursts -system.physmem.perBankRdBursts::8 11726 # Per bank write bursts -system.physmem.perBankRdBursts::9 15447 # Per bank write bursts -system.physmem.perBankRdBursts::10 11755 # Per bank write bursts -system.physmem.perBankRdBursts::11 11322 # Per bank write bursts -system.physmem.perBankRdBursts::12 9441 # Per bank write bursts -system.physmem.perBankRdBursts::13 9563 # Per bank write bursts -system.physmem.perBankRdBursts::14 9879 # Per bank write bursts -system.physmem.perBankRdBursts::15 20503 # Per bank write bursts -system.physmem.perBankWrBursts::0 5981 # Per bank write bursts -system.physmem.perBankWrBursts::1 6205 # Per bank write bursts -system.physmem.perBankWrBursts::2 6090 # Per bank write bursts -system.physmem.perBankWrBursts::3 6159 # Per bank write bursts -system.physmem.perBankWrBursts::4 6110 # Per bank write bursts -system.physmem.perBankWrBursts::5 6252 # Per bank write bursts -system.physmem.perBankWrBursts::6 5998 # Per bank write bursts -system.physmem.perBankWrBursts::7 5984 # Per bank write bursts -system.physmem.perBankWrBursts::8 5961 # Per bank write bursts -system.physmem.perBankWrBursts::9 6093 # Per bank write bursts -system.physmem.perBankWrBursts::10 6222 # Per bank write bursts -system.physmem.perBankWrBursts::11 5895 # Per bank write bursts -system.physmem.perBankWrBursts::12 6037 # Per bank write bursts -system.physmem.perBankWrBursts::13 6052 # Per bank write bursts -system.physmem.perBankWrBursts::14 6175 # Per bank write bursts -system.physmem.perBankWrBursts::15 6026 # Per bank write bursts +system.physmem.perBankRdBursts::0 9655 # Per bank write bursts +system.physmem.perBankRdBursts::1 9974 # Per bank write bursts +system.physmem.perBankRdBursts::2 12579 # Per bank write bursts +system.physmem.perBankRdBursts::3 25363 # Per bank write bursts +system.physmem.perBankRdBursts::4 17343 # Per bank write bursts +system.physmem.perBankRdBursts::5 22132 # Per bank write bursts +system.physmem.perBankRdBursts::6 11760 # Per bank write bursts +system.physmem.perBankRdBursts::7 14137 # Per bank write bursts +system.physmem.perBankRdBursts::8 11660 # Per bank write bursts +system.physmem.perBankRdBursts::9 15453 # Per bank write bursts +system.physmem.perBankRdBursts::10 11698 # Per bank write bursts +system.physmem.perBankRdBursts::11 11338 # Per bank write bursts +system.physmem.perBankRdBursts::12 9437 # Per bank write bursts +system.physmem.perBankRdBursts::13 9564 # Per bank write bursts +system.physmem.perBankRdBursts::14 9858 # Per bank write bursts +system.physmem.perBankRdBursts::15 20511 # Per bank write bursts +system.physmem.perBankWrBursts::0 5992 # Per bank write bursts +system.physmem.perBankWrBursts::1 6239 # Per bank write bursts +system.physmem.perBankWrBursts::2 6121 # Per bank write bursts +system.physmem.perBankWrBursts::3 6129 # Per bank write bursts +system.physmem.perBankWrBursts::4 6098 # Per bank write bursts +system.physmem.perBankWrBursts::5 6229 # Per bank write bursts +system.physmem.perBankWrBursts::6 6018 # Per bank write bursts +system.physmem.perBankWrBursts::7 5980 # Per bank write bursts +system.physmem.perBankWrBursts::8 5938 # Per bank write bursts +system.physmem.perBankWrBursts::9 6095 # Per bank write bursts +system.physmem.perBankWrBursts::10 6202 # Per bank write bursts +system.physmem.perBankWrBursts::11 5916 # Per bank write bursts +system.physmem.perBankWrBursts::12 6046 # Per bank write bursts +system.physmem.perBankWrBursts::13 6090 # Per bank write bursts +system.physmem.perBankWrBursts::14 6173 # Per bank write bursts +system.physmem.perBankWrBursts::15 6015 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37283321500 # Total gap between requests +system.physmem.totGap 37982044500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222574 # Read request sizes (log2) +system.physmem.readPktSize::6 222619 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97262 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 113358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5097 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97298 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 111989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,34 +149,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req 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queue length does an incoming req see -system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -198,109 +198,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132565 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 154.319345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.621145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 210.186270 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82651 62.35% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32256 24.33% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6354 4.79% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2721 2.05% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1163 0.88% 94.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1002 0.76% 95.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 846 0.64% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 812 0.61% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4760 3.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132565 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.864488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 211.288279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5866 99.86% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 7 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 132891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 153.980270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.520664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 209.589027 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82855 62.35% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32511 24.46% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6209 4.67% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2728 2.05% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1195 0.90% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 994 0.75% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 885 0.67% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 776 0.58% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4738 3.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132891 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.813870 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.295819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5876 99.88% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5874 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.554307 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512747 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.243213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4672 79.54% 79.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 38 0.65% 80.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 729 12.41% 92.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 209 3.56% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 107 1.82% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 58 0.99% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 31 0.53% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 16 0.27% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 11 0.19% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5874 # Writes before turning the bus around for reads -system.physmem.totQLat 7261518854 # Total ticks spent queuing -system.physmem.totMemAccLat 11431968854 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1112120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32647.19 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.535951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.496117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.216118 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4707 80.01% 80.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 47 0.80% 80.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 703 11.95% 92.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 205 3.48% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 109 1.85% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 61 1.04% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 33 0.56% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.19% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads +system.physmem.totQLat 8417974819 # Total ticks spent queuing +system.physmem.totMemAccLat 12589137319 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112310000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37840.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51397.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 166.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 382.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 166.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56590.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 163.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 375.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 163.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.29 # Data bus utilization in percentage -system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing -system.physmem.readRowHits 157163 # Number of row buffer hits during reads -system.physmem.writeRowHits 29925 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.77 # Row buffer hit rate for writes -system.physmem.avgGap 116570.12 # Average gap between requests -system.physmem.pageHitRate 58.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 537077520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 293048250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 957496800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 315958320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 23206024395 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2012333250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 29756923815 # Total energy per rank (pJ) -system.physmem_0.averagePower 798.183082 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3201879547 # Time in different power states -system.physmem_0.memoryStateTime::REF 1244880000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32834079203 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 464871960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 253650375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 777051600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313949520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 21592790730 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3427453500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 29264752965 # Total energy per rank (pJ) -system.physmem_1.averagePower 784.981262 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 5568954615 # Time in different power states -system.physmem_1.memoryStateTime::REF 1244880000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30467009135 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17068882 # Number of BP lookups -system.cpu.branchPred.condPredicted 11456187 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 597693 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9279962 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7373647 # Number of BTB hits +system.physmem.busUtil 4.21 # Data bus utilization in percentage +system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing +system.physmem.readRowHits 157076 # Number of row buffer hits during reads +system.physmem.writeRowHits 29766 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes +system.physmem.avgGap 118724.68 # Average gap between requests +system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 508332300 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 270162255 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 877813020 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254767320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3007433520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2937544590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74566560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13007568150 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1007588640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 71626485 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 22017862440 # Total energy per rank (pJ) +system.physmem_0.averagePower 579.691165 # Core power per rank (mW) +system.physmem_0.totalIdleTime 31344656336 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 41004063 # Time in different power states +system.physmem_0.memoryStateTime::REF 1272480000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 195565250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2624595348 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5323818601 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28524592738 # Time in different power states +system.physmem_1.actEnergy 440580840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 234159090 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 710558520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 253039500 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2889422640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2771748120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 73304160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11932439280 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1384694400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 508589940 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 21198847170 # Total energy per rank (pJ) +system.physmem_1.averagePower 558.127949 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31712588164 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 50452548 # Time in different power states +system.physmem_1.memoryStateTime::REF 1222746000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1938473750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3605935527 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4996269288 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26168178887 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17071043 # Number of BP lookups +system.cpu.branchPred.condPredicted 11458506 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 598065 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9277652 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7374059 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.457728 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1854916 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101589 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 233217 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195584 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37633 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22185 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.481953 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1854771 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101571 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233347 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 194967 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 38380 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22266 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +341,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +371,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +401,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,96 +432,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 74566667 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 75964113 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5541341 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87099155 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17068882 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9424147 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 65038748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1222021 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 11659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30739 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22432357 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69340 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 71233545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.545306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.327706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5537723 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87105546 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17071043 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9423797 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 66074321 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1222765 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 12043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 60 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 33616 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22433583 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69302 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 72269145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.523281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.330897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 26059108 36.58% 36.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8166381 11.46% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9112889 12.79% 60.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27895167 39.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27092588 37.49% 37.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8164913 11.30% 48.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9113637 12.61% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27898007 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 71233545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.228908 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.168071 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8928507 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 25221623 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30949867 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5689167 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 444381 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3134053 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168503 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100299686 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2798262 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 444381 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13572247 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10675080 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 842433 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31772787 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13926617 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98328841 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 859440 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4124148 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69439 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4596367 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5265270 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103255092 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453545884 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114277398 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 716 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 72269145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224725 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.146667 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8914938 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26268747 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30971085 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5669704 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 444671 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3134143 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168562 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100303161 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2799230 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 444671 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13550474 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11467047 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 876029 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31784130 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14146794 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98330583 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 860090 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4210253 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 70388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4670257 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5435231 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103259286 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453553071 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114279094 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9625723 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18974 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19002 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12839389 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24155878 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21759886 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1433320 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2321800 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97398916 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34841 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94478155 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 593843 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6751150 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17960313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1055 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 71233545 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.326316 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.168839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9629917 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18998 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19022 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12803731 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24155645 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21760500 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1435489 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2293932 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97400499 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34856 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94484787 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 595355 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6752748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17957034 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1070 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 72269145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.307401 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.171287 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23112455 32.45% 32.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17441476 24.48% 56.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17040128 23.92% 80.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11602976 16.29% 97.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2035055 2.86% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1455 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24146655 33.41% 33.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17449315 24.14% 57.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17027031 23.56% 81.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11604628 16.06% 97.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2040054 2.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1462 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 71233545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72269145 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6731709 22.63% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 38 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6736684 22.63% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 37 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available @@ -538,13 +549,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11081856 37.26% 59.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11930481 40.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11088474 37.25% 59.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11940322 40.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49303920 52.19% 52.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86563 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49305598 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86530 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -565,89 +576,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 11 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23954982 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21132627 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23958877 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21133721 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94478155 # Type of FU issued -system.cpu.iq.rate 1.267029 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29744084 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314825 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 290527434 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104196109 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93201296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 348 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 616 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124222040 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1368179 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued +system.cpu.iq.rate 1.243808 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29765517 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 183 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1289616 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2048 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1204148 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1204762 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 144864 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185613 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 147075 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 188044 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 444381 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 624509 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1115710 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97447803 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 444671 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 622988 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1195662 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97449431 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24155878 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21759886 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18921 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1617 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1111435 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 24155645 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21760500 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18936 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1589 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1191442 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 249911 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221890 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 471801 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93685311 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23691817 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 792844 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 249986 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 222081 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 472067 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93691189 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23695668 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 793598 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14046 # number of nop insts executed -system.cpu.iew.exec_refs 44616394 # number of memory reference insts executed -system.cpu.iew.exec_branches 14207133 # Number of branches executed -system.cpu.iew.exec_stores 20924577 # Number of stores executed -system.cpu.iew.exec_rate 1.256397 # Inst execution rate -system.cpu.iew.wb_sent 93308677 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93201392 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44951021 # num instructions producing a value -system.cpu.iew.wb_consumers 76633881 # num instructions consuming a value -system.cpu.iew.wb_rate 1.249907 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586569 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5894305 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 14076 # number of nop insts executed +system.cpu.iew.exec_refs 44621004 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207535 # Number of branches executed +system.cpu.iew.exec_stores 20925336 # Number of stores executed +system.cpu.iew.exec_rate 1.233361 # Inst execution rate +system.cpu.iew.wb_sent 93310594 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93203542 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44951761 # num instructions producing a value +system.cpu.iew.wb_consumers 76639550 # num instructions consuming a value +system.cpu.iew.wb_rate 1.226942 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586535 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5895620 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 431064 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 70277782 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.290424 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.118209 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431354 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 71312758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.271696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.107515 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 36842990 52.42% 52.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16674938 23.73% 76.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4291723 6.11% 82.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4149088 5.90% 88.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947878 2.77% 90.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1240751 1.77% 92.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 737656 1.05% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580756 0.83% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3812002 5.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 37859507 53.09% 53.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16683603 23.39% 76.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4297164 6.03% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4156384 5.83% 88.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1956005 2.74% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1240140 1.74% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 732437 1.03% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 578410 0.81% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3809108 5.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 70277782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71312758 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -693,552 +704,552 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3812002 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 163022945 # The number of ROB reads -system.cpu.rob.rob_writes 194122181 # The number of ROB writes -system.cpu.timesIdled 54257 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3333122 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3809108 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 164062130 # The number of ROB reads +system.cpu.rob.rob_writes 194125448 # The number of ROB writes +system.cpu.timesIdled 54252 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3694968 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.051603 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.051603 # CPI: Total CPI of All Threads -system.cpu.ipc 0.950930 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.950930 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101976703 # number of integer regfile reads -system.cpu.int_regfile_writes 56611271 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.fp_regfile_writes 48 # number of floating regfile writes -system.cpu.cc_regfile_reads 345090037 # number of cc regfile reads -system.cpu.cc_regfile_writes 38758670 # number of cc regfile writes -system.cpu.misc_regfile_reads 44101489 # number of misc regfile reads +system.cpu.cpi 1.071311 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.071311 # CPI: Total CPI of All Threads +system.cpu.ipc 0.933436 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.933436 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101982930 # number of integer regfile reads +system.cpu.int_regfile_writes 56612163 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 45 # number of floating regfile writes +system.cpu.cc_regfile_reads 345107562 # number of cc regfile reads +system.cpu.cc_regfile_writes 38759661 # number of cc regfile writes +system.cpu.misc_regfile_reads 44102170 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484862 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.874566 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40338135 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485374 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.107325 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 151605500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.874566 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997802 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484814 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.868965 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40339815 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485326 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.119007 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 154595500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.868965 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84467396 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84467396 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21414103 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21414103 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18832546 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18832546 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60212 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60212 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15310 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15310 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84466838 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84466838 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21417711 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21417711 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18830642 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18830642 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15309 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15309 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40246649 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40246649 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40306861 # number of overall hits -system.cpu.dcache.overall_hits::total 40306861 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 566310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 566310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1017355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1017355 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68643 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68643 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 613 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 613 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1583665 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1583665 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1652308 # number of overall misses -system.cpu.dcache.overall_misses::total 1652308 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13581553500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13581553500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13903205430 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13903205430 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5738500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5738500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27484758930 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27484758930 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27484758930 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27484758930 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21980413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21980413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40248353 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40248353 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40308541 # number of overall hits +system.cpu.dcache.overall_hits::total 40308541 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 562442 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 562442 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1019259 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1019259 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68672 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68672 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 614 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 614 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1581701 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1581701 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1650373 # number of overall misses +system.cpu.dcache.overall_misses::total 1650373 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14412910000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14412910000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14258561428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14258561428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5705500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5705500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28671471428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28671471428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28671471428 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28671471428 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980153 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128860 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128860 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41830314 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41830314 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41959169 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41959169 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051252 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051252 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532715 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532715 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038498 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038498 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037859 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037859 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039379 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039379 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9361.337684 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9361.337684 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17355.159664 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16634.161990 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2820837 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 130956 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21.540342 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484862 # number of writebacks -system.cpu.dcache.writebacks::total 484862 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 267183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868792 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 868792 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 613 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 613 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135975 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135975 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135975 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135975 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299127 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299127 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148563 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148563 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37696 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37696 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447690 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447690 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485386 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485386 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6671017500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6671017500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2276896471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2276896471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1910092000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1910092000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947913971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8947913971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10858005971 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10858005971 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013609 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41830054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41958914 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41958914 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025589 # miss rate for ReadReq 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# number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 614 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1134066 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1134066 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1134066 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1134066 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299074 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299074 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148561 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148561 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37704 # number of SoftPFReq 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rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292546 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010703 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010703 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011568 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011568 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22301.622722 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22301.622722 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15326.134172 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15326.134172 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50670.946520 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50670.946520 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19986.852445 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19986.852445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22369.837554 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22369.837554 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325915 # number of replacements -system.cpu.icache.tags.tagsinuse 510.404253 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22094458 # Total number of references to valid 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86371.461875 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592 # average ReadSharedReq mshr miss latency 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-system.cpu.toL2Bus.snoop_filter.hit_single_requests 810817 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79904 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18775 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297472 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1621957 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810494 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18773 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18772 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 663212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 351973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 556066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 144126 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148601 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148601 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 326440 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336773 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 978779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2434413 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41749696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62095104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103844800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 269627 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6225728 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1081438 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.288019 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 662893 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 354931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 552820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28222 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 146565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 326165 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336729 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455492 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2433446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41714496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62088960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103803456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 272099 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6227968 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1083589 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091107 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.287765 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 982719 90.87% 90.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98718 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 984867 90.89% 90.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98721 9.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1081438 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1622078500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489794228 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1083589 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1621431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 489373744 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728148836 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 348072 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 728066857 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 348152 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205320 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214175 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97262 # Transaction distribution -system.membus.trans_dist::CleanEvict 28224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 12 # Transaction distribution -system.membus.trans_dist::ReadExReq 8398 # Transaction distribution -system.membus.trans_dist::ReadExResp 8398 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570645 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20469440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20469440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214278 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97298 # Transaction distribution +system.membus.trans_dist::CleanEvict 28222 # Transaction distribution +system.membus.trans_dist::UpgradeReq 13 # Transaction distribution +system.membus.trans_dist::ReadExReq 8340 # Transaction distribution +system.membus.trans_dist::ReadExResp 8340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214279 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570770 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20474624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20474624 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222586 # Request fanout histogram +system.membus.snoop_fanout::samples 222632 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222586 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222632 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222586 # Request fanout histogram -system.membus.reqLayer0.occupancy 837454269 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222632 # Request fanout histogram +system.membus.reqLayer0.occupancy 835899979 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1175863136 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1175524166 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini index 10131fd38..0a31f5d4d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout index cd35cd53a..871055fe1 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4307 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28067 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1219570622500 because target called exit() +Exiting @ tick 1241902335500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index d8a41d287..5d202194f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.222275 # Number of seconds simulated -sim_ticks 1222274983500 # Number of ticks simulated -final_tick 1222274983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.241902 # Number of seconds simulated +sim_ticks 1241902335500 # Number of ticks simulated +final_tick 1241902335500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 407632 # Simulator instruction rate (inst/s) -host_op_rate 407632 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272801132 # Simulator tick rate (ticks/s) -host_mem_usage 256700 # Number of bytes of host memory used -host_seconds 4480.46 # Real time elapsed on the host +host_inst_rate 311711 # Simulator instruction rate (inst/s) +host_op_rate 311711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 211957790 # Simulator tick rate (ticks/s) +host_mem_usage 254092 # Number of bytes of host memory used +host_seconds 5859.20 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 61440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126177664 # Number of bytes read from this memory -system.physmem.bytes_read::total 126239104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66092544 # Number of bytes written to this memory -system.physmem.bytes_written::total 66092544 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 960 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1971526 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1972486 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032696 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032696 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103231814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103282081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54073384 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54073384 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54073384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103231814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157355465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1972486 # Number of read requests accepted -system.physmem.writeReqs 1032696 # Number of write requests accepted -system.physmem.readBursts 1972486 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1032696 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 126156992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue -system.physmem.bytesWritten 66090816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126239104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66092544 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126178240 # Number of bytes read from this memory +system.physmem.bytes_read::total 126239872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66092288 # Number of bytes written to this memory +system.physmem.bytes_written::total 66092288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1971535 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1972498 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032692 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032692 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 49627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 101600775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 101650402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 53218587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 53218587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 53218587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 101600775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 154868990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1972498 # Number of read requests accepted +system.physmem.writeReqs 1032692 # Number of write requests accepted +system.physmem.readBursts 1972498 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1032692 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 126161536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 78336 # Total number of bytes read from write queue +system.physmem.bytesWritten 66090880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126239872 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66092288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1224 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119355 # Per bank write bursts -system.physmem.perBankRdBursts::1 114736 # Per bank write bursts -system.physmem.perBankRdBursts::2 116711 # Per bank write bursts -system.physmem.perBankRdBursts::3 118315 # Per bank write bursts -system.physmem.perBankRdBursts::4 118360 # Per bank write bursts -system.physmem.perBankRdBursts::5 118227 # Per bank write bursts -system.physmem.perBankRdBursts::6 120694 # Per bank write bursts -system.physmem.perBankRdBursts::7 125539 # Per bank write bursts -system.physmem.perBankRdBursts::8 127875 # Per bank write bursts -system.physmem.perBankRdBursts::9 130856 # Per bank write bursts -system.physmem.perBankRdBursts::10 129453 # Per bank write bursts -system.physmem.perBankRdBursts::11 131175 # Per bank write bursts -system.physmem.perBankRdBursts::12 126741 # Per bank write bursts -system.physmem.perBankRdBursts::13 125953 # Per bank write bursts -system.physmem.perBankRdBursts::14 123325 # Per bank write bursts -system.physmem.perBankRdBursts::15 123888 # Per bank write bursts +system.physmem.perBankRdBursts::0 119357 # Per bank write bursts +system.physmem.perBankRdBursts::1 114729 # Per bank write bursts +system.physmem.perBankRdBursts::2 116715 # Per bank write bursts +system.physmem.perBankRdBursts::3 118322 # Per bank write bursts +system.physmem.perBankRdBursts::4 118352 # Per bank write bursts +system.physmem.perBankRdBursts::5 118237 # Per bank write bursts +system.physmem.perBankRdBursts::6 120696 # Per bank write bursts +system.physmem.perBankRdBursts::7 125562 # Per bank write bursts +system.physmem.perBankRdBursts::8 127868 # Per bank write bursts +system.physmem.perBankRdBursts::9 130858 # Per bank write bursts +system.physmem.perBankRdBursts::10 129451 # Per bank write bursts +system.physmem.perBankRdBursts::11 131187 # Per bank write bursts +system.physmem.perBankRdBursts::12 126743 # Per bank write bursts +system.physmem.perBankRdBursts::13 125956 # Per bank write bursts +system.physmem.perBankRdBursts::14 123338 # Per bank write bursts +system.physmem.perBankRdBursts::15 123903 # Per bank write bursts system.physmem.perBankWrBursts::0 62004 # Per bank write bursts -system.physmem.perBankWrBursts::1 62322 # Per bank write bursts -system.physmem.perBankWrBursts::2 61319 # Per bank write bursts -system.physmem.perBankWrBursts::3 62011 # Per bank write bursts -system.physmem.perBankWrBursts::4 62436 # Per bank write bursts -system.physmem.perBankWrBursts::5 63988 # Per bank write bursts -system.physmem.perBankWrBursts::6 65064 # Per bank write bursts -system.physmem.perBankWrBursts::7 66489 # Per bank write bursts -system.physmem.perBankWrBursts::8 66234 # Per bank write bursts -system.physmem.perBankWrBursts::9 66705 # Per bank write bursts -system.physmem.perBankWrBursts::10 66339 # Per bank write bursts -system.physmem.perBankWrBursts::11 66709 # Per bank write bursts -system.physmem.perBankWrBursts::12 65174 # Per bank write bursts -system.physmem.perBankWrBursts::13 65212 # Per bank write bursts -system.physmem.perBankWrBursts::14 65629 # Per bank write bursts -system.physmem.perBankWrBursts::15 65034 # Per bank write bursts +system.physmem.perBankWrBursts::1 62324 # Per bank write bursts +system.physmem.perBankWrBursts::2 61320 # Per bank write bursts +system.physmem.perBankWrBursts::3 62012 # Per bank write bursts +system.physmem.perBankWrBursts::4 62437 # Per bank write bursts +system.physmem.perBankWrBursts::5 63989 # Per bank write bursts +system.physmem.perBankWrBursts::6 65066 # Per bank write bursts +system.physmem.perBankWrBursts::7 66492 # Per bank write bursts +system.physmem.perBankWrBursts::8 66230 # Per bank write bursts +system.physmem.perBankWrBursts::9 66701 # Per bank write bursts +system.physmem.perBankWrBursts::10 66337 # Per bank write bursts +system.physmem.perBankWrBursts::11 66707 # Per bank write bursts +system.physmem.perBankWrBursts::12 65162 # Per bank write bursts +system.physmem.perBankWrBursts::13 65226 # Per bank write bursts +system.physmem.perBankWrBursts::14 65630 # Per bank write bursts +system.physmem.perBankWrBursts::15 65033 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1222274866500 # Total gap between requests +system.physmem.totGap 1241902212500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1972486 # Read request sizes (log2) +system.physmem.readPktSize::6 1972498 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1032696 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1847755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123438 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1032692 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1834002 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 137262 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,137 +194,147 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1846311 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.123632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.172382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 131.523418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1463397 79.26% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 266113 14.41% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48771 2.64% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20101 1.09% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12770 0.69% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7489 0.41% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5280 0.29% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4734 0.26% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17656 0.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1846311 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.510131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.099317 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 136.122575 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60389 99.72% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 130 0.21% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 8 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1848577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.999494 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.158472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.975371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1464855 79.24% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 267102 14.45% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48426 2.62% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20608 1.11% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12613 0.68% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7404 0.40% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5582 0.30% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4649 0.25% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17338 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1848577 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60747 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.448697 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.033030 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 139.766082 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60580 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 126 0.21% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 11 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 5 0.01% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2559 4 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 1 0.00% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 4 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60557 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60557 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.052843 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.021089 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.041900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29161 48.15% 48.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1164 1.92% 50.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28160 46.50% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2021 3.34% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 45 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60557 # Writes before turning the bus around for reads -system.physmem.totQLat 36942736250 # Total ticks spent queuing -system.physmem.totMemAccLat 73902792500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9856015000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18741.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60747 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.999523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.968024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.037878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 30790 50.69% 50.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1097 1.81% 52.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26995 44.44% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1834 3.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60747 # Writes before turning the bus around for reads +system.physmem.totQLat 58523135000 # Total ticks spent queuing +system.physmem.totMemAccLat 95484522500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9856370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29687.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37491.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.21 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.07 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48437.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 101.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 53.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 101.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 53.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.21 # Data bus utilization in percentage +system.physmem.busUtilRead 0.79 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing -system.physmem.readRowHits 727606 # Number of row buffer hits during reads -system.physmem.writeRowHits 429946 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes -system.physmem.avgGap 406722.41 # Average gap between requests -system.physmem.pageHitRate 38.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6766986240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3692304000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7425061800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3276501840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416045775330 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 368409693000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 885449053890 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.429872 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 610096075500 # Time in different power states -system.physmem_0.memoryStateTime::REF 40814280000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 571360638500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7191102240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3923716500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7949838000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3415193280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 427319070030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 358520838000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 888152489730 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.641687 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 593574305750 # Time in different power states -system.physmem_1.memoryStateTime::REF 40814280000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 587881640500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 246953326 # Number of BP lookups -system.cpu.branchPred.condPredicted 186908369 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15587365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168276583 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165592346 # Number of BTB hits +system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing +system.physmem.readRowHits 727297 # Number of row buffer hits during reads +system.physmem.writeRowHits 428065 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.45 # Row buffer hit rate for writes +system.physmem.avgGap 413252.48 # Average gap between requests +system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6395269440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3399162525 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6797065800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2639461680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 75004519200.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 46893448560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2685169920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 246120093660 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 85384513440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 94763106600 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 570117979365 # Total energy per rank (pJ) +system.physmem_0.averagePower 459.068285 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1131989083250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3611832250 # Time in different power states +system.physmem_0.memoryStateTime::REF 31797904000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 369900280750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 222356311250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 74502708250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 539733299000 # Time in different power states +system.physmem_1.actEnergy 6803606040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3616187190 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7277830560 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2751075720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 76383156720.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47598512910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2658705600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 254833635780 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 85755552000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 89279622225 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 576994094775 # Total energy per rank (pJ) +system.physmem_1.averagePower 464.605041 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1130512338500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3468880500 # Time in different power states +system.physmem_1.memoryStateTime::REF 32377406000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 348347909000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 223320346000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75543655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 558844138750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 246965199 # Number of BP lookups +system.cpu.branchPred.condPredicted 186917374 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15586746 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 168139701 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165606683 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.404866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18556185 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 105918 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 315 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 98.493504 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18556232 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 106082 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 314 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 63 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 252 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 453405484 # DTB read hits -system.cpu.dtb.read_misses 5001335 # DTB read misses +system.cpu.dtb.read_hits 453404968 # DTB read hits +system.cpu.dtb.read_misses 5001226 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 458406819 # DTB read accesses -system.cpu.dtb.write_hits 161377349 # DTB write hits -system.cpu.dtb.write_misses 1709149 # DTB write misses +system.cpu.dtb.read_accesses 458406194 # DTB read accesses +system.cpu.dtb.write_hits 161377184 # DTB write hits +system.cpu.dtb.write_misses 1709229 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163086498 # DTB write accesses -system.cpu.dtb.data_hits 614782833 # DTB hits -system.cpu.dtb.data_misses 6710484 # DTB misses +system.cpu.dtb.write_accesses 163086413 # DTB write accesses +system.cpu.dtb.data_hits 614782152 # DTB hits +system.cpu.dtb.data_misses 6710455 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 621493317 # DTB accesses -system.cpu.itb.fetch_hits 600105517 # ITB hits +system.cpu.dtb.data_accesses 621492607 # DTB accesses +system.cpu.itb.fetch_hits 600133421 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 600105536 # ITB accesses +system.cpu.itb.fetch_accesses 600133440 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,16 +348,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2444549967 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2483804671 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 55126564 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 55133015 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.338468 # CPI: cycles per instruction -system.cpu.ipc 0.747123 # IPC: instructions per cycle +system.cpu.cpi 1.359962 # CPI: cycles per instruction +system.cpu.ipc 0.735315 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction @@ -383,107 +393,107 @@ system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1826378509 # Class of committed instruction -system.cpu.tickCycles 2082292947 # Number of cycles that the object actually ticked -system.cpu.idleCycles 362257020 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9121995 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.838657 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 602779955 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126091 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 66.050180 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16887433500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.838657 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996299 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996299 # Average percentage of cache occupancy +system.cpu.tickCycles 2082494897 # Number of cycles that the object actually ticked +system.cpu.idleCycles 401309774 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9121955 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.932596 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 602775567 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 66.049989 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 17009517500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.932596 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996321 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996321 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1547 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2420 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1466 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2515 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1233656307 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1233656307 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 444297476 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 444297476 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158482479 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158482479 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 602779955 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 602779955 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 602779955 # number of overall hits -system.cpu.dcache.overall_hits::total 602779955 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7239130 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7239130 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2246023 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2246023 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9485153 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9485153 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9485153 # number of overall misses -system.cpu.dcache.overall_misses::total 9485153 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 185791393500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 185791393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110650401500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110650401500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296441795000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296441795000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296441795000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296441795000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 451536606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 451536606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1233653477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1233653477 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 444296125 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 444296125 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158479442 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158479442 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 602775567 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 602775567 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 602775567 # number of overall hits +system.cpu.dcache.overall_hits::total 602775567 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7239086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7239086 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2249060 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2249060 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9488146 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9488146 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9488146 # number of overall misses +system.cpu.dcache.overall_misses::total 9488146 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 201399177000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 201399177000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119572112000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119572112000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 320971289000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 320971289000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 320971289000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 320971289000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 451535211 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 451535211 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 612265108 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 612265108 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 612265108 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 612265108 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 612263713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 612263713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 612263713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 612263713 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016032 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013974 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013974 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015492 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015492 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015492 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015492 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25664.878722 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25664.878722 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49265.034908 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49265.034908 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31253.243358 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31253.243358 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013993 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013993 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015497 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015497 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015497 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015497 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27821.078103 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27821.078103 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53165.372200 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53165.372200 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33828.662523 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33828.662523 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3671998 # number of writebacks -system.cpu.dcache.writebacks::total 3671998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 362 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 358700 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 358700 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 359062 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 359062 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 359062 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 359062 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238768 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238768 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887323 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126091 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126091 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126091 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126091 # number of overall MSHR misses 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# number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285301962000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 285301962000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -492,67 +502,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014905 system.cpu.dcache.demand_mshr_miss_rate::total 0.014905 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014905 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24665.262583 # average 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+system.cpu.icache.demand_avg_miss_latency::cpu.inst 97051.921080 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 97051.921080 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 97051.921080 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 97051.921080 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,262 +571,262 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 3 # number of writebacks system.cpu.icache.writebacks::total 3 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960 # number of 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of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 92498000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 92498000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80170.312500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80170.312500 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80170.312500 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80170.312500 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80170.312500 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80170.312500 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1940039 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31449.191087 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16276000 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1972807 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.250173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 89114668000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 7.970416 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.267708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31398.952962 # Average occupied blocks per requestor +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 96051.921080 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 96051.921080 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 96051.921080 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 96051.921080 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 96051.921080 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 96051.921080 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1940051 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31462.306469 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16275911 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1972819 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.250078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 89697966000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 7.975185 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.025867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31412.305417 # Average occupied blocks per requestor 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0.419672 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419672 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162939 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162939 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162940 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162940 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for demand accesses 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78216.681391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78216.681391 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18249049 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121998 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216116 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86899.894452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86899.894452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 84549.325026 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 84549.325026 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 91448.860765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 91448.860765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18248972 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121958 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1439 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1442 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7239728 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4704694 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7239684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4704671 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6357340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 960 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238768 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1923 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27376100 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819077696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819139328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1940039 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66092544 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11067090 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::CleanEvict 6357335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238721 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1929 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374057 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27375986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819073920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819135744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1940051 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66092288 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11067065 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011402 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011414 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11065651 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1439 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11065623 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1442 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11067090 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12796525500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11067065 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12796468000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1440000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1444500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689136500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13689076500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3911328 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1938842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 3911349 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1938851 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1180436 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032696 # Transaction distribution -system.membus.trans_dist::CleanEvict 906146 # Transaction distribution -system.membus.trans_dist::ReadExReq 792050 # Transaction distribution -system.membus.trans_dist::ReadExResp 792050 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1180436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5883814 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192331648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192331648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1180439 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032692 # Transaction distribution +system.membus.trans_dist::CleanEvict 906159 # Transaction distribution +system.membus.trans_dist::ReadExReq 792059 # Transaction distribution +system.membus.trans_dist::ReadExResp 792059 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1180439 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883847 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5883847 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192332160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192332160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1972486 # Request fanout histogram +system.membus.snoop_fanout::samples 1972498 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1972486 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1972498 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1972486 # Request fanout histogram -system.membus.reqLayer0.occupancy 8508050000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1972498 # Request fanout histogram +system.membus.reqLayer0.occupancy 8507556000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10787775250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10783034500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index b191243cb..1d1d7a36d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index e33a21652..03b7f79ab 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4309 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28058 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -26,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 669587683000 because target called exit() +Exiting @ tick 684199968000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 7435ab9ce..d6615dc1b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629948 # Number of seconds simulated -sim_ticks 629947889500 # Number of ticks simulated -final_tick 629947889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.684200 # Number of seconds simulated +sim_ticks 684199968000 # Number of ticks simulated +final_tick 684199968000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297749 # Simulator instruction rate (inst/s) -host_op_rate 297749 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111692471 # Simulator tick rate (ticks/s) -host_mem_usage 257464 # Number of bytes of host memory used -host_seconds 5640.02 # Real time elapsed on the host -sim_insts 1679312925 # Number of instructions simulated -sim_ops 1679312925 # Number of ops (including micro ops) simulated +host_inst_rate 209715 # Simulator instruction rate (inst/s) +host_op_rate 209715 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82651888 # Simulator tick rate (ticks/s) +host_mem_usage 254604 # Number of bytes of host memory used +host_seconds 8278.09 # Real time elapsed on the host +sim_insts 1736043781 # Number of instructions simulated +sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 56512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 116052224 # Number of bytes read from this memory -system.physmem.bytes_read::total 116108736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 56512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 56512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65771840 # Number of bytes written to this memory -system.physmem.bytes_written::total 65771840 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1813316 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1814199 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1027685 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1027685 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 184225118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 184314827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89709 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89709 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 104408382 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 104408382 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 104408382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 184225118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 288723209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1814199 # Number of read requests accepted -system.physmem.writeReqs 1027685 # Number of write requests accepted -system.physmem.readBursts 1814199 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1027685 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 116025984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82752 # Total number of bytes read from write queue -system.physmem.bytesWritten 65770240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 116108736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65771840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1293 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126674880 # Number of bytes read from this memory +system.physmem.bytes_read::total 126735616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66206592 # Number of bytes written to this memory +system.physmem.bytes_written::total 66206592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1979295 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1980244 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1034478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1034478 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 185143066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 185231836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96764974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96764974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96764974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 185143066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 281996809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1980244 # Number of read requests accepted +system.physmem.writeReqs 1034478 # Number of write requests accepted +system.physmem.readBursts 1980244 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1034478 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 126652288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83328 # Total number of bytes read from write queue +system.physmem.bytesWritten 66205120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126735616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66206592 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1302 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 109825 # Per bank write bursts -system.physmem.perBankRdBursts::1 106113 # Per bank write bursts -system.physmem.perBankRdBursts::2 107421 # Per bank write bursts -system.physmem.perBankRdBursts::3 108541 # Per bank write bursts -system.physmem.perBankRdBursts::4 108748 # Per bank write bursts -system.physmem.perBankRdBursts::5 108721 # Per bank write bursts -system.physmem.perBankRdBursts::6 111475 # Per bank write bursts -system.physmem.perBankRdBursts::7 116266 # Per bank write bursts -system.physmem.perBankRdBursts::8 117532 # Per bank write bursts -system.physmem.perBankRdBursts::9 120021 # Per bank write bursts -system.physmem.perBankRdBursts::10 119000 # Per bank write bursts -system.physmem.perBankRdBursts::11 120366 # Per bank write bursts -system.physmem.perBankRdBursts::12 116224 # Per bank write bursts -system.physmem.perBankRdBursts::13 115367 # Per bank write bursts -system.physmem.perBankRdBursts::14 113352 # Per bank write bursts -system.physmem.perBankRdBursts::15 113934 # Per bank write bursts -system.physmem.perBankWrBursts::0 61679 # Per bank write bursts -system.physmem.perBankWrBursts::1 62003 # Per bank write bursts -system.physmem.perBankWrBursts::2 61008 # Per bank write bursts -system.physmem.perBankWrBursts::3 61698 # Per bank write bursts -system.physmem.perBankWrBursts::4 62148 # Per bank write bursts -system.physmem.perBankWrBursts::5 63666 # Per bank write bursts -system.physmem.perBankWrBursts::6 64723 # Per bank write bursts -system.physmem.perBankWrBursts::7 66137 # Per bank write bursts -system.physmem.perBankWrBursts::8 65915 # Per bank write bursts -system.physmem.perBankWrBursts::9 66335 # Per bank write bursts -system.physmem.perBankWrBursts::10 66021 # Per bank write bursts -system.physmem.perBankWrBursts::11 66389 # Per bank write bursts -system.physmem.perBankWrBursts::12 64907 # Per bank write bursts -system.physmem.perBankWrBursts::13 64927 # Per bank write bursts -system.physmem.perBankWrBursts::14 65328 # Per bank write bursts -system.physmem.perBankWrBursts::15 64776 # Per bank write bursts +system.physmem.perBankRdBursts::0 119682 # Per bank write bursts +system.physmem.perBankRdBursts::1 115093 # Per bank write bursts +system.physmem.perBankRdBursts::2 117079 # Per bank write bursts +system.physmem.perBankRdBursts::3 118658 # Per bank write bursts +system.physmem.perBankRdBursts::4 118799 # Per bank write bursts +system.physmem.perBankRdBursts::5 118596 # Per bank write bursts +system.physmem.perBankRdBursts::6 121104 # Per bank write bursts +system.physmem.perBankRdBursts::7 126057 # Per bank write bursts +system.physmem.perBankRdBursts::8 128556 # Per bank write bursts +system.physmem.perBankRdBursts::9 131368 # Per bank write bursts +system.physmem.perBankRdBursts::10 130043 # Per bank write bursts +system.physmem.perBankRdBursts::11 131744 # Per bank write bursts +system.physmem.perBankRdBursts::12 127398 # Per bank write bursts +system.physmem.perBankRdBursts::13 126519 # Per bank write bursts +system.physmem.perBankRdBursts::14 123764 # Per bank write bursts +system.physmem.perBankRdBursts::15 124482 # Per bank write bursts +system.physmem.perBankWrBursts::0 62070 # Per bank write bursts +system.physmem.perBankWrBursts::1 62408 # Per bank write bursts +system.physmem.perBankWrBursts::2 61409 # Per bank write bursts +system.physmem.perBankWrBursts::3 62103 # Per bank write bursts +system.physmem.perBankWrBursts::4 62566 # Per bank write bursts +system.physmem.perBankWrBursts::5 64096 # Per bank write bursts +system.physmem.perBankWrBursts::6 65160 # Per bank write bursts +system.physmem.perBankWrBursts::7 66609 # Per bank write bursts +system.physmem.perBankWrBursts::8 66404 # Per bank write bursts +system.physmem.perBankWrBursts::9 66820 # Per bank write bursts +system.physmem.perBankWrBursts::10 66475 # Per bank write bursts +system.physmem.perBankWrBursts::11 66816 # Per bank write bursts +system.physmem.perBankWrBursts::12 65322 # Per bank write bursts +system.physmem.perBankWrBursts::13 65320 # Per bank write bursts +system.physmem.perBankWrBursts::14 65711 # Per bank write bursts +system.physmem.perBankWrBursts::15 65166 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 629947397500 # Total gap between requests +system.physmem.totGap 684199865500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1814199 # Read request sizes (log2) +system.physmem.readPktSize::6 1980244 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1027685 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1469096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1034478 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1615224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 253124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 75634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 57932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 65572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 58148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 66372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,139 +194,149 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1631200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 111.449220 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 84.546651 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 143.577205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1240852 76.07% 76.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 269138 16.50% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51923 3.18% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20333 1.25% 97.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12353 0.76% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6354 0.39% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4947 0.30% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3735 0.23% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21565 1.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1631200 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60546 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.938741 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.568202 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 131.498063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60449 99.84% 99.84% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 61 0.10% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1786108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.975625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.936522 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 138.228671 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1386417 77.62% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 276583 15.49% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52891 2.96% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20920 1.17% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12358 0.69% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6524 0.37% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5164 0.29% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3751 0.21% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21500 1.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1786108 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61165 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.352277 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 22.914892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 140.448273 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60991 99.72% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 137 0.22% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 7 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 2 0.00% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60546 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60546 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.973210 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.937472 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.113084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 32669 53.96% 53.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1474 2.43% 56.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 22634 37.38% 93.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3027 5.00% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 624 1.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 106 0.18% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60546 # Writes before turning the bus around for reads -system.physmem.totQLat 37088946500 # Total ticks spent queuing -system.physmem.totMemAccLat 71080934000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9064530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20458.28 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61165 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.912532 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.877578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.101156 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 34708 56.74% 56.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1369 2.24% 58.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21665 35.42% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2721 4.45% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 576 0.94% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 109 0.18% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61165 # Writes before turning the bus around for reads +system.physmem.totQLat 56581400750 # Total ticks spent queuing +system.physmem.totMemAccLat 93686563250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9894710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28591.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39208.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 184.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 104.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 184.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 104.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47341.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 185.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 185.23 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.25 # Data bus utilization in percentage -system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.82 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.61 # Average write queue length when enqueuing -system.physmem.readRowHits 781743 # Number of row buffer hits during reads -system.physmem.writeRowHits 427619 # Number of row buffer hits during writes -system.physmem.readRowHitRate 43.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.61 # Row buffer hit rate for writes -system.physmem.avgGap 221665.42 # Average gap between requests -system.physmem.pageHitRate 42.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5990438160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3268592250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6841434600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3259841760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 41145046800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 279886127580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 132453942750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 472845423900 # Total energy per rank (pJ) -system.physmem_0.averagePower 750.611658 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 218497726500 # Time in different power states -system.physmem_0.memoryStateTime::REF 21035300000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 390413882500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6341433840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3460107750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7299201000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3399395040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 41145046800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 287961158835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125370582000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 474976925265 # Total energy per rank (pJ) -system.physmem_1.averagePower 753.995279 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 206677750500 # Time in different power states -system.physmem_1.memoryStateTime::REF 21035300000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 402234088500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 393343738 # Number of BP lookups -system.cpu.branchPred.condPredicted 308206683 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15638618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 270406177 # Number of BTB lookups -system.cpu.branchPred.BTBHits 266678706 # Number of BTB hits +system.physmem.busUtil 2.20 # Data bus utilization in percentage +system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing +system.physmem.readRowHits 796002 # Number of row buffer hits during reads +system.physmem.writeRowHits 431282 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.69 # Row buffer hit rate for writes +system.physmem.avgGap 226952.89 # Average gap between requests +system.physmem.pageHitRate 40.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6177735060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3283540260 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6819185520 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2643517620 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 44816475600.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 37044798750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1443275040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 170396037690 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 31359460320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 36616359660 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 340610162070 # Total energy per rank (pJ) +system.physmem_0.averagePower 497.822532 # Core power per rank (mW) +system.physmem_0.totalIdleTime 599184631500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1534958250 # Time in different power states +system.physmem_0.memoryStateTime::REF 18981984000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 143840379000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 81664935250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 64497738500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 373679973000 # Time in different power states +system.physmem_1.actEnergy 6575111760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3494739600 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7310460360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2756337480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 45376412640.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 37526229300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1410684000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 175219175340 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 30265452000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 34407180735 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 344356241235 # Total energy per rank (pJ) +system.physmem_1.averagePower 503.297652 # Core power per rank (mW) +system.physmem_1.totalIdleTime 598199672750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1433387500 # Time in different power states +system.physmem_1.memoryStateTime::REF 19217296000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 135130926250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 78815070250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 65349556500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 384253731500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 409436754 # Number of BP lookups +system.cpu.branchPred.condPredicted 318234486 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15963820 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282367334 # Number of BTB lookups +system.cpu.branchPred.BTBHits 278623697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.621529 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24232356 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 43 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 11458 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 743 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 10715 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 54 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 98.674196 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26172484 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 12628 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1002 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 11626 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 615604408 # DTB read hits -system.cpu.dtb.read_misses 10829988 # DTB read misses +system.cpu.dtb.read_hits 645003218 # DTB read hits +system.cpu.dtb.read_misses 12159343 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 626434396 # DTB read accesses -system.cpu.dtb.write_hits 204678819 # DTB write hits -system.cpu.dtb.write_misses 7425838 # DTB write misses +system.cpu.dtb.read_accesses 657162561 # DTB read accesses +system.cpu.dtb.write_hits 218108239 # DTB write hits +system.cpu.dtb.write_misses 7507876 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 212104657 # DTB write accesses -system.cpu.dtb.data_hits 820283227 # DTB hits -system.cpu.dtb.data_misses 18255826 # DTB misses +system.cpu.dtb.write_accesses 225616115 # DTB write accesses +system.cpu.dtb.data_hits 863111457 # DTB hits +system.cpu.dtb.data_misses 19667219 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 838539053 # DTB accesses -system.cpu.itb.fetch_hits 399075166 # ITB hits +system.cpu.dtb.data_accesses 882778676 # DTB accesses +system.cpu.itb.fetch_hits 420694791 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 399075203 # ITB accesses +system.cpu.itb.fetch_accesses 420694828 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -339,751 +349,759 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 23 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1259895780 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1368399937 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 409587649 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3241372877 # Number of instructions fetch has processed -system.cpu.fetch.Branches 393343738 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 290911805 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 828631431 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 43212526 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 431834940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3410573803 # Number of instructions fetch has processed +system.cpu.fetch.Branches 409436754 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 304797183 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 913784247 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45380414 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1670 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 399075166 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7874466 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1259827144 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.572871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.161590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1708 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 420694791 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8284167 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1368311169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.492543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.138689 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 668246093 53.04% 53.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43806893 3.48% 56.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23751936 1.89% 58.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40823777 3.24% 61.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 134784051 10.70% 72.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61318653 4.87% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43063501 3.42% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28777614 2.28% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215254626 17.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 743223403 54.32% 54.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47685517 3.48% 57.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24183643 1.77% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45097399 3.30% 62.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142825430 10.44% 73.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 65953370 4.82% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43585313 3.19% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29408397 2.15% 83.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226348697 16.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1259827144 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.312203 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.572731 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 336809889 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370413676 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 497881112 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 33116842 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21605625 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58265374 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3099960384 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1859 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21605625 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354079753 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 199727925 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5296 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 510193154 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 174215391 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3021993285 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1813082 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19910474 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 129183664 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30561708 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2254247429 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3918399799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3918272154 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 127644 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1331032194 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 923215197 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 126 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 124 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94488821 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 681241316 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255797496 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 84438658 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55736283 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2741763403 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 107 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2499259906 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1517170 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1062450541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 465504121 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 84 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1259827144 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.983812 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.153359 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1368311169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.299208 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.492381 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 353769261 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 432754726 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 524267891 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34829792 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22689499 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62032551 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3256358950 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22689499 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 372017301 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 224454621 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9976 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 537214927 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 211924845 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3173979679 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1947204 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21862090 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 161736150 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 34961727 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2371970000 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4117940809 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4117804241 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136567 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 995767037 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 144 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 143 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99713027 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 717292360 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272467386 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90468830 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58360421 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2884387847 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2620166340 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1550282 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1148344190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 502911540 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1368311169 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.914891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.143845 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 494791866 39.27% 39.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 161324184 12.81% 52.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 149742004 11.89% 63.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141543893 11.24% 75.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 119990032 9.52% 84.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80369213 6.38% 91.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 66025796 5.24% 96.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 32462182 2.58% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13577974 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 564702258 41.27% 41.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169734991 12.40% 53.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158008570 11.55% 65.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149164272 10.90% 76.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126054849 9.21% 85.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84104604 6.15% 91.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68048276 4.97% 96.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34057471 2.49% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14435878 1.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1259827144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1368311169 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12419183 35.12% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18417667 52.09% 87.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4521757 12.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13157745 35.86% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18955564 51.66% 87.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4577828 12.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1641003125 65.66% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896111 0.04% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 23 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 640377775 25.62% 91.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 216982552 8.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1716973131 65.53% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 895059 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 21 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671607156 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230690638 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2499259906 # Type of FU issued -system.cpu.iq.rate 1.983704 # Inst issue rate -system.cpu.iq.fu_busy_cnt 35358607 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014148 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6293293204 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3803117225 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2401572542 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1929523 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1233317 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 883284 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2533656719 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 961794 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60564498 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2620166340 # Type of FU issued +system.cpu.iq.rate 1.914766 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36691137 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014003 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6644947058 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4031627633 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2518705843 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1938210 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1246935 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 885827 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2655891113 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 966364 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69399237 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 251534222 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 355806 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 138747 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 101659209 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 272696697 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372755 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 144718 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 111738884 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 256 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6319064 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 276 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6347426 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21605625 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 137066476 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20199207 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2888644044 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6351774 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 681241316 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255797496 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 107 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 653480 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19719948 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 138747 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10434747 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8530204 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18964951 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2455710851 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 626434405 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 43549049 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22689499 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 153700665 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24607409 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3035418130 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6594075 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 717292360 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272467386 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 793020 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 24069505 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 144718 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10634250 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8701065 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19335315 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2575033857 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 657162570 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45132483 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 146880534 # number of nop insts executed -system.cpu.iew.exec_refs 838539129 # number of memory reference insts executed -system.cpu.iew.exec_branches 303173790 # Number of branches executed -system.cpu.iew.exec_stores 212104724 # Number of stores executed -system.cpu.iew.exec_rate 1.949138 # Inst execution rate -system.cpu.iew.wb_sent 2430569294 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2402455826 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1423499549 # num instructions producing a value -system.cpu.iew.wb_consumers 1834375042 # num instructions consuming a value -system.cpu.iew.wb_rate 1.906869 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776013 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 934600585 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15637980 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1130658933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.564025 # Number of insts commited each cycle +system.cpu.iew.exec_nop 151030158 # number of nop insts executed +system.cpu.iew.exec_refs 882778753 # number of memory reference insts executed +system.cpu.iew.exec_branches 315511040 # Number of branches executed +system.cpu.iew.exec_stores 225616183 # Number of stores executed +system.cpu.iew.exec_rate 1.881785 # Inst execution rate +system.cpu.iew.wb_sent 2549403036 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2519591670 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1487461563 # num instructions producing a value +system.cpu.iew.wb_consumers 1918503373 # num instructions consuming a value +system.cpu.iew.wb_rate 1.841268 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775324 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 998993468 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15963112 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1230277663 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.479162 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.528603 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 654603026 57.90% 57.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 156815138 13.87% 71.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 77634971 6.87% 78.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 50637990 4.48% 83.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28095009 2.48% 85.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18859448 1.67% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19659708 1.74% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22259274 1.97% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102094369 9.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 741569515 60.28% 60.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159647987 12.98% 73.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79500884 6.46% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52016561 4.23% 83.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28471103 2.31% 86.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19445294 1.58% 87.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19999560 1.63% 89.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23041626 1.87% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106585133 8.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1130658933 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1761204444 # Number of instructions committed -system.cpu.commit.committedOps 1761204444 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1230277663 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1819780126 # Number of instructions committed +system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 583845365 # Number of memory references committed -system.cpu.commit.loads 429707085 # Number of loads committed +system.cpu.commit.refs 605324165 # Number of memory references committed +system.cpu.commit.loads 444595663 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 208988363 # Number of branches committed -system.cpu.commit.fp_insts 805327 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1662744776 # Number of committed integer instructions. -system.cpu.commit.function_calls 16089601 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 81891519 4.65% 4.65% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1094662288 62.15% 66.80% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 66 0.00% 66.80% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.80% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 805058 0.05% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 429707085 24.40% 91.25% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 154138280 8.75% 100.00% # Class of committed instruction +system.cpu.commit.branches 214632552 # Number of branches committed +system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. +system.cpu.commit.function_calls 16767440 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1761204444 # Class of committed instruction -system.cpu.commit.bw_lim_events 102094369 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3648383709 # The number of ROB reads -system.cpu.rob.rob_writes 5520911290 # The number of ROB writes -system.cpu.timesIdled 650 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1679312925 # Number of Instructions Simulated -system.cpu.committedOps 1679312925 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.750245 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.750245 # CPI: Total CPI of All Threads -system.cpu.ipc 1.332898 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.332898 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3307128958 # number of integer regfile reads -system.cpu.int_regfile_writes 1925697564 # number of integer regfile writes -system.cpu.fp_regfile_reads 36300 # number of floating regfile reads -system.cpu.fp_regfile_writes 615 # number of floating regfile writes +system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction +system.cpu.commit.bw_lim_events 106585133 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3856686924 # The number of ROB reads +system.cpu.rob.rob_writes 5775715040 # The number of ROB writes +system.cpu.timesIdled 709 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 88768 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1736043781 # Number of Instructions Simulated +system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.788229 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.788229 # CPI: Total CPI of All Threads +system.cpu.ipc 1.268667 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.268667 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3463738117 # number of integer regfile reads +system.cpu.int_regfile_writes 2019389646 # number of integer regfile writes +system.cpu.fp_regfile_reads 39803 # number of floating regfile reads +system.cpu.fp_regfile_writes 598 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 8606834 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.896222 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 685926884 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 8610930 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.657701 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5135502500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.896222 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997777 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997777 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9207265 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.531672 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 712311191 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9211361 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.329636 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5174346500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.531672 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997933 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997933 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 950 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2966 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 666 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2980 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1415363302 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1415363302 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 536911304 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 536911304 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 149015576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 149015576 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1470218079 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1470218079 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 556814159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 556814159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155497028 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155497028 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 685926880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 685926880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 685926880 # number of overall hits -system.cpu.dcache.overall_hits::total 685926880 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12326597 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12326597 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5122704 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5122704 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 712311187 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 712311187 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 712311187 # number of overall hits +system.cpu.dcache.overall_hits::total 712311187 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12960693 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12960693 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5231474 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5231474 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17449301 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17449301 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17449301 # number of overall misses -system.cpu.dcache.overall_misses::total 17449301 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 397459380500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 397459380500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 314315569058 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 314315569058 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 73500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 73500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 711774949558 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 711774949558 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 711774949558 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 711774949558 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549237901 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549237901 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 154138280 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 154138280 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 18192167 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18192167 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18192167 # number of overall misses +system.cpu.dcache.overall_misses::total 18192167 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 452018170000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 452018170000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 345871511780 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 345871511780 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 79500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 79500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 797889681780 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 797889681780 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 797889681780 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 797889681780 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 569774852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 569774852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 703376181 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 703376181 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 703376181 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 703376181 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022443 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022443 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033234 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.033234 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 730503354 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 730503354 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 730503354 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 730503354 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022747 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022747 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032549 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032549 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024808 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024808 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024808 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024808 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32244.047607 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32244.047607 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61357.355228 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61357.355228 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 73500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 73500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40791.029369 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40791.029369 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40791.029369 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40791.029369 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16026921 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9753373 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1104089 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 68174 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.515968 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 143.065876 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3596228 # number of writebacks -system.cpu.dcache.writebacks::total 3596228 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5571741 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5571741 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3266630 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3266630 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8838371 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8838371 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8838371 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8838371 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 6754856 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 6754856 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1856074 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1856074 # number of WriteReq MSHR misses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024904 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024904 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024904 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024904 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34876.080315 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34876.080315 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66113.587066 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66113.587066 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 79500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 79500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43858.968631 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43858.968631 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16718017 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10716708 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1109373 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 69036 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.069789 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 155.233617 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3713171 # number of writebacks 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number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879172 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8610930 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8610930 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8610930 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8610930 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 164940989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 164940989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84797281851 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84797281851 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 72500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 72500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 249738270851 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 249738270851 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 249738270851 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 249738270851 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012299 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012299 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.012042 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.012042 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9211360 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9211360 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9211360 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9211360 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194855974500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 194855974500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91510360097 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 91510360097 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 78500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 78500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286366334597 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 286366334597 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286366334597 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 286366334597 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012242 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012242 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012242 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012242 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24418.135487 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24418.135487 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45686.369105 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45686.369105 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 72500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 72500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29002.473699 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29002.473699 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29002.473699 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29002.473699 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 744.964371 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 399073789 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 883 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 451952.195923 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26575.419847 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26575.419847 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48697.170933 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48697.170933 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 78500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 78500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31088.388099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31088.388099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31088.388099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31088.388099 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 753.632230 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 420693280 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 443301.664910 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 744.964371 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.363752 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.363752 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 883 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 883 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.431152 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 798151215 # Number of tag accesses -system.cpu.icache.tags.data_accesses 798151215 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 399073789 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 399073789 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 399073789 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 399073789 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 399073789 # number of overall hits -system.cpu.icache.overall_hits::total 399073789 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1377 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1377 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1377 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1377 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1377 # number of overall misses -system.cpu.icache.overall_misses::total 1377 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 106712499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 106712499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 106712499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 106712499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 106712499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 106712499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 399075166 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 399075166 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 399075166 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 399075166 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 399075166 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 399075166 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77496.368192 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77496.368192 # average ReadReq miss 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rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.154936 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.163073 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.163073 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.210583 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.210664 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214875 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214956 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.210583 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.210664 # miss rate for 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83501.698754 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90424.584297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 90421.214817 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214875 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214956 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97792.362802 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97792.362802 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 97461.538462 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 97461.538462 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99078.804750 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99078.804750 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 97461.538462 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98569.496462 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98568.965491 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 97461.538462 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98569.496462 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98568.965491 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1027685 # number of writebacks -system.cpu.l2cache.writebacks::total 1027685 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 164 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 164 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 766745 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 766745 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 883 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 883 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1046571 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1046571 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 883 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1813316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1814199 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 883 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1813316 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1814199 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62350175000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62350175000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64902000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64902000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 83485010500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 83485010500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64902000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145835185500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 145900087500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64902000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145835185500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 145900087500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1034478 # number of writebacks +system.cpu.l2cache.writebacks::total 1034478 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 783612 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 783612 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1195683 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1195683 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1979295 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1980244 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1979295 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1980244 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68795149000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68795149000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 83001000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 83001000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 106510012500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 106510012500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 83001000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 175305161500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 175388162500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 83001000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 175305161500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 175388162500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413097 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413097 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.416995 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.416995 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.154936 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.154936 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.163073 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.163073 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.210583 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.210664 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214956 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.210583 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.210664 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81318.006638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81318.006638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73501.698754 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73501.698754 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79770.039969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79770.039969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73501.698754 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80424.584297 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80421.214817 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73501.698754 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80424.584297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80421.214817 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 17218648 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 8606834 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214956 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87792.362802 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87792.362802 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 87461.538462 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 87461.538462 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89078.804750 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89078.804750 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18419576 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207266 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1383 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1383 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1448 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1448 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 6755724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4623913 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5764670 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1856089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1856089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 883 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6754842 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1766 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 25828695 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 25830461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 781258112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 781314624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1781749 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65771840 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 10393563 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000133 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011535 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7333122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4747649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6407418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332173 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27631886 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827170048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827230848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1947802 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66206592 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11160112 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011390 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10392180 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1383 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11158664 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1448 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10393563 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12205552000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11160112 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12922960000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1324500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1423500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12916395000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3594729 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1780530 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 13817041500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 3926838 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1946594 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1047454 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1027685 # Transaction distribution -system.membus.trans_dist::CleanEvict 752845 # Transaction distribution -system.membus.trans_dist::ReadExReq 766745 # Transaction distribution -system.membus.trans_dist::ReadExResp 766745 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1047454 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5408928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5408928 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 181880576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 181880576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1196632 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1034478 # Transaction distribution +system.membus.trans_dist::CleanEvict 912116 # Transaction distribution +system.membus.trans_dist::ReadExReq 783612 # Transaction distribution +system.membus.trans_dist::ReadExResp 783612 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1196632 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5907082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5907082 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192942208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192942208 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1814199 # Request fanout histogram +system.membus.snoop_fanout::samples 1980244 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1814199 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1980244 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1814199 # Request fanout histogram -system.membus.reqLayer0.occupancy 8122837000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9853981000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1980244 # Request fanout histogram +system.membus.reqLayer0.occupancy 8533086500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 10770167500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini index 9ef5c346e..7df53f247 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout index b6bf1e68a..b95f9cdb7 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:58:37 -gem5 executing on e108600-lin, pid 24092 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:01 +gem5 executing on e108600-lin, pid 17341 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1128033563500 because target called exit() +Exiting @ tick 1150225722500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index ddbab1eb8..16fb45e1d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.130744 # Number of seconds simulated -sim_ticks 1130744162500 # Number of ticks simulated -final_tick 1130744162500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150226 # Number of seconds simulated +sim_ticks 1150225722500 # Number of ticks simulated +final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210155 # Simulator instruction rate (inst/s) -host_op_rate 226410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153850224 # Simulator tick rate (ticks/s) -host_mem_usage 274312 # Number of bytes of host memory used -host_seconds 7349.64 # Real time elapsed on the host +host_inst_rate 267770 # Simulator instruction rate (inst/s) +host_op_rate 288482 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 199406485 # Simulator tick rate (ticks/s) +host_mem_usage 271372 # Number of bytes of host memory used +host_seconds 5768.25 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132094976 # Number of bytes read from this memory -system.physmem.bytes_read::total 132145216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory +system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67850112 # Number of bytes written to this memory -system.physmem.bytes_written::total 67850112 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory +system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063984 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2064769 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1060158 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1060158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 116821276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116865707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60004831 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60004831 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60004831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 116821276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 176870538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2064769 # Number of read requests accepted -system.physmem.writeReqs 1060158 # Number of write requests accepted -system.physmem.readBursts 2064769 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1060158 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 132060352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue -system.physmem.bytesWritten 67848640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132145216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67850112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064767 # Number of read requests accepted +system.physmem.writeReqs 1060156 # Number of write requests accepted +system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue +system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67849984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1300 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128520 # Per bank write bursts -system.physmem.perBankRdBursts::1 125806 # Per bank write bursts -system.physmem.perBankRdBursts::2 122672 # Per bank write bursts -system.physmem.perBankRdBursts::3 124571 # Per bank write bursts +system.physmem.perBankRdBursts::0 128524 # Per bank write bursts +system.physmem.perBankRdBursts::1 125801 # Per bank write bursts +system.physmem.perBankRdBursts::2 122666 # Per bank write bursts +system.physmem.perBankRdBursts::3 124575 # Per bank write bursts system.physmem.perBankRdBursts::4 123572 # Per bank write bursts -system.physmem.perBankRdBursts::5 123679 # Per bank write bursts -system.physmem.perBankRdBursts::6 124365 # Per bank write bursts -system.physmem.perBankRdBursts::7 124958 # Per bank write bursts -system.physmem.perBankRdBursts::8 132489 # Per bank write bursts -system.physmem.perBankRdBursts::9 134780 # Per bank write bursts -system.physmem.perBankRdBursts::10 133233 # Per bank write bursts -system.physmem.perBankRdBursts::11 134506 # Per bank write bursts -system.physmem.perBankRdBursts::12 134518 # Per bank write bursts -system.physmem.perBankRdBursts::13 134594 # Per bank write bursts -system.physmem.perBankRdBursts::14 130540 # Per bank write bursts -system.physmem.perBankRdBursts::15 130640 # Per bank write bursts +system.physmem.perBankRdBursts::5 123680 # Per bank write bursts +system.physmem.perBankRdBursts::6 124357 # Per bank write bursts +system.physmem.perBankRdBursts::7 124965 # Per bank write bursts +system.physmem.perBankRdBursts::8 132488 # Per bank write bursts +system.physmem.perBankRdBursts::9 134781 # Per bank write bursts +system.physmem.perBankRdBursts::10 133246 # Per bank write bursts +system.physmem.perBankRdBursts::11 134508 # Per bank write bursts +system.physmem.perBankRdBursts::12 134524 # Per bank write bursts +system.physmem.perBankRdBursts::13 134597 # Per bank write bursts +system.physmem.perBankRdBursts::14 130537 # Per bank write bursts +system.physmem.perBankRdBursts::15 130646 # Per bank write bursts system.physmem.perBankWrBursts::0 66781 # Per bank write bursts -system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::1 64940 # Per bank write bursts system.physmem.perBankWrBursts::2 63173 # Per bank write bursts system.physmem.perBankWrBursts::3 63584 # Per bank write bursts system.physmem.perBankWrBursts::4 63558 # Per bank write bursts system.physmem.perBankWrBursts::5 63644 # Per bank write bursts system.physmem.perBankWrBursts::6 65047 # Per bank write bursts -system.physmem.perBankWrBursts::7 66055 # Per bank write bursts -system.physmem.perBankWrBursts::8 67972 # Per bank write bursts -system.physmem.perBankWrBursts::9 68438 # Per bank write bursts -system.physmem.perBankWrBursts::10 68161 # Per bank write bursts -system.physmem.perBankWrBursts::11 68586 # Per bank write bursts -system.physmem.perBankWrBursts::12 68040 # Per bank write bursts -system.physmem.perBankWrBursts::13 68530 # Per bank write bursts +system.physmem.perBankWrBursts::7 66059 # Per bank write bursts +system.physmem.perBankWrBursts::8 67975 # Per bank write bursts +system.physmem.perBankWrBursts::9 68435 # Per bank write bursts +system.physmem.perBankWrBursts::10 68155 # Per bank write bursts +system.physmem.perBankWrBursts::11 68585 # Per bank write bursts +system.physmem.perBankWrBursts::12 68036 # Per bank write bursts +system.physmem.perBankWrBursts::13 68532 # Per bank write bursts system.physmem.perBankWrBursts::14 67159 # Per bank write bursts system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1130744067500 # Total gap between requests +system.physmem.totGap 1150225621500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2064769 # Read request sizes (log2) +system.physmem.readPktSize::6 2064767 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1060158 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1931837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131592 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060156 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,103 +194,114 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1925169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.839212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.850367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 126.421931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1496084 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 309482 16.08% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52255 2.71% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20716 1.08% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12793 0.66% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7748 0.40% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5753 0.30% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5054 0.26% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15284 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1925169 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.244314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.928422 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.698604 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61952 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.101710 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.070337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.034747 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 28322 45.69% 45.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1015 1.64% 47.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 30732 49.58% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1873 3.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 43 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61990 # Writes before turning the bus around for reads -system.physmem.totQLat 38536102500 # Total ticks spent queuing -system.physmem.totMemAccLat 77225658750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10317215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18675.63 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads +system.physmem.totQLat 59945214750 # Total ticks spent queuing +system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37425.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.38 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing -system.physmem.readRowHits 775929 # Number of row buffer hits during reads -system.physmem.writeRowHits 422476 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.85 # Row buffer hit rate for writes -system.physmem.avgGap 361846.55 # Average gap between requests -system.physmem.pageHitRate 38.37 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7091695800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3869476875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7785421800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3348753840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 423921506085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 306584736000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 826456199280 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.896688 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 507283799000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37757980000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 585701078500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7462581840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4071845250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8309316600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3520920960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 432965070225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 298651785000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 828836128755 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.001436 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 494051909000 # Time in different power states -system.physmem_1.memoryStateTime::REF 37757980000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 598934101500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019432 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610009 # Number of conditional branches predicted +system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing +system.physmem.readRowHits 775403 # Number of row buffer hits during reads +system.physmem.writeRowHits 420503 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes +system.physmem.avgGap 368081.27 # Average gap between requests +system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.667814 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states +system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states +system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.748583 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states +system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019882 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131647101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324380 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918400 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. @@ -298,7 +309,7 @@ system.cpu.branchPred.indirectHits 232 # Nu system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2261488325 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300451445 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363718 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.464161 # CPI: cycles per instruction -system.cpu.ipc 0.682985 # IPC: instructions per cycle +system.cpu.cpi 1.489387 # CPI: cycles per instruction +system.cpu.ipc 0.671417 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -464,61 +475,61 @@ system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1844743027 # Number of cycles that the object actually ticked -system.cpu.idleCycles 416745298 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220102 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.712457 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624495296 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224198 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701853 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9823555500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.712457 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997488 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997488 # Average percentage of cache occupancy +system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220107 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391740 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391740 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454164183 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454164183 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170330990 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170330990 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624495173 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624495173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624495174 # number of overall hits -system.cpu.dcache.overall_hits::total 624495174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333416 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333416 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2255057 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2255057 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits +system.cpu.dcache.overall_hits::total 624493043 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9588473 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9588473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9588475 # number of overall misses -system.cpu.dcache.overall_misses::total 9588475 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192638967000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 111261397000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 303900364000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 303900364000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 303900364000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 303900364000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497599 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses +system.cpu.dcache.overall_misses::total 9590309 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -527,64 +538,64 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083646 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083646 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083649 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083649 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31694.344240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31694.337629 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3670051 # number of writebacks -system.cpu.dcache.writebacks::total 3670051 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks +system.cpu.dcache.writebacks::total 3670055 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364227 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364227 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364276 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364276 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333367 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333367 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224197 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224197 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224198 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224198 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86626211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86626211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 271929707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 271929782500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -595,70 +606,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency 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-system.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76614.355231 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76614.355231 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 91001.216545 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency 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miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2032334 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31895.835750 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor 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ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081702 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6081702 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081704 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6081704 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7160208 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7160245 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7160215 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7160252 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7160208 # number of overall hits -system.cpu.l2cache.overall_hits::total 7160245 # number of overall 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accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3670051 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 2063988 # number of overall misses +system.cpu.l2cache.overall_misses::total 2064773 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282559500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 78282559500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72328000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 72328000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 72328000 # number of demand (read+write) miss cycles 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accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890830 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890834 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890834 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333368 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7333368 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333369 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7333369 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 822 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9224198 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9225020 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9224203 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9225025 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 822 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9224198 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9225020 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429612 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.429612 # miss rate for ReadExReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 9224203 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9225025 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.429611 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954988 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170681 # miss rate for ReadSharedReq accesses @@ -783,26 +794,26 @@ system.cpu.l2cache.demand_miss_rate::total 0.223823 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89177.093746 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89177.093746 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77071.337580 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77071.337580 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88236.430485 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88236.430485 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88602.261505 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88602.261505 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1060158 # number of writebacks -system.cpu.l2cache.writebacks::total 1060158 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1060156 # number of writebacks +system.cpu.l2cache.writebacks::total 1060156 # number of writebacks system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits @@ -811,128 +822,128 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 6 system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812324 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 812324 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812323 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 812323 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251660 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251660 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251659 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251659 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2063984 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2064769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2063982 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2064767 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2063984 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2064769 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64317453500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64317453500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52651000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52651000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 97925523500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 97925523500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52651000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162242977000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162295628000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52651000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162242977000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162295628000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.223823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.223823 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445155 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220147 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1445 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4730209 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668513 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670190 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825231936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 825286656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2032337 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67850112 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11257357 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016509 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825232512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825287232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032334 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67849984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257359 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11254306 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3045 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254309 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11257357 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12892661500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257359 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892670500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836299994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4095876 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2031264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1252445 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1060158 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252444 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution system.membus.trans_dist::CleanEvict 970949 # Transaction distribution -system.membus.trans_dist::ReadExReq 812324 # Transaction distribution -system.membus.trans_dist::ReadExResp 812324 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1252445 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6160645 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 199995328 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 812323 # Transaction distribution +system.membus.trans_dist::ReadExResp 812323 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199995072 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2064769 # Request fanout histogram +system.membus.snoop_fanout::samples 2064767 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2064769 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2064769 # Request fanout histogram -system.membus.reqLayer0.occupancy 8803577000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064767 # Request fanout histogram +system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11289358000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 8b8fd1b4f..5a7d7b1a5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 00cbc440d..fbc8b4e01 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12200 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:48:52 +gem5 executing on e108600-lin, pid 17438 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 767803843500 because target called exit() +Exiting @ tick 787742202500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 4f03996ba..ea5c16164 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.770752 # Number of seconds simulated -sim_ticks 770752376500 # Number of ticks simulated -final_tick 770752376500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.787742 # Number of seconds simulated +sim_ticks 787742202500 # Number of ticks simulated +final_tick 787742202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147248 # Simulator instruction rate (inst/s) -host_op_rate 158637 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73478006 # Simulator tick rate (ticks/s) -host_mem_usage 329736 # Number of bytes of host memory used -host_seconds 10489.57 # Real time elapsed on the host +host_inst_rate 201500 # Simulator instruction rate (inst/s) +host_op_rate 217086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 102767126 # Simulator tick rate (ticks/s) +host_mem_usage 327820 # Number of bytes of host memory used +host_seconds 7665.31 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236002624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63781504 # Number of bytes read from this memory -system.physmem.bytes_read::total 299849792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236035776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63780672 # Number of bytes read from this memory +system.physmem.bytes_read::total 299882112 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104607936 # Number of bytes written to this memory -system.physmem.bytes_written::total 104607936 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 104579136 # Number of bytes written to this memory +system.physmem.bytes_written::total 104579136 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3687541 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996586 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4685153 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634499 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634499 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306197725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82752264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389035183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 135721847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 135721847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 135721847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306197725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82752264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 524757030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4685154 # Number of read requests accepted -system.physmem.writeReqs 1634499 # Number of write requests accepted -system.physmem.readBursts 4685154 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634499 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299347712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 502144 # Total number of bytes read from write queue -system.physmem.bytesWritten 104604544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299849856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104607936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7846 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one +system.physmem.num_reads::cpu.data 3688059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996573 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4685658 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634049 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634049 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 83357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299635814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 80966428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380685599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 83357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 83357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132758072 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132758072 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132758072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 83357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299635814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 80966428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 513443671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4685658 # Number of read requests accepted +system.physmem.writeReqs 1634049 # Number of write requests accepted +system.physmem.readBursts 4685658 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634049 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299378880 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 503232 # Total number of bytes read from write queue +system.physmem.bytesWritten 104576512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299882112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104579136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7863 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 17 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301314 # Per bank write bursts -system.physmem.perBankRdBursts::1 301808 # Per bank write bursts -system.physmem.perBankRdBursts::2 285079 # Per bank write bursts -system.physmem.perBankRdBursts::3 287721 # Per bank write bursts -system.physmem.perBankRdBursts::4 288732 # Per bank write bursts -system.physmem.perBankRdBursts::5 286480 # Per bank write bursts -system.physmem.perBankRdBursts::6 281880 # Per bank write bursts -system.physmem.perBankRdBursts::7 278193 # Per bank write bursts -system.physmem.perBankRdBursts::8 293719 # Per bank write bursts -system.physmem.perBankRdBursts::9 299847 # Per bank write bursts -system.physmem.perBankRdBursts::10 291529 # Per bank write bursts -system.physmem.perBankRdBursts::11 297903 # Per bank write bursts -system.physmem.perBankRdBursts::12 299405 # Per bank write bursts -system.physmem.perBankRdBursts::13 299387 # Per bank write bursts -system.physmem.perBankRdBursts::14 294305 # Per bank write bursts -system.physmem.perBankRdBursts::15 290006 # Per bank write bursts -system.physmem.perBankWrBursts::0 103629 # Per bank write bursts -system.physmem.perBankWrBursts::1 101748 # Per bank write bursts -system.physmem.perBankWrBursts::2 99222 # Per bank write bursts -system.physmem.perBankWrBursts::3 99944 # Per bank write bursts -system.physmem.perBankWrBursts::4 98990 # Per bank write bursts -system.physmem.perBankWrBursts::5 98822 # Per bank write bursts -system.physmem.perBankWrBursts::6 102440 # Per bank write bursts -system.physmem.perBankWrBursts::7 104048 # Per bank write bursts -system.physmem.perBankWrBursts::8 105134 # Per bank write bursts -system.physmem.perBankWrBursts::9 103994 # Per bank write bursts -system.physmem.perBankWrBursts::10 101818 # Per bank write bursts -system.physmem.perBankWrBursts::11 102570 # Per bank write bursts -system.physmem.perBankWrBursts::12 102850 # Per bank write bursts -system.physmem.perBankWrBursts::13 102376 # Per bank write bursts -system.physmem.perBankWrBursts::14 104237 # Per bank write bursts -system.physmem.perBankWrBursts::15 102624 # Per bank write bursts +system.physmem.perBankRdBursts::0 301431 # Per bank write bursts +system.physmem.perBankRdBursts::1 301123 # Per bank write bursts +system.physmem.perBankRdBursts::2 285299 # Per bank write bursts +system.physmem.perBankRdBursts::3 287676 # Per bank write bursts +system.physmem.perBankRdBursts::4 288751 # Per bank write bursts +system.physmem.perBankRdBursts::5 286469 # Per bank write bursts +system.physmem.perBankRdBursts::6 281133 # Per bank write bursts +system.physmem.perBankRdBursts::7 278330 # Per bank write bursts +system.physmem.perBankRdBursts::8 294107 # Per bank write bursts +system.physmem.perBankRdBursts::9 299584 # Per bank write bursts +system.physmem.perBankRdBursts::10 292343 # Per bank write bursts +system.physmem.perBankRdBursts::11 297976 # Per bank write bursts +system.physmem.perBankRdBursts::12 299704 # Per bank write bursts +system.physmem.perBankRdBursts::13 299189 # Per bank write bursts +system.physmem.perBankRdBursts::14 294388 # Per bank write bursts +system.physmem.perBankRdBursts::15 290292 # Per bank write bursts +system.physmem.perBankWrBursts::0 103694 # Per bank write bursts +system.physmem.perBankWrBursts::1 101682 # Per bank write bursts +system.physmem.perBankWrBursts::2 99052 # Per bank write bursts +system.physmem.perBankWrBursts::3 99844 # Per bank write bursts +system.physmem.perBankWrBursts::4 99095 # Per bank write bursts +system.physmem.perBankWrBursts::5 98699 # Per bank write bursts +system.physmem.perBankWrBursts::6 102473 # Per bank write bursts +system.physmem.perBankWrBursts::7 104090 # Per bank write bursts +system.physmem.perBankWrBursts::8 105068 # Per bank write bursts +system.physmem.perBankWrBursts::9 104102 # Per bank write bursts +system.physmem.perBankWrBursts::10 101990 # Per bank write bursts +system.physmem.perBankWrBursts::11 102510 # Per bank write bursts +system.physmem.perBankWrBursts::12 102612 # Per bank write bursts +system.physmem.perBankWrBursts::13 102296 # Per bank write bursts +system.physmem.perBankWrBursts::14 104281 # Per bank write bursts +system.physmem.perBankWrBursts::15 102520 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 770752366000 # Total gap between requests +system.physmem.totGap 787742161500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4685154 # Read request sizes (log2) +system.physmem.readPktSize::6 4685658 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634499 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2776424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1031022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 327510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 146630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 80164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634049 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2727854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1051064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 327817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 158136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 89940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,40 +149,40 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 100949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 109545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 110077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 108778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see @@ -198,130 +198,133 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4255173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.931559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.862227 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.833954 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3394354 79.77% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 663703 15.60% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94226 2.21% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35436 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22765 0.53% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12171 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7342 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19831 0.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4255173 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97794 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.827914 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.473591 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 93707 95.82% 95.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1671 1.71% 97.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 768 0.79% 98.31% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 406 0.42% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 365 0.37% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 337 0.34% 99.45% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 234 0.24% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 165 0.17% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 89 0.09% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 24 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 12 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1664-1791 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3968-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97794 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97794 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.713152 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.671812 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.223073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68724 70.27% 70.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1896 1.94% 72.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18671 19.09% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5634 5.76% 97.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1729 1.77% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 613 0.63% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 266 0.27% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 147 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 67 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 30 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97794 # Writes before turning the bus around for reads -system.physmem.totQLat 128325813562 # Total ticks spent queuing -system.physmem.totMemAccLat 216025338562 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23386540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27435.83 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4258602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.856263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.818587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.740363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3399214 79.82% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 662534 15.56% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94110 2.21% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35203 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22640 0.53% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12473 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7407 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5223 0.12% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19798 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4258602 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97968 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.747867 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.462080 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95523 97.50% 97.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1197 1.22% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 705 0.72% 99.45% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 407 0.42% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 106 0.11% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 17 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97968 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97968 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.678997 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.638691 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.208217 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 70313 71.77% 71.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1920 1.96% 73.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17565 17.93% 91.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5314 5.42% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1711 1.75% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 637 0.65% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 262 0.27% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 130 0.13% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 63 0.06% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97968 # Writes before turning the bus around for reads +system.physmem.totQLat 162666982970 # Total ticks spent queuing +system.physmem.totMemAccLat 250375639220 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23388975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34774.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46185.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 135.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 135.72 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53524.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.09 # Data bus utilization in percentage -system.physmem.busUtilRead 3.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing -system.physmem.readRowHits 1715091 # Number of row buffer hits during reads -system.physmem.writeRowHits 341475 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.89 # Row buffer hit rate for writes -system.physmem.avgGap 121961.18 # Average gap between requests -system.physmem.pageHitRate 32.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15989112720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8724218250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18025846800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5241069360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 417928675995 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 95843265750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 612093526155 # Total energy per rank (pJ) -system.physmem_0.averagePower 794.157652 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 156909498029 # Time in different power states -system.physmem_0.memoryStateTime::REF 25736880000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 588099785971 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16179556680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8828131125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18455494200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5349602880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 412908393870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100247038500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 612309554535 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.437909 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 164276600328 # Time in different power states -system.physmem_1.memoryStateTime::REF 25736880000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 580733308672 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286275195 # Number of BP lookups -system.cpu.branchPred.condPredicted 223398341 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14628424 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157667483 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150349199 # Number of BTB hits +system.physmem.busUtil 4.01 # Data bus utilization in percentage +system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing +system.physmem.readRowHits 1712898 # Number of row buffer hits during reads +system.physmem.writeRowHits 340301 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 20.83 # Row buffer hit rate for writes +system.physmem.avgGap 124648.53 # Average gap between requests +system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15106540680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8029309200 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16494913680 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4221043380 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 59407414560.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64582002630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1606944480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 223006056720 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 35875852320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 16122239730 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 444464207160 # Total energy per rank (pJ) +system.physmem_0.averagePower 564.225454 # Core power per rank (mW) +system.physmem_0.totalIdleTime 641904162368 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1401750889 # Time in different power states +system.physmem_0.memoryStateTime::REF 25151370000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 59428702250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 93425472309 # Time in different power states +system.physmem_0.memoryStateTime::ACT 119284909993 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 489049997059 # Time in different power states +system.physmem_1.actEnergy 15299891880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8132085390 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 16904542620 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4308478380 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 58934141760.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64765265610 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1612336320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 219700492200 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 35552759520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18091245240 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 443312102310 # Total energy per rank (pJ) +system.physmem_1.averagePower 562.762917 # Core power per rank (mW) +system.physmem_1.totalIdleTime 641480248383 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1450220904 # Time in different power states +system.physmem_1.memoryStateTime::REF 24952394000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67105561000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 92583809905 # Time in different power states +system.physmem_1.memoryStateTime::ACT 119858377963 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 481791838728 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286283098 # Number of BP lookups +system.cpu.branchPred.condPredicted 223408244 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630421 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158004936 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150354998 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.358406 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16643020 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3069 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1906 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1163 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 137 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.158418 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16643073 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3065 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1898 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1167 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 134 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,7 +354,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,7 +384,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -411,7 +414,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -442,129 +445,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1541504754 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1575484406 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925502 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067484101 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286275195 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166994125 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1512857238 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29281631 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 279 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1018 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656940019 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 946 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1541424852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.436951 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229037 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13928690 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067537239 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286283098 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166999969 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1546809233 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29285745 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 303 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 986 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656964714 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1575382084 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.406011 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.233492 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 459011037 29.78% 29.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465435057 30.20% 59.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101419068 6.58% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515559690 33.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 492942163 31.29% 31.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465443083 29.54% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101428647 6.44% 67.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515568191 32.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1541424852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185712 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.341212 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74709451 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 544021839 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849845592 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58207832 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14640138 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42201657 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 726 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037180089 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52484609 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14640138 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139806563 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 462600801 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15884 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837785307 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86576159 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976384850 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26739549 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45323653 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126929 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1602638 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25499860 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985860548 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128169124 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432875929 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1575382084 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181711 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.312318 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74686824 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577980395 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849907031 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58165638 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642196 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42200734 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 724 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037196735 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52499519 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642196 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139768268 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 492678513 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15538 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837819054 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 90458515 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976393108 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26740093 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45400307 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126273 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1723349 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 29315109 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985867653 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128208959 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432891999 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310961603 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 175 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111534180 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542566077 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199303375 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26892889 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29237160 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947969517 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857492369 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13496690 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283937332 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647289356 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1541424852 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.205049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150817 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310968708 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 177 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 176 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111448171 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542564068 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199306440 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26831952 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28868587 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947979256 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 230 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857513748 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13517148 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283947070 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647252748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1575382084 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.179088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151868 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 588435916 38.17% 38.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326131475 21.16% 59.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378210554 24.54% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219654013 14.25% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28986723 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6171 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 622503864 39.51% 39.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326012726 20.69% 60.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378121823 24.00% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219723484 13.95% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29014011 1.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1541424852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1575382084 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166021321 40.99% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1993 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191489776 47.28% 88.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47539480 11.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166098751 40.96% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2024 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191460462 47.22% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47920671 11.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138243662 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800931 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138250302 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801028 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -592,82 +595,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532135699 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186312026 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532139540 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186322827 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857492369 # Type of FU issued -system.cpu.iq.rate 1.204986 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405052570 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218064 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5674958613 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231919871 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805704142 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 1857513748 # Type of FU issued +system.cpu.iq.rate 1.179011 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405481908 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218293 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5709408399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231939413 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805717250 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262544806 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262995523 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17811536 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 17822173 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84259743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66618 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13244 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24456330 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84257734 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66715 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13309 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24459395 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4512030 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4891489 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4550351 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4849996 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14640138 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25364964 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1346928 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947969899 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642196 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25436916 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1454941 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947979633 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542566077 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199303375 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159350 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1186169 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13244 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7699482 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8703162 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16402644 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827831567 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516957415 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29660802 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542564068 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199306440 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 168 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1294449 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13309 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700831 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8703764 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16404595 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827842620 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516961097 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29671128 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151 # number of nop insts executed -system.cpu.iew.exec_refs 698708795 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542425 # Number of branches executed -system.cpu.iew.exec_stores 181751380 # Number of stores executed -system.cpu.iew.exec_rate 1.185745 # Inst execution rate -system.cpu.iew.wb_sent 1808736265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805704212 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169174812 # num instructions producing a value -system.cpu.iew.wb_consumers 1689572222 # num instructions consuming a value -system.cpu.iew.wb_rate 1.171391 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258041892 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 147 # number of nop insts executed +system.cpu.iew.exec_refs 698716504 # number of memory reference insts executed +system.cpu.iew.exec_branches 229543654 # Number of branches executed +system.cpu.iew.exec_stores 181755407 # Number of stores executed +system.cpu.iew.exec_rate 1.160178 # Inst execution rate +system.cpu.iew.wb_sent 1808745333 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805717319 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169202335 # num instructions producing a value +system.cpu.iew.wb_consumers 1689603795 # num instructions consuming a value +system.cpu.iew.wb_rate 1.146135 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691998 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258049766 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14627747 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1501940299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.107922 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025263 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629745 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1535892995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.083430 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.009496 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 921653315 61.36% 61.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250636600 16.69% 78.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110060462 7.33% 85.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55269176 3.68% 89.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29319156 1.95% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34080655 2.27% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24723288 1.65% 94.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18133421 1.21% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58064226 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 955612705 62.22% 62.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250634240 16.32% 78.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110090472 7.17% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55300497 3.60% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29246766 1.90% 91.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34056030 2.22% 93.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24731317 1.61% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18107101 1.18% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58113867 3.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1501940299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1535892995 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -713,78 +716,78 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58064226 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3365949800 # The number of ROB reads -system.cpu.rob.rob_writes 3883638365 # The number of ROB writes -system.cpu.timesIdled 837 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79902 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58113867 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3399860729 # The number of ROB reads +system.cpu.rob.rob_writes 3883658641 # The number of ROB writes +system.cpu.timesIdled 841 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 102322 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.998020 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.998020 # CPI: Total CPI of All Threads -system.cpu.ipc 1.001984 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.001984 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175818987 # number of integer regfile reads -system.cpu.int_regfile_writes 1261576435 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 52 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965775009 # number of cc regfile reads -system.cpu.cc_regfile_writes 551856674 # number of cc regfile writes -system.cpu.misc_regfile_reads 675846934 # number of misc regfile reads +system.cpu.cpi 1.020020 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.020020 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175838440 # number of integer regfile reads +system.cpu.int_regfile_writes 1261579513 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965813253 # number of cc regfile reads +system.cpu.cc_regfile_writes 551861987 # number of cc regfile writes +system.cpu.misc_regfile_reads 675852638 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003150 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964340 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638065664 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17003662 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 79206500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964340 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17003360 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963277 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638058665 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17003872 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524316 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 83293500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963277 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999928 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999928 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 406 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335709608 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335709608 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469347574 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469347574 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168717937 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168717937 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335696042 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335696042 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469342719 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469342719 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168715791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168715791 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638065511 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638065511 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638065511 # number of overall hits -system.cpu.dcache.overall_hits::total 638065511 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17419228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17419228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3868110 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3868110 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638058510 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638058510 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638058510 # number of overall hits +system.cpu.dcache.overall_hits::total 638058510 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17417195 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17417195 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3870256 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3870256 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287338 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287338 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287340 # number of overall misses -system.cpu.dcache.overall_misses::total 21287340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 416423435500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 150253086257 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 199500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 566676521757 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 566676521757 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 566676521757 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 566676521757 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486766802 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486766802 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21287451 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21287451 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21287453 # number of overall misses +system.cpu.dcache.overall_misses::total 21287453 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 440618340000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 440618340000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157333375444 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157333375444 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 245500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 597951715444 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 597951715444 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 597951715444 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 597951715444 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486759914 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486759914 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -793,470 +796,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659352849 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659352849 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659352851 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659352851 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022413 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022413 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659345961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659345961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659345963 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659345963 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022425 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022425 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032285 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032285 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032285 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032285 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49875 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49875 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26620.356277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26620.353776 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20685246 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3452781 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 946049 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67233 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.864878 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51.355450 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003150 # number of writebacks -system.cpu.dcache.writebacks::total 17003150 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3153076 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3153076 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130592 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1130592 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25297.893260 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25297.893260 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40651.929858 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40651.929858 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 61375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28089.399499 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28089.399499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28089.396859 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28089.396859 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21254267 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3791320 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 940376 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67438 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.601882 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.219342 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17003360 # number of writebacks +system.cpu.dcache.writebacks::total 17003360 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150878 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3150878 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132695 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1132695 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4283668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4283668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4283668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4283668 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266152 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266152 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737518 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737518 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4283573 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4283573 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4283573 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4283573 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266317 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266317 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737561 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737561 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17003670 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17003670 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17003671 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17003671 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 451887651533 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 451887720533 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17003878 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17003878 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17003879 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17003879 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354302060000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 354302060000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121168074300 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 121168074300 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475470134300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 475470134300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475470209300 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 475470209300 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025788 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025788 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 588 # number of replacements -system.cpu.icache.tags.tagsinuse 444.874436 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656938405 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611674.492551 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24834.865228 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24834.865228 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44261.323967 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44261.323967 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27962.452700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27962.452700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27962.455467 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27962.455467 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states 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445.623702 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.870359 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.870359 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313881106 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313881106 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656938405 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656938405 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656938405 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656938405 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656938405 # number of overall hits -system.cpu.icache.overall_hits::total 656938405 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1611 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1611 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1611 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1611 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1611 # number of overall misses -system.cpu.icache.overall_misses::total 1611 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 103785485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 103785485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 103785485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 103785485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 103785485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 103785485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656940016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656940016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656940016 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656940016 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656940016 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656940016 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.951172 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313930500 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313930500 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 656963104 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656963104 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656963104 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656963104 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656963104 # number of overall hits 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overall miss cycles +system.cpu.icache.overall_miss_latency::total 127367486 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656964712 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656964712 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656964712 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656964712 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656964712 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656964712 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64423.019863 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64423.019863 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64423.019863 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64423.019863 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 16825 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 586 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.945946 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 58.600000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 588 # number of writebacks -system.cpu.icache.writebacks::total 588 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 535 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 535 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 535 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 535 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 535 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75943989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75943989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75943989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75943989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75943989 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75943989 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79208.635572 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 79208.635572 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 79208.635572 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 79208.635572 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21110 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 318 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 109.378238 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 35.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 589 # number of writebacks +system.cpu.icache.writebacks::total 589 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 531 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 531 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 531 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 531 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 531 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 531 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 92273990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 92273990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 92273990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 92273990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 92273990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 92273990 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70579.915428 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70579.915428 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 11612917 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11641367 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19112 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85676.870938 # average ReadReq mshr miss latency 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redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655505 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4647068 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15866.736257 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13267029 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4662976 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.845185 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4657940 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 4647528 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15870.760193 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13267468 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4663442 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.844995 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15646.626307 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 220.109950 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.954994 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968429 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 143 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 463 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4068 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7095 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2886 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1253 # Occupied blocks per task id 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of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 977265 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1026 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1026 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709455 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709455 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3686720 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3687746 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3686720 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1197394 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4885140 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84175133455 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84175133455 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 106500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 106500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98289203000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98289203000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 84580000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 84580000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237438885500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237438885500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 84580000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335728088500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 335812668500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 84580000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335728088500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84175133455 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 419987801955 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356810 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356810 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954461 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189922 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189922 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216837 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356978 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356978 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.952646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189920 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189920 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216863 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287303 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34008488 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003756 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 201663 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 201662 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287278 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70298.609693 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15214.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15214.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100575.793669 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100575.793669 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82436.647173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82436.647173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.448609 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.448609 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91061.767405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85972.521147 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34008905 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003965 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 200821 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200820 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6469733 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12168504 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3012569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1490485 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14267344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6459789 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12178209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3013479 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1493524 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737555 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737555 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266107 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2738 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51010503 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51013241 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176436672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176543040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6137564 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104608640 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23142303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009630 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097659 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266268 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011129 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51013871 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176463552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176570112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6141063 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104579840 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23146008 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009594 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097477 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22919446 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 222856 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22923954 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 222053 0.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23142303 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34007983525 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 16538 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23146008 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34008401540 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 16551 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1611000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1614499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25505500994 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9332231 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4668264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 25505814993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 9333193 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4668760 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3708204 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634499 # Transaction distribution -system.membus.trans_dist::CleanEvict 3012569 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 976948 # Transaction distribution -system.membus.trans_dist::ReadExResp 976948 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3708206 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14017383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14017383 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404457664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404457664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3708223 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634049 # Transaction distribution +system.membus.trans_dist::CleanEvict 3013479 # Transaction distribution +system.membus.trans_dist::UpgradeReq 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 977434 # Transaction distribution +system.membus.trans_dist::ReadExResp 977434 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3708224 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14018850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14018850 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404461184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404461184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4685163 # Request fanout histogram +system.membus.snoop_fanout::samples 4685665 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4685163 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4685665 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4685163 # Request fanout histogram -system.membus.reqLayer0.occupancy 17662405597 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25476549560 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.snoop_fanout::total 4685665 # Request fanout histogram +system.membus.reqLayer0.occupancy 17659262741 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 25448696800 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini index 5e0a983c6..35828777f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout index 9e68a8154..4b089cf00 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout @@ -3,11 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4311 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:43 +gem5 executing on e108600-lin, pid 28042 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -24,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 53344764500 because target called exit() +122 123 124 Exiting @ tick 53437621500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index d3e370d8a..2c8dfca63 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053349 # Number of seconds simulated -sim_ticks 53349450500 # Number of ticks simulated -final_tick 53349450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.053438 # Number of seconds simulated +sim_ticks 53437621500 # Number of ticks simulated +final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 273465 # Simulator instruction rate (inst/s) -host_op_rate 273465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158745564 # Simulator tick rate (ticks/s) -host_mem_usage 258296 # Number of bytes of host memory used -host_seconds 336.07 # Real time elapsed on the host +host_inst_rate 247892 # Simulator instruction rate (inst/s) +host_op_rate 247892 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 144138078 # Simulator tick rate (ticks/s) +host_mem_usage 256712 # Number of bytes of host memory used +host_seconds 370.74 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory system.physmem.bytes_read::total 340608 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 202880 # Nu system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3802851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6384471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3802851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3802851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3802851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2581620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6384471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5322 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53349362500 # Total gap between requests +system.physmem.totGap 53437285500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.743381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.338865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.606559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 303 30.86% 30.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 220 22.40% 53.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 9.57% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 105 10.69% 73.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 62 6.31% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.67% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.95% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 22 2.24% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 111 11.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation -system.physmem.totQLat 40016750 # Total ticks spent queuing -system.physmem.totMemAccLat 139804250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation +system.physmem.totQLat 132267250 # Total ticks spent queuing +system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7519.12 # Average queueing delay per DRAM burst +system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26269.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -217,49 +217,59 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4333 # Number of row buffer hits during reads +system.physmem.readRowHits 4338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10024307.12 # Average gap between requests -system.physmem.pageHitRate 81.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3462480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1889250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 10040827.79 # Average gap between requests +system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1795262310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30431523750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 35736125550 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.920144 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 50622338000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1781260000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 940274500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3923640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2140875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21247200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.626273 # Core power per rank (mW) +system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states +system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states +system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1822659075 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30407483250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35741598600 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.022916 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 50582866250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1781260000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 980601250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450641 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210938 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085190 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320739 # Number of BTB hits +system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ) +system.physmem_1.averagePower 251.716611 # Core power per rank (mW) +system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states +system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11450652 # Number of BP lookups +system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.437516 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176674 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. @@ -282,10 +292,10 @@ system.cpu.dtb.data_hits 26995130 # DT system.cpu.dtb.data_misses 43659 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27038789 # DTB accesses -system.cpu.itb.fetch_hits 22968614 # ITB hits +system.cpu.itb.fetch_hits 22968644 # ITB hits system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968704 # ITB accesses +system.cpu.itb.fetch_accesses 22968734 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106698901 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 106875243 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191321 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.160994 # CPI: cycles per instruction -system.cpu.ipc 0.861331 # IPC: instructions per cycle +system.cpu.cpi 1.162912 # CPI: cycles per instruction +system.cpu.ipc 0.859910 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction @@ -344,76 +354,76 @@ system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103791781 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2907120 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.584590 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572201 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.444195 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584590 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353414 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153439 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153439 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074005 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074005 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498196 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498196 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572201 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572201 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572201 # number of overall hits -system.cpu.dcache.overall_hits::total 26572201 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits +system.cpu.dcache.overall_hits::total 26572187 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2907 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2907 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3403 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3403 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3403 # number of overall misses -system.cpu.dcache.overall_misses::total 3403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37687000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37687000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 223750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 223750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 261437000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 261437000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 261437000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 261437000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses +system.cpu.dcache.overall_misses::total 3415 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575604 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76825.448134 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76825.448134 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1164 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1164 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1172 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1172 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1172 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1172 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses @@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2231 system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36777500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36777500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 140150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 140150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 176927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176927500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 176927500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -454,70 +464,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.701416 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952783 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1642.239495 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22952813 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.954706 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.956601 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.701416 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.802100 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.802100 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.239495 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801875 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953058 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953058 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952783 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952783 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952783 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952783 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952783 # number of overall hits -system.cpu.icache.overall_hits::total 22952783 # number of overall hits +system.cpu.icache.tags.tag_accesses 45953118 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45953118 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22952813 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22952813 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22952813 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22952813 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22952813 # number of overall hits +system.cpu.icache.overall_hits::total 22952813 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 411111000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 411111000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 411111000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 411111000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 411111000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 411111000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968614 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968614 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968614 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968614 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 456439000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 456439000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 456439000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 456439000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 456439000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 456439000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22968644 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22968644 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22968644 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22968644 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22968644 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22968644 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25968.732234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25968.732234 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28831.975238 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,46 +542,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15831 system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 395281000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 395281000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 395281000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 395281000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 395281000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 395281000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 440609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 440609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 440609000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3575.444447 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3574.446973 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.450993 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.993454 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044952 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109114 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.836656 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.610316 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044941 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109083 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits @@ -600,18 +610,18 @@ system.cpu.l2cache.demand_misses::total 5322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 137262000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 137262000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 238604500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 238604500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35483000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 35483000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 238604500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 172745000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 411349500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 238604500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 172745000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 411349500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163078000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 163078000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 283932500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 283932500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 56594000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 56594000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 283932500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 219672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 503604500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 283932500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 219672000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 503604500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) @@ -640,18 +650,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294668 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,18 +680,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120092000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120092000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 206904500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 206904500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31133000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31133000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206904500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151225000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 358129500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206904500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151225000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 358129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 145908000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 145908000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252232500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252232500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 52244000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 52244000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252232500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 198152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 450384500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252232500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 198152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 450384500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses @@ -694,25 +704,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution @@ -752,7 +762,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3605 # Transaction distribution system.membus.trans_dist::ReadExReq 1717 # Transaction distribution system.membus.trans_dist::ReadExResp 1717 # Transaction distribution @@ -773,9 +783,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6421000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28180500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index d82573b75..f4beb67d4 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 1d7fd9550..e5a3bf839 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4313 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28064 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav @@ -26,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 21909208500 because target called exit() +122 123 124 Exiting @ tick 21954917500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 720778178..2ed297d74 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021906 # Number of seconds simulated -sim_ticks 21906070500 # Number of ticks simulated -final_tick 21906070500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021955 # Number of seconds simulated +sim_ticks 21954917500 # Number of ticks simulated +final_tick 21954917500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201237 # Simulator instruction rate (inst/s) -host_op_rate 201237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52367931 # Simulator tick rate (ticks/s) -host_mem_usage 260088 # Number of bytes of host memory used -host_seconds 418.31 # Real time elapsed on the host +host_inst_rate 181107 # Simulator instruction rate (inst/s) +host_op_rate 181107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47234568 # Simulator tick rate (ticks/s) +host_mem_usage 257228 # Number of bytes of host memory used +host_seconds 464.81 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8945831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6325187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15271018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8945831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8945831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8945831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6325187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15271018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5227 # Number of read requests accepted +system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8923012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6311115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15234127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8923012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8923012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8923012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6311115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15234127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5226 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5226 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 470 # Per bank write bursts +system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 292 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21905974500 # Total gap between requests +system.physmem.totGap 21954815500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5227 # Read request sizes (log2) +system.physmem.readPktSize::6 5226 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,105 +187,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.707657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.399691 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 360.883028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 260 30.16% 30.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 179 20.77% 50.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 10.79% 61.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.61% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 30 3.48% 71.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.29% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 31 3.60% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 50 5.80% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 14.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 862 # Bytes accessed per row activation -system.physmem.totQLat 40339750 # Total ticks spent queuing -system.physmem.totMemAccLat 138346000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7717.57 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.932636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.340491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.649518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 261 30.31% 30.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 173 20.09% 50.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 10.80% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.62% 67.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37 4.30% 72.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 30 3.48% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 47 5.46% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 3.83% 84.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 130 15.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 861 # Bytes accessed per row activation +system.physmem.totQLat 128746000 # Total ticks spent queuing +system.physmem.totMemAccLat 226733500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26130000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24635.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26467.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43385.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4357 # Number of row buffer hits during reads +system.physmem.readRowHits 4356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4190926.82 # Average gap between requests -system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19570200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4201074.53 # Average gap between requests +system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3034500 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1593900 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18099900 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 905463810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12347522250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14707973130 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.505534 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20538678250 # Time in different power states -system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 632936750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3333960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1819125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20779200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 118625520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 48811380 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6176640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 312556080 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 154176960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 5001436845 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 5664547785 # Total energy per rank (pJ) +system.physmem_0.averagePower 258.008156 # Core power per rank (mW) +system.physmem_0.totalIdleTime 21831003750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 11536500 # Time in different power states +system.physmem_0.memoryStateTime::REF 50426000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 20744771750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 401491250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 61308000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 685384000 # Time in different power states +system.physmem_1.actEnergy 3177300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1673595 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19213740 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 902236185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12350353500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14709101250 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.557040 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20543762750 # Time in different power states -system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 628284250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16102243 # Number of BP lookups -system.cpu.branchPred.condPredicted 11688063 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 931000 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8962915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7507921 # Number of BTB hits +system.physmem_1.refreshEnergy 106332720.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46621440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 5256960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 301076850 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 131936160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 5018107080 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 5633395845 # Total energy per rank (pJ) +system.physmem_1.averagePower 256.589251 # Core power per rank (mW) +system.physmem_1.totalIdleTime 21838957750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 9258500 # Time in different power states +system.physmem_1.memoryStateTime::REF 45178000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 20835144000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 343577000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 61468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 660291500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16102182 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688137 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 930988 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8963257 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7508303 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.766509 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1594308 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.767575 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594537 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 29379 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25730 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3649 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 29363 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3639 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24059471 # DTB read hits -system.cpu.dtb.read_misses 206747 # DTB read misses -system.cpu.dtb.read_acv 6 # DTB read access violations -system.cpu.dtb.read_accesses 24266218 # DTB read accesses -system.cpu.dtb.write_hits 7167964 # DTB write hits -system.cpu.dtb.write_misses 1190 # DTB write misses +system.cpu.dtb.read_hits 24064359 # DTB read hits +system.cpu.dtb.read_misses 206311 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 24270670 # DTB read accesses +system.cpu.dtb.write_hits 7168837 # DTB write hits +system.cpu.dtb.write_misses 1192 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7169154 # DTB write accesses -system.cpu.dtb.data_hits 31227435 # DTB hits -system.cpu.dtb.data_misses 207937 # DTB misses -system.cpu.dtb.data_acv 6 # DTB access violations -system.cpu.dtb.data_accesses 31435372 # DTB accesses -system.cpu.itb.fetch_hits 15930202 # ITB hits +system.cpu.dtb.write_accesses 7170029 # DTB write accesses +system.cpu.dtb.data_hits 31233196 # DTB hits +system.cpu.dtb.data_misses 207503 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 31440699 # DTB accesses +system.cpu.itb.fetch_hits 15932695 # ITB hits system.cpu.itb.fetch_misses 79 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15930281 # ITB accesses +system.cpu.itb.fetch_accesses 15932774 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,140 +309,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43812142 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 43909836 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16640800 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137955116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16102243 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9127959 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25951378 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1939862 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2284 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15930202 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367997 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43564561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.166682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16643979 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137979397 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102182 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9128564 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26000321 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939876 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2307 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15932695 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367713 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43616730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.163451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19388904 44.51% 44.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2617971 6.01% 50.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1329653 3.05% 53.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1933242 4.44% 58.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3001866 6.89% 64.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1292154 2.97% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1355153 3.11% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 885983 2.03% 73.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11759635 26.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19436456 44.56% 44.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2618537 6.00% 50.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1330059 3.05% 53.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1934096 4.43% 58.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001834 6.88% 64.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292274 2.96% 67.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355703 3.11% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 886638 2.03% 73.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11761133 26.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43564561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367529 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.148787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12866207 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8201064 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19435677 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2103016 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 958597 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2653560 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11864 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132121785 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49799 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 958597 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13983011 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4637206 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10599 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20305280 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3669868 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128752916 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70736 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2012785 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1367413 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 56554 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94580122 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167299448 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159747069 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7552378 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43616730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.366710 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.142335 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12867029 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8250930 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19434015 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2106147 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958609 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2654207 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11848 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132149793 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49699 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958609 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13986200 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4658485 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10631 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305693 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3697112 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128776944 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70815 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2027533 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1361651 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 79521 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94599397 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167333600 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159779432 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7554167 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26152761 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 949 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8254781 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26901517 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8704631 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3463893 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1634991 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111837286 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1924 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99746434 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118591 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27659500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21091403 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1535 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43564561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.289623 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099110 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26172036 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 950 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8272242 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26904484 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704450 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3461355 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1614052 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111855473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1918 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99762246 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119439 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27677681 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21095832 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1529 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43616730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.287247 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099564 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11223672 25.76% 25.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7655343 17.57% 43.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7467756 17.14% 60.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5704970 13.10% 73.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4467403 10.25% 83.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2981246 6.84% 90.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2039535 4.68% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1169471 2.68% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 855165 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11270720 25.84% 25.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7659760 17.56% 43.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7470187 17.13% 60.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5700495 13.07% 73.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4466514 10.24% 83.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2981046 6.83% 90.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2041941 4.68% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1170841 2.68% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855226 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43564561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43616730 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 481664 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 484010 20.16% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 522 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34768 1.46% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12121 0.51% 22.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1011551 42.34% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 688710 28.83% 93.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159620 6.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1012503 42.17% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 694860 28.94% 93.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 162157 6.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60652801 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 489881 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60662676 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2847832 2.86% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115342 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2442782 2.45% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314177 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766025 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847523 2.85% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2443321 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314198 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued @@ -454,82 +464,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24850091 24.91% 92.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7267177 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24854622 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7268455 7.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99746434 # Type of FU issued -system.cpu.iq.rate 2.276685 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2388956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023950 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229877287 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129889935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89741335 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15687689 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9649325 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7189295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93754597 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8380786 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1921314 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99762246 # Type of FU issued +system.cpu.iq.rate 2.271979 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2401186 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024069 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229973015 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129921960 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89757276 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15688832 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9653681 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189481 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93781523 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8381902 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1923320 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6905319 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11494 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40918 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2203528 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6908286 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11342 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203347 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42864 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1503 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 958597 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3610605 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461685 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122758059 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241249 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26901517 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8704631 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1924 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38682 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 417297 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40918 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 531922 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502439 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98421413 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24266766 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1325021 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 958609 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3613912 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 479107 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122779790 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241415 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26904484 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704450 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1918 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38391 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 434865 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502384 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034333 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98436741 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24271214 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325505 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10918849 # number of nop insts executed -system.cpu.iew.exec_refs 31435958 # number of memory reference insts executed -system.cpu.iew.exec_branches 12470734 # Number of branches executed -system.cpu.iew.exec_stores 7169192 # Number of stores executed -system.cpu.iew.exec_rate 2.246441 # Inst execution rate -system.cpu.iew.wb_sent 97629714 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96930630 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66965531 # num instructions producing a value -system.cpu.iew.wb_consumers 94946242 # num instructions consuming a value -system.cpu.iew.wb_rate 2.212415 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705299 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30856710 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10922399 # number of nop insts executed +system.cpu.iew.exec_refs 31441282 # number of memory reference insts executed +system.cpu.iew.exec_branches 12471732 # Number of branches executed +system.cpu.iew.exec_stores 7170068 # Number of stores executed +system.cpu.iew.exec_rate 2.241792 # Inst execution rate +system.cpu.iew.wb_sent 97645487 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96946757 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66976137 # num instructions producing a value +system.cpu.iew.wb_consumers 94960144 # num instructions consuming a value +system.cpu.iew.wb_rate 2.207860 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705308 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30878503 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 919666 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39073158 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.352076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.920100 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 919659 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39122931 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.349084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.919383 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14677251 37.56% 37.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8528323 21.83% 59.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880033 9.93% 69.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1914323 4.90% 74.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1374739 3.52% 77.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1034073 2.65% 80.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692942 1.77% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727068 1.86% 84.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6244406 15.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14724541 37.64% 37.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8532800 21.81% 59.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3880104 9.92% 69.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1909784 4.88% 74.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1376640 3.52% 77.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1034511 2.64% 80.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692868 1.77% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 729092 1.86% 84.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6242591 15.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39073158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39122931 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -575,118 +585,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6244406 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155587477 # The number of ROB reads -system.cpu.rob.rob_writes 250066312 # The number of ROB writes -system.cpu.timesIdled 4758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 247581 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6242591 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155660858 # The number of ROB reads +system.cpu.rob.rob_writes 250112359 # The number of ROB writes +system.cpu.timesIdled 4774 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 293106 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520460 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520460 # CPI: Total CPI of All Threads -system.cpu.ipc 1.921379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.921379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 132984940 # number of integer regfile reads -system.cpu.int_regfile_writes 72890464 # number of integer regfile writes -system.cpu.fp_regfile_reads 6263699 # number of floating regfile reads -system.cpu.fp_regfile_writes 6177982 # number of floating regfile writes -system.cpu.misc_regfile_reads 719169 # number of misc regfile reads +system.cpu.cpi 0.521620 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.521620 # CPI: Total CPI of All Threads +system.cpu.ipc 1.917104 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.917104 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133010551 # number of integer regfile reads +system.cpu.int_regfile_writes 72904644 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263409 # number of floating regfile reads +system.cpu.fp_regfile_writes 6178123 # number of floating regfile writes +system.cpu.misc_regfile_reads 719113 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.358075 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28585648 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.034872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28588531 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12733.028062 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12734.312249 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.358075 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355800 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355800 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.034872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355721 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355721 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57192649 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57192649 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22092545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22092545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492630 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492630 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 473 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 473 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28585175 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28585175 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28585175 # number of overall hits -system.cpu.dcache.overall_hits::total 28585175 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1080 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1080 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8473 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8473 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 57198427 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57198427 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22095438 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22095438 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492623 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492623 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28588061 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28588061 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28588061 # number of overall hits +system.cpu.dcache.overall_hits::total 28588061 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1079 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1079 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8480 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8480 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9553 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9553 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9553 # number of overall misses -system.cpu.dcache.overall_misses::total 9553 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 72549500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 72549500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 550211742 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 550211742 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 86000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 86000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 622761242 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 622761242 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 622761242 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 622761242 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22093625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22093625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9559 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9559 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9559 # number of overall misses +system.cpu.dcache.overall_misses::total 9559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87318000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87318000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 649645257 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 649645257 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 106000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 106000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 736963257 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 736963257 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 736963257 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 736963257 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22096517 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22096517 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28594728 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28594728 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28594728 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28594728 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28597620 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28597620 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28597620 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28597620 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002110 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002110 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67175.462963 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67175.462963 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64937.063850 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64937.063850 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 86000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 86000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65190.122684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65190.122684 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33457 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 396 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.487374 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80924.930491 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 80924.930491 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76609.110495 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76609.110495 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 106000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 106000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77096.271263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77096.271263 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 43101 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 174 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 123.145714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 565 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 565 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6744 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7309 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7309 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7309 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7309 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6751 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6751 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7315 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7315 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7315 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7315 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses @@ -697,232 +707,232 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2244 system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136978995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 136978995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 85000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 85000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177801495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 177801495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177801495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 177801495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47711000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47711000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177283495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 177283495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224994495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 224994495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224994495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 224994495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002110 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79266.990291 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79266.990291 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79224.404280 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79224.404280 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 85000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 85000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 9515 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.893985 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15915792 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11453 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1389.661399 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92642.718447 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92642.718447 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102535.277617 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102535.277617 # average WriteReq mshr miss latency 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valid blocks. +system.cpu.icache.tags.sampled_refs 11449 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1390.362652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.893985 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781687 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781687 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.395362 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781443 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781443 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 943 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31871855 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31871855 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 15915792 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15915792 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15915792 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15915792 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15915792 # number of overall hits -system.cpu.icache.overall_hits::total 15915792 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14409 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14409 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14409 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14409 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14409 # number of overall misses -system.cpu.icache.overall_misses::total 14409 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 447639000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 447639000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 447639000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 447639000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 447639000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 447639000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15930201 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15930201 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15930201 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15930201 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15930201 # 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31066.625026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31066.625026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31066.625026 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 446 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 31876835 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31876835 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 15918262 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15918262 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15918262 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15918262 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15918262 # number of overall hits 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of overall miss cycles +system.cpu.icache.overall_miss_latency::total 508617000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15932693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15932693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15932693 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15932693 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15932693 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15932693 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000906 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000906 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000906 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000906 # 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miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 337628000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337628000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 337628000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 9511 # number of writebacks +system.cpu.icache.writebacks::total 9511 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2981 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2981 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2981 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2981 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2981 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2981 # number of overall MSHR hits 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94510.237275 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -931,122 +941,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3062 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3061 # number of 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-system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.381599 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92333.529066 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92333.529066 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79244.691277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79244.691277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90559.523810 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90559.523810 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 23364 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9669 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 11965 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9511 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11450 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32422 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32410 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 37070 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 37058 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341440 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1492544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1492032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 13699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13695 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13699 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13695 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13699 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21309000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13695 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21301000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17173500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5227 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5226 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3524 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3523 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3524 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3523 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5227 # Request fanout histogram +system.membus.snoop_fanout::samples 5226 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5227 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5226 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5227 # Request fanout histogram -system.membus.reqLayer0.occupancy 6278000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5226 # Request fanout histogram +system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27461750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27424000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini index cdcb110c1..701cef29f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout index 90ea58e8e..862c8292b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:40:38 -gem5 executing on e108600-lin, pid 23114 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:49:48 +gem5 executing on e108600-lin, pid 17449 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/minor-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav @@ -26,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 132485848500 because target called exit() +122 123 124 Exiting @ tick 132538562500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 9382954d5..26e7200e9 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132488 # Number of seconds simulated -sim_ticks 132487590500 # Number of ticks simulated -final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132539 # Number of seconds simulated +sim_ticks 132538562500 # Number of ticks simulated +final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200266 # Simulator instruction rate (inst/s) -host_op_rate 211113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153975874 # Simulator tick rate (ticks/s) -host_mem_usage 275560 # Number of bytes of host memory used -host_seconds 860.44 # Real time elapsed on the host +host_inst_rate 171463 # Simulator instruction rate (inst/s) +host_op_rate 180750 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131881088 # Simulator tick rate (ticks/s) +host_mem_usage 273644 # Number of bytes of host memory used +host_seconds 1004.99 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1043017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 824756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1867773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 824756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1867773 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132487495500 # Total gap between requests +system.physmem.totGap 132538461500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation -system.physmem.totQLat 28381250 # Total ticks spent queuing -system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.439776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.287318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 274 29.53% 29.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 366 39.44% 68.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89 9.59% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.14% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24 2.59% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 19 2.05% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.94% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63 6.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation +system.physmem.totQLat 84421250 # Total ticks spent queuing +system.physmem.totMemAccLat 156946250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst +system.physmem.avgQLat 21825.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 40575.56 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -217,56 +217,66 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2936 # Number of row buffer hits during reads +system.physmem.readRowHits 2935 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34252196.35 # Average gap between requests -system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34265372.67 # Average gap between requests +system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2977380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1582515 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.825360 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 159806400.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56564520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6779040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 507399750 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 193240800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 31407910590 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 32351114145 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.088313 # Core power per rank (mW) +system.physmem_0.totalIdleTime 132395468250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 11004000 # Time in different power states +system.physmem_0.memoryStateTime::REF 67828000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 130780838250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 503202000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 62983500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1112706750 # Time in different power states +system.physmem_1.actEnergy 3684240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1939245 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.826698 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693795 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 142596480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 50045430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 5323200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 514216380 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 148467840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 31429438665 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 32308536150 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.767063 # Core power per rank (mW) +system.physmem_1.totalIdleTime 132414854750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 7934000 # Time in different power states +system.physmem_1.memoryStateTime::REF 60464000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 130900584250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 386668500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 55249000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1127662750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693791 # Number of BP lookups +system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264975181 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 265077125 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.537712 # CPI: cycles per instruction -system.cpu.ipc 0.650317 # IPC: instructions per cycle +system.cpu.cpi 1.538304 # CPI: cycles per instruction +system.cpu.ipc 0.650067 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -432,62 +442,62 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256741537 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8335588 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.587934 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40755397 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22504.360574 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.587934 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336569 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336569 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362633 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362633 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits -system.cpu.dcache.overall_hits::total 40710587 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40710121 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40710121 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40710583 # number of overall hits +system.cpu.dcache.overall_hits::total 40710583 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1651 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1654 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses -system.cpu.dcache.overall_misses::total 2403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2406 # number of overall misses +system.cpu.dcache.overall_misses::total 2406 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64864500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64864500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 147460000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 147460000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 212324500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 212324500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 212324500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 212324500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +506,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses @@ -510,14 +520,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 88284.615385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 88247.921862 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,12 +538,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 552 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 552 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 592 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 592 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 592 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 592 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 555 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 555 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 595 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 595 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 595 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 595 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses @@ -544,16 +554,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61185500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 61185500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100181500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 100181500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161367000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161367000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161444000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161444000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -564,72 +574,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1424.889067 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70941363 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 15213.674244 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.889067 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695747 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695747 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 491 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses -system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70941364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70941364 # number of overall hits -system.cpu.icache.overall_hits::total 70941364 # number of overall hits +system.cpu.icache.tags.tag_accesses 141896717 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141896717 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 70941363 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70941363 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70941363 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70941363 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70941363 # number of overall hits +system.cpu.icache.overall_hits::total 70941363 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 70946028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 70946028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 70946028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 236552500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 236552500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 236552500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 236552500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 236552500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 236552500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70946027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70946027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70946027 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70946027 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70946027 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70946027 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50718.803602 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50718.803602 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50718.803602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50718.803602 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,46 +654,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4664 system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231889500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 231889500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231889500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 231889500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231889500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 231889500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.018010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49719.018010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2835.336724 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.638236 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.698487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits @@ -712,18 +722,18 @@ system.cpu.l2cache.demand_misses::total 3885 # nu system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98447500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 98447500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198239500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 198239500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 59270000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 59270000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198239500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157717500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 355957000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198239500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157717500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 355957000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) @@ -752,18 +762,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.600000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,18 +802,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87537500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87537500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 51432500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 51432500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176566000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138970000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 315536000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176566000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138970000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 315536000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses @@ -816,25 +826,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution @@ -874,7 +884,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -895,9 +905,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20568250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 86715fd27..3c414751d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 6247d8422..8c06d056d 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -3,11 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:31:02 -gem5 executing on e108600-lin, pid 12562 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:01 +gem5 executing on e108600-lin, pid 17342 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 84937723500 because target called exit() +122 123 124 Exiting @ tick 86053034000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 834ad990c..04ea23c2f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085052 # Number of seconds simulated -sim_ticks 85051506000 # Number of ticks simulated -final_tick 85051506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.086053 # Number of seconds simulated +sim_ticks 86053034000 # Number of ticks simulated +final_tick 86053034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137318 # Simulator instruction rate (inst/s) -host_op_rate 144756 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67782320 # Simulator tick rate (ticks/s) -host_mem_usage 272616 # Number of bytes of host memory used -host_seconds 1254.77 # Real time elapsed on the host +host_inst_rate 114393 # Simulator instruction rate (inst/s) +host_op_rate 120589 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57131119 # Simulator tick rate (ticks/s) +host_mem_usage 270696 # Number of bytes of host memory used +host_seconds 1506.24 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 651584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 192256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory -system.physmem.bytes_read::total 914880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 651584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 651584 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3004 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14295 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7661052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2260466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 835259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10756776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7661052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7661052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7661052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2260466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 835259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10756776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14295 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 652224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 193472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 70848 # Number of bytes read from this memory +system.physmem.bytes_read::total 916544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 652224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 652224 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10191 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1107 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14321 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7579326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2248288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 823306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10650920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7579326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7579326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7579326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2248288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 823306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10650920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14321 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14295 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14321 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 914880 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916544 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 914880 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916544 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1374 # Per bank write bursts -system.physmem.perBankRdBursts::1 495 # Per bank write bursts -system.physmem.perBankRdBursts::2 5094 # Per bank write bursts -system.physmem.perBankRdBursts::3 807 # Per bank write bursts -system.physmem.perBankRdBursts::4 2274 # Per bank write bursts +system.physmem.perBankRdBursts::0 1378 # Per bank write bursts +system.physmem.perBankRdBursts::1 501 # Per bank write bursts +system.physmem.perBankRdBursts::2 5089 # Per bank write bursts +system.physmem.perBankRdBursts::3 804 # Per bank write bursts +system.physmem.perBankRdBursts::4 2285 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts system.physmem.perBankRdBursts::6 384 # Per bank write bursts -system.physmem.perBankRdBursts::7 621 # Per bank write bursts +system.physmem.perBankRdBursts::7 628 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts -system.physmem.perBankRdBursts::9 230 # Per bank write bursts +system.physmem.perBankRdBursts::9 231 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts system.physmem.perBankRdBursts::11 348 # Per bank write bursts -system.physmem.perBankRdBursts::12 319 # Per bank write bursts +system.physmem.perBankRdBursts::12 321 # Per bank write bursts system.physmem.perBankRdBursts::13 267 # Per bank write bursts -system.physmem.perBankRdBursts::14 239 # Per bank write bursts -system.physmem.perBankRdBursts::15 795 # Per bank write bursts +system.physmem.perBankRdBursts::14 240 # Per bank write bursts +system.physmem.perBankRdBursts::15 797 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85051447500 # Total gap between requests +system.physmem.totGap 86052975500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14295 # Read request sizes (log2) +system.physmem.readPktSize::6 14321 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,18 +95,18 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -191,86 +191,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8758 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.242978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 83.732821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 121.093987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6415 73.25% 73.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1879 21.45% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 191 2.18% 96.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 97 1.11% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 0.40% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 31 0.35% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21 0.24% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 0.19% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8758 # Bytes accessed per row activation -system.physmem.totQLat 205669486 # Total ticks spent queuing -system.physmem.totMemAccLat 473700736 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14387.51 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8480 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 108.022642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.441459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 123.287712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5899 69.56% 69.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2101 24.78% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 209 2.46% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 1.05% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41 0.48% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 0.42% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15 0.18% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13 0.15% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 77 0.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8480 # Bytes accessed per row activation +system.physmem.totQLat 1499260235 # Total ticks spent queuing +system.physmem.totMemAccLat 1767778985 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 104689.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33137.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 10.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 123439.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 10.76 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5530 # Number of row buffer hits during reads +system.physmem.readRowHits 5837 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 38.68 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 5949734.00 # Average gap between requests -system.physmem.pageHitRate 38.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 56571480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 30867375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 89442600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6008866.39 # Average gap between requests +system.physmem.pageHitRate 40.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 82060020 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 17335593540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 35823020250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 58890496125 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.426384 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 59484367239 # Time in different power states -system.physmem_0.memoryStateTime::REF 2839980000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22725351261 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9616320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5247000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21801000 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 5180800560.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1120628550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 275264640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12259963560 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8345872320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9276913815 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36622770765 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.583720 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82871785017 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 531109000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2203210000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34253599252 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21734056085 # Time in different power states +system.physmem_0.memoryStateTime::ACT 445220983 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26885838680 # Time in different power states +system.physmem_1.actEnergy 9017820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4789290 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20191920 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4216606920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 47330903250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 57139175370 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.834595 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 78723898183 # Time in different power states -system.physmem_1.memoryStateTime::REF 2839980000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3485604317 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85633597 # Number of BP lookups -system.cpu.branchPred.condPredicted 68181299 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5935035 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39958046 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38197568 # Number of BTB hits +system.physmem_1.refreshEnergy 882623040.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198112620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 50847360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1971627720 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1393669440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18810725700 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23341907430 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.250252 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85485463257 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 101360000 # Time in different power states +system.physmem_1.memoryStateTime::REF 375610000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77532398500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3629358146 # Time in different power states +system.physmem_1.memoryStateTime::ACT 90573993 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4323733361 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85625838 # Number of BP lookups +system.cpu.branchPred.condPredicted 68176243 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935432 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39943176 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38184524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.594184 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683467 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81914 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681978 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 654112 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 27866 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40296 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.597115 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683485 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81916 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681521 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653387 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 28134 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40344 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,131 +401,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 170103013 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 172106069 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5682904 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347166765 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85633597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42535147 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 157608501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11884039 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5685351 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347171735 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85625838 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42521396 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158200265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884759 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 3989 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78333693 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18018 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169239484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.146393 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.050401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 4307 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78326471 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18089 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169836333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.138878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.056220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17572638 10.38% 10.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30072408 17.77% 28.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31601234 18.67% 46.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89993204 53.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18169241 10.70% 10.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30071574 17.71% 28.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31598899 18.61% 47.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89996619 52.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169239484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.503422 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.040921 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17519961 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17356982 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121861075 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6734206 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5767260 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11064637 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189821 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304987544 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27243895 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5767260 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37487022 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8574296 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 598391 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108353196 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8459319 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277412346 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13179472 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3059617 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 843440 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2298708 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 38369 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27077 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481431446 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187749796 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296450503 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005240 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169836333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.497518 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.017196 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17522714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17948295 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121866676 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6730979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767669 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064280 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189793 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304996623 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27241409 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767669 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37489750 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8834769 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 601523 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108355832 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8786790 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277419061 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13180458 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3061814 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 846087 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2626546 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 39334 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27085 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481448286 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187772528 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296460965 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3003847 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188454517 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23636 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23644 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13356506 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33916395 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14406588 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2541453 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1809916 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263792468 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45987 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214404594 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5189732 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82202501 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216956580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 771 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169239484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.266871 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.018138 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188471357 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23624 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13352846 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33915531 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14406995 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2538352 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1801972 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263797881 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45980 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214410891 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5187410 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82207907 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216953193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 764 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169836333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.262456 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.019138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52525006 31.04% 31.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35947009 21.24% 52.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65510390 38.71% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13639375 8.06% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570056 0.93% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47432 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 216 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53122752 31.28% 31.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35940807 21.16% 52.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65514665 38.58% 91.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13639448 8.03% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571104 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47348 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 209 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169239484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169836333 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35663808 66.17% 66.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153282 0.28% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35657368 66.16% 66.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153250 0.28% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34308 0.06% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14056089 26.08% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3953676 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35732 0.07% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 954 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34277 0.06% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14055726 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3956441 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166984371 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919276 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166991462 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919191 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued @@ -534,91 +544,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33016 0.02% 78.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460481 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206631 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165181 0.08% 78.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245709 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460330 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206622 0.10% 78.87% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31870339 14.86% 93.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13371616 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31869240 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13372180 6.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214404594 # Type of FU issued -system.cpu.iq.rate 1.260440 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53899365 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251391 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653186184 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344036614 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204245973 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3951585 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011286 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806392 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266171590 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2132369 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1599233 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214410891 # Type of FU issued +system.cpu.iq.rate 1.245807 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53895257 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251364 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653788467 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344049655 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204252570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952315 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2009022 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806352 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266172688 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133460 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1598637 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6020251 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7425 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7087 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1761954 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6019387 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7380 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7051 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25499 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25560 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 770 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5767260 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5621824 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 63176 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263858489 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5767669 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5624657 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 173600 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263863986 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33916395 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14406588 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23579 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3874 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56135 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7087 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3147809 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246868 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6394677 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207120469 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30635063 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7284125 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33915531 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14406995 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23572 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3856 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 166551 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7051 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3148917 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246700 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6395617 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207126816 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30634090 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7284075 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20034 # number of nop insts executed -system.cpu.iew.exec_refs 43773548 # number of memory reference insts executed -system.cpu.iew.exec_branches 44851099 # Number of branches executed -system.cpu.iew.exec_stores 13138485 # Number of stores executed -system.cpu.iew.exec_rate 1.217618 # Inst execution rate -system.cpu.iew.wb_sent 206362307 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206052365 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129396792 # num instructions producing a value -system.cpu.iew.wb_consumers 221653711 # num instructions consuming a value -system.cpu.iew.wb_rate 1.211339 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583779 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68665439 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20125 # number of nop insts executed +system.cpu.iew.exec_refs 43772682 # number of memory reference insts executed +system.cpu.iew.exec_branches 44853086 # Number of branches executed +system.cpu.iew.exec_stores 13138592 # Number of stores executed +system.cpu.iew.exec_rate 1.203484 # Inst execution rate +system.cpu.iew.wb_sent 206368979 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206058922 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129395738 # num instructions producing a value +system.cpu.iew.wb_consumers 221650226 # num instructions consuming a value +system.cpu.iew.wb_rate 1.197279 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583783 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68671574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5760276 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 157944348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.150091 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.652266 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5760722 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158539716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.145772 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.650496 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73354007 46.44% 46.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41142542 26.05% 72.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22532573 14.27% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9515365 6.02% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3551587 2.25% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2142504 1.36% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1329210 0.84% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1010049 0.64% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3366511 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73944910 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41143540 25.95% 72.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22534900 14.21% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9516225 6.00% 92.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3553894 2.24% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2144247 1.35% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1327660 0.84% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1009164 0.64% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3365176 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 157944348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158539716 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,83 +674,83 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3366511 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 404888417 # The number of ROB reads -system.cpu.rob.rob_writes 511940612 # The number of ROB writes -system.cpu.timesIdled 9843 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 863529 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3365176 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405491255 # The number of ROB reads +system.cpu.rob.rob_writes 511954468 # The number of ROB writes +system.cpu.timesIdled 10012 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2269736 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.987232 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.987232 # CPI: Total CPI of All Threads -system.cpu.ipc 1.012933 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.012933 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218721236 # number of integer regfile reads -system.cpu.int_regfile_writes 114166498 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904044 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441835 # number of floating regfile writes -system.cpu.cc_regfile_reads 708181937 # number of cc regfile reads -system.cpu.cc_regfile_writes 229500026 # number of cc regfile writes -system.cpu.misc_regfile_reads 57441519 # number of misc regfile reads +system.cpu.cpi 0.998857 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.998857 # CPI: Total CPI of All Threads +system.cpu.ipc 1.001144 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.001144 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218726711 # number of integer regfile reads +system.cpu.int_regfile_writes 114168819 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904003 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441695 # number of floating regfile writes +system.cpu.cc_regfile_reads 708199076 # number of cc regfile reads +system.cpu.cc_regfile_writes 229511616 # number of cc regfile writes +system.cpu.misc_regfile_reads 57440558 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72593 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.410345 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41032184 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73105 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.277396 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 509673500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.410345 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998848 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998848 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72579 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.404028 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41032024 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73091 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.382715 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 516933500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.404028 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998836 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82362697 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82362697 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28645946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28645946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82362375 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82362375 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28645802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28645802 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341304 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341304 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40987266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40987266 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40987630 # number of overall hits -system.cpu.dcache.overall_hits::total 40987630 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89269 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89269 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40987106 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40987106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40987470 # number of overall hits +system.cpu.dcache.overall_hits::total 40987470 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89259 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89259 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22983 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22983 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112236 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112236 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112352 # number of overall misses -system.cpu.dcache.overall_misses::total 112352 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1192862000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1192862000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 244207999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 244207999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2309000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1437069999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1437069999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1437069999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1437069999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28735215 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28735215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112242 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112242 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112358 # number of overall misses +system.cpu.dcache.overall_misses::total 112358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1986737500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1986737500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 247540999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 247540999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2234278499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2234278499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2234278499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2234278499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28735061 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28735061 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) @@ -749,14 +759,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41099502 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41099502 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41099982 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41099982 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003107 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003107 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41099348 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41099348 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41099828 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41099828 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses @@ -765,54 +775,54 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8880.769231 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8880.769231 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12804.002272 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12790.782532 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10626 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22258.119629 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22258.119629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10770.613018 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10770.613018 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19905.904198 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19905.904198 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19885.353059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19885.353059 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11288 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 868 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.241935 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72593 # number of writebacks -system.cpu.dcache.writebacks::total 72593 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24834 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24834 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14410 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14410 # number of WriteReq MSHR hits +system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 13.049711 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72579 # number of writebacks +system.cpu.dcache.writebacks::total 72579 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24837 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24837 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14427 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14427 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39244 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39244 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39244 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39244 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64435 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64435 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8557 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8557 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 39264 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39264 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39264 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39264 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64422 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64422 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8556 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8556 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72992 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72992 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73105 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73105 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 724757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 724757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85765499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85765499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 963000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 963000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 810522499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 810522499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 811485499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 811485499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 72978 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72978 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73091 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73091 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062843500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062843500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87501999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 87501999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150345499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1150345499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151314499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1151314499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses @@ -821,373 +831,374 @@ system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001779 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11247.877706 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11247.877706 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10022.846675 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10022.846675 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8522.123894 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8522.123894 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11104.264837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11104.264837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11100.273565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11100.273565 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53637 # number of replacements -system.cpu.icache.tags.tagsinuse 510.592571 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78276090 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54149 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1445.568524 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84288957500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.592571 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997251 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997251 # Average percentage of cache occupancy +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16498.145044 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16498.145044 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10226.975105 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10226.975105 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15762.907986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15762.907986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15751.795693 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15751.795693 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53612 # number of replacements +system.cpu.icache.tags.tagsinuse 510.587809 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78268729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54124 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1446.100233 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85282294500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.587809 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997242 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997242 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156721475 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156721475 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78276090 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78276090 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78276090 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78276090 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78276090 # number of overall hits -system.cpu.icache.overall_hits::total 78276090 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57573 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57573 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57573 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57573 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57573 # number of overall misses -system.cpu.icache.overall_misses::total 57573 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1245757924 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1245757924 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1245757924 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1245757924 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1245757924 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1245757924 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78333663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78333663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78333663 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78333663 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78333663 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78333663 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21637.884494 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21637.884494 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21637.884494 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21637.884494 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 76503 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 31 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3201 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 156706996 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156706996 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 78268729 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78268729 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78268729 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78268729 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78268729 # number of overall hits +system.cpu.icache.overall_hits::total 78268729 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57707 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57707 # number of ReadReq misses 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188286 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043200 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043200 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188286 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041359 # mshr miss rate for demand accesses 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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253485 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126250 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 904 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 903 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120040 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47408.177443 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78403.361345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78403.361345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161478.853891 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161478.853891 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194328.366248 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194328.366248 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166905.970940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 150809.647109 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253407 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126211 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10475 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 949 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54150 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64481 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218803 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380739 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6898304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9324672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16222976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2352 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64697 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64468 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380622 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6895104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9322880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16217984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2394 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129607 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.087812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283049 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129610 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088311 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283775 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118227 91.22% 91.22% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11379 8.78% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118165 91.17% 91.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11444 8.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129607 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129610 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252894500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81228989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81192487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109661492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109641490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14295 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14321 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10482 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14059 # Transaction distribution -system.membus.trans_dist::ReadExReq 236 # Transaction distribution -system.membus.trans_dist::ReadExResp 236 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14059 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28590 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28590 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 914880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 914880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14082 # Transaction distribution +system.membus.trans_dist::ReadExReq 238 # Transaction distribution +system.membus.trans_dist::ReadExResp 238 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14083 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28641 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28641 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14295 # Request fanout histogram +system.membus.snoop_fanout::samples 14321 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14295 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14321 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14295 # Request fanout histogram -system.membus.reqLayer0.occupancy 18052130 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14321 # Request fanout histogram +system.membus.reqLayer0.occupancy 18093154 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77159307 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77218560 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 4ca9409ac..8d26638e4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -179,7 +179,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,6 +756,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -767,7 +768,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -775,29 +776,36 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -817,6 +825,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -848,9 +857,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 6416a69a9..99d577e0b 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18548 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:09:02 +gem5 executing on e108600-lin, pid 17639 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav @@ -20,7 +20,6 @@ Authors: Carl Sechen, Bill Swartz info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. - 1 2 3 4 5 6 7 8 9 10 11 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -9804,7 +9803,8 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. - 12 13 14 15 +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 @@ -9812,4 +9812,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 103324153500 because target called exit() +122 123 124 Exiting @ tick 103189362000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index c2d15923a..f0c12dca0 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103278 # Number of seconds simulated -sim_ticks 103278421500 # Number of ticks simulated -final_tick 103278421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.103189 # Number of seconds simulated +sim_ticks 103189362000 # Number of ticks simulated +final_tick 103189362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68420 # Simulator instruction rate (inst/s) -host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53503682 # Simulator tick rate (ticks/s) -host_mem_usage 309068 # Number of bytes of host memory used -host_seconds 1930.31 # Real time elapsed on the host +host_inst_rate 73255 # Simulator instruction rate (inst/s) +host_op_rate 122783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57235650 # Simulator tick rate (ticks/s) +host_mem_usage 306480 # Number of bytes of host memory used +host_seconds 1802.89 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory -system.physmem.bytes_read::total 362688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5667 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2248214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1263536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3511750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2248214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2248214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2248214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1263536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3511750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5668 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 232704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130112 # Number of bytes read from this memory +system.physmem.bytes_read::total 362816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232704 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2033 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5669 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2255116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1260905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3516021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2255116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2255116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2255116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1260905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3516021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5669 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5668 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5669 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 362752 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 362816 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 362752 # Total read bytes from the system interface side +system.physmem.bytesReadSys 362816 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 314 # Per bank write bursts -system.physmem.perBankRdBursts::1 385 # Per bank write bursts -system.physmem.perBankRdBursts::2 471 # Per bank write bursts -system.physmem.perBankRdBursts::3 359 # Per bank write bursts -system.physmem.perBankRdBursts::4 360 # Per bank write bursts -system.physmem.perBankRdBursts::5 334 # Per bank write bursts -system.physmem.perBankRdBursts::6 420 # Per bank write bursts -system.physmem.perBankRdBursts::7 393 # Per bank write bursts -system.physmem.perBankRdBursts::8 389 # Per bank write bursts +system.physmem.perBankRdBursts::0 309 # Per bank write bursts +system.physmem.perBankRdBursts::1 384 # Per bank write bursts +system.physmem.perBankRdBursts::2 476 # Per bank write bursts +system.physmem.perBankRdBursts::3 363 # Per bank write bursts +system.physmem.perBankRdBursts::4 357 # Per bank write bursts +system.physmem.perBankRdBursts::5 335 # Per bank write bursts +system.physmem.perBankRdBursts::6 419 # Per bank write bursts +system.physmem.perBankRdBursts::7 395 # Per bank write bursts +system.physmem.perBankRdBursts::8 387 # Per bank write bursts system.physmem.perBankRdBursts::9 296 # Per bank write bursts -system.physmem.perBankRdBursts::10 257 # Per bank write bursts -system.physmem.perBankRdBursts::11 272 # Per bank write bursts -system.physmem.perBankRdBursts::12 232 # Per bank write bursts -system.physmem.perBankRdBursts::13 487 # Per bank write bursts -system.physmem.perBankRdBursts::14 416 # Per bank write bursts -system.physmem.perBankRdBursts::15 283 # Per bank write bursts +system.physmem.perBankRdBursts::10 260 # Per bank write bursts +system.physmem.perBankRdBursts::11 268 # Per bank write bursts +system.physmem.perBankRdBursts::12 228 # Per bank write bursts +system.physmem.perBankRdBursts::13 486 # Per bank write bursts +system.physmem.perBankRdBursts::14 420 # Per bank write bursts +system.physmem.perBankRdBursts::15 286 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103278386000 # Total gap between requests +system.physmem.totGap 103189107000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5668 # Read request sizes (log2) +system.physmem.readPktSize::6 5669 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,321 +187,331 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1276 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 283.335423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.570090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 315.354372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 562 44.04% 44.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 260 20.38% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 126 9.87% 74.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 5.09% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 2.98% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 4.08% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.51% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.96% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 116 9.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1276 # Bytes accessed per row activation -system.physmem.totQLat 44968750 # Total ticks spent queuing -system.physmem.totMemAccLat 151243750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7933.79 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1243 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.012068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.006967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.689818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 565 45.45% 45.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 237 19.07% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 7.64% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.23% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 45 3.62% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.59% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 2.33% 87.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 1.69% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 129 10.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1243 # Bytes accessed per row activation +system.physmem.totQLat 180648250 # Total ticks spent queuing +system.physmem.totMemAccLat 286942000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31865.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26683.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 50615.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4387 # Number of row buffer hits during reads +system.physmem.readRowHits 4421 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18221310.16 # Average gap between requests -system.physmem.pageHitRate 77.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5677560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3097875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 23649600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 18202347.33 # Average gap between requests +system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5333580 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2823480 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 21691320 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3123252585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 59226559500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 69127776960 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.342795 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 98524507750 # Time in different power states -system.physmem_0.memoryStateTime::REF 3448640000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1303957250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3969000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2165625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20412600 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 286422240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 93806610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 15765120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 717579270 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 394813440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 24141432120 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 25679671980 # Total energy per rank (pJ) +system.physmem_0.averagePower 248.859682 # Core power per rank (mW) +system.physmem_0.totalIdleTime 102941166250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 30119500 # Time in different power states +system.physmem_0.memoryStateTime::REF 121808000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 100340787250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1028168000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 94814000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1573665250 # Time in different power states +system.physmem_1.actEnergy 3577140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1893705 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18785340 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3000772125 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 59333991750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 69106850940 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.140248 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 98704275500 # Time in different power states -system.physmem_1.memoryStateTime::REF 3448640000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1124404000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40909998 # Number of BP lookups -system.cpu.branchPred.condPredicted 40909998 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6747980 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35338690 # Number of BTB lookups +system.physmem_1.refreshEnergy 224343600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72770760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12467520 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 571365720 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 300199680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 24277951200 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 25483354665 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.957187 # Core power per rank (mW) +system.physmem_1.totalIdleTime 102997073250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23820000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95422000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 100962546500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 781772000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 72828000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1252973500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40834752 # Number of BP lookups +system.cpu.branchPred.condPredicted 40834752 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6720926 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35301077 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3198330 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 606499 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35338690 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9879284 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25459406 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5040736 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3198104 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 606453 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35301077 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9875363 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25425714 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5011557 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206556844 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 206378725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46378865 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 420308215 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40909998 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13077614 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152415438 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14966481 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 135 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 72789 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 564 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41283191 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1528436 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206357094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.419964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660932 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 46270336 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 419359791 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40834752 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13073467 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152339601 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14895691 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 89 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 73704 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 808 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41191275 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1518616 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206138472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.415591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660484 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99044157 48.00% 48.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5139433 2.49% 50.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5380650 2.61% 53.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5336666 2.59% 55.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6016483 2.92% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5851353 2.84% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5736237 2.78% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4733991 2.29% 66.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 69118124 33.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99063302 48.06% 48.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5137465 2.49% 50.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5366260 2.60% 53.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5330020 2.59% 55.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6010905 2.92% 58.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5824389 2.83% 61.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5722044 2.78% 64.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4745811 2.30% 66.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68938276 33.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206357094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.198057 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.034831 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32325248 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86371056 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62511253 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17666297 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7483240 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 591444337 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7483240 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42110583 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46566289 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29410 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68967744 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41199828 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 552624215 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1533 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36277086 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4842177 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 151976 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 630066400 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1487530571 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 975657611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15077279 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 206138472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197863 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.031991 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32237214 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86447407 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62317142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17688864 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7447845 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 590237823 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7447845 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42013779 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46504501 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31211 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68811152 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41329984 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 551593859 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1410 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36393589 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4822156 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 169929 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 628796373 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1484193525 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 973498992 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15084169 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 370636950 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2363 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2376 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89140950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128894590 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45939948 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77227738 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25186602 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 490698604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59973 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338566221 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1098463 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 269395193 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 527209931 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 58728 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206357094 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640681 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805896 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 369366923 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2443 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2459 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89351866 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128676829 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45848779 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77202780 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25186397 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 489944627 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61663 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338268196 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1105632 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 268642906 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 525336348 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60418 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206138472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640976 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805234 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73312584 35.53% 35.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46573584 22.57% 58.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32816576 15.90% 74.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20907210 10.13% 84.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15065478 7.30% 91.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8412685 4.08% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5234413 2.54% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2370472 1.15% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1664092 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73134407 35.48% 35.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46607709 22.61% 58.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32815647 15.92% 74.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20883524 10.13% 84.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15044203 7.30% 91.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8407546 4.08% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5216740 2.53% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2365929 1.15% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1662767 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206357094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206138472 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 762770 19.47% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2718793 69.40% 88.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 436106 11.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 759085 19.35% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2731626 69.64% 88.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 432034 11.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211777 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216613901 63.98% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 799985 0.24% 64.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7047582 2.08% 66.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1810682 0.53% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 84424015 24.94% 92.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26658279 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211760 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216459489 63.99% 64.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800418 0.24% 64.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7047773 2.08% 66.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1809637 0.53% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 84315938 24.93% 92.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26623181 7.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338566221 # Type of FU issued -system.cpu.iq.rate 1.639095 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3917669 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011571 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 880328489 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 745561228 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 316131833 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8177179 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15427221 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3556889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 337169115 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4102998 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18179072 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 338268196 # Type of FU issued +system.cpu.iq.rate 1.639065 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3922745 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011597 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 879521716 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 744046350 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 315909602 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8181525 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15431147 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3556535 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 336873543 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4105638 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18155877 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72245003 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55572 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 872144 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25424231 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 72027242 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 864575 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25333062 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50651 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50542 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 27 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7483240 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35798970 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 583606 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490758577 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1261619 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128894590 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45939948 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 21909 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 539997 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 37637 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 872144 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1294345 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6884684 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8179029 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326602378 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80777118 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11963843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7447845 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35704467 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 582987 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490006290 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1248239 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128676829 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45848779 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22549 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 539423 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38394 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 864575 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1296720 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6850218 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8146938 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326347367 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80684613 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11920829 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106442155 # number of memory reference insts executed -system.cpu.iew.exec_branches 18940356 # Number of branches executed -system.cpu.iew.exec_stores 25665037 # Number of stores executed -system.cpu.iew.exec_rate 1.581174 # Inst execution rate -system.cpu.iew.wb_sent 322715986 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319688722 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256576217 # num instructions producing a value -system.cpu.iew.wb_consumers 435723594 # num instructions consuming a value -system.cpu.iew.wb_rate 1.547703 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588851 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 269420821 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 106316260 # number of memory reference insts executed +system.cpu.iew.exec_branches 18920718 # Number of branches executed +system.cpu.iew.exec_stores 25631647 # Number of stores executed +system.cpu.iew.exec_rate 1.581303 # Inst execution rate +system.cpu.iew.wb_sent 322480012 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319466137 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256417161 # num instructions producing a value +system.cpu.iew.wb_consumers 435540007 # num instructions consuming a value +system.cpu.iew.wb_rate 1.547961 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588734 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 268667644 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6753005 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163742250 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.351901 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.936120 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6725958 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163655626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.352617 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.935975 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67180478 41.03% 41.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54846489 33.50% 74.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13227508 8.08% 82.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10675855 6.52% 89.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5434961 3.32% 92.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3126709 1.91% 94.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1096647 0.67% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1147781 0.70% 95.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7005822 4.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67077696 40.99% 40.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54856110 33.52% 74.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13235317 8.09% 82.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10672053 6.52% 89.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5439540 3.32% 92.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3134329 1.92% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1088236 0.66% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1157500 0.71% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6994845 4.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163742250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163655626 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -547,469 +557,469 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7005822 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 647520633 # The number of ROB reads -system.cpu.rob.rob_writes 1024585644 # The number of ROB writes -system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199750 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6994845 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 646691809 # The number of ROB reads +system.cpu.rob.rob_writes 1022946396 # The number of ROB writes +system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 240253 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.563981 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.563981 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639394 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639394 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524858514 # number of integer regfile reads -system.cpu.int_regfile_writes 289109549 # number of integer regfile writes -system.cpu.fp_regfile_reads 4527972 # number of floating regfile reads -system.cpu.fp_regfile_writes 3322072 # number of floating regfile writes -system.cpu.cc_regfile_reads 107078976 # number of cc regfile reads -system.cpu.cc_regfile_writes 65816113 # number of cc regfile writes -system.cpu.misc_regfile_reads 177007720 # number of misc regfile reads +system.cpu.cpi 1.562632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.562632 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639946 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639946 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524499390 # number of integer regfile reads +system.cpu.int_regfile_writes 288922915 # number of integer regfile writes +system.cpu.fp_regfile_reads 4524370 # number of floating regfile reads +system.cpu.fp_regfile_writes 3323309 # number of floating regfile writes +system.cpu.cc_regfile_reads 107020933 # number of cc regfile reads +system.cpu.cc_regfile_writes 65779043 # number of cc regfile writes +system.cpu.misc_regfile_reads 176790948 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 77 # number of replacements -system.cpu.dcache.tags.tagsinuse 1524.395872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82831685 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2117 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39126.917808 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 81 # number of replacements +system.cpu.dcache.tags.tagsinuse 1508.634180 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82760913 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2105 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39316.348219 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1524.395872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.372167 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.372167 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2040 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 411 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1479 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165670739 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165670739 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62317357 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62317357 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513773 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513773 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82831130 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82831130 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82831130 # number of overall hits -system.cpu.dcache.overall_hits::total 82831130 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1223 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1223 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1958 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1958 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3181 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3181 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3181 # number of overall misses -system.cpu.dcache.overall_misses::total 3181 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77985000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77985000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 124974000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 124974000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 202959000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 202959000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 202959000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 202959000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62318580 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62318580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1508.634180 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.368319 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.368319 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2024 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 423 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1459 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165529197 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165529197 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 62246604 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62246604 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513664 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513664 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82760268 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82760268 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82760268 # number of overall hits +system.cpu.dcache.overall_hits::total 82760268 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1211 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1211 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2067 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2067 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3278 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3278 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3278 # number of overall misses +system.cpu.dcache.overall_misses::total 3278 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 109883500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 109883500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 137432000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 137432000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 247315500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 247315500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 247315500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 247315500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62247815 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62247815 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82834311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82834311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82834311 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82834311 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000095 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63765.331153 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63765.331153 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63827.374872 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63827.374872 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63803.520905 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63803.520905 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 403 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 82763546 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82763546 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82763546 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82763546 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000101 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000101 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 90737.819983 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 90737.819983 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66488.630866 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66488.630866 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75447.071385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75447.071385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75447.071385 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 307 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.777778 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 76.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 622 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 622 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 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overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38801.953520 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.occ_blocks::cpu.inst 1674.310192 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.817534 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.817534 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1988 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 841 # Occupied blocks per task id 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-system.cpu.l2cache.overall_mshr_miss_latency::total 384080500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995392 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995392 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428133 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.881469 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.881469 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.535121 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.535121 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65943.783069 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65943.783069 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67314.911797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67314.911797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76051.136364 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76051.136364 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18024 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7043 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1515 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1515 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3636 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3636 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 518 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 518 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3636 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2033 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5669 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3636 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2033 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5669 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110602500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110602500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 349163500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 349163500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 60126000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 60126000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 349163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 170728500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 519892000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 349163500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 170728500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 519892000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995401 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995401 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.427111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888508 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888508 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.533905 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.427111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965796 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.533905 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73004.950495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73004.950495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96029.565457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96029.565457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 116073.359073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 116073.359073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96029.565457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83978.603050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91707.884989 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18313 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7194 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 597 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9504 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9638 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6489 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 61 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 8907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 599 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5178 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1094080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 433 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 27712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11458 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.082912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.275760 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackClean 6530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 9056 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 583 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24098 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5373 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29471 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 962688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 135744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1098432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 543 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 34752 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11702 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100496 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300673 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10508 91.71% 91.71% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 950 8.29% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10526 89.95% 89.95% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1176 10.05% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11458 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15517998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11702 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15702500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13359000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13582500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3392501 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3428499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5668 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5669 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4155 # Transaction distribution -system.membus.trans_dist::ReadExReq 1512 # Transaction distribution -system.membus.trans_dist::ReadExResp 1512 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4156 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11335 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11335 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11335 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 362688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 103189362000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4154 # Transaction distribution +system.membus.trans_dist::ReadExReq 1515 # Transaction distribution +system.membus.trans_dist::ReadExResp 1515 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4154 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11338 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11338 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11338 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 362816 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5668 # Request fanout histogram +system.membus.snoop_fanout::samples 5669 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5668 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5669 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5668 # Request fanout histogram -system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5669 # Request fanout histogram +system.membus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30060000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30047500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |