diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
| commit | cfb805cc71bd1c4b72691b69faa879663e548c11 (patch) | |
| tree | 4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/long/se | |
| parent | 612f8f074fa1099cf70faf495d46cc647762a031 (diff) | |
| download | gem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz | |
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/long/se')
64 files changed, 6774 insertions, 4488 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 09e0d3e34..fd7ad70a0 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 88b266667..c4b7fa411 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:37:28 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:10:45 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x50d0380 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -23,4 +24,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 26911413000 because target called exit() +Exiting @ tick 26911921000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index f2d38a430..8c91cbc4e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026911 # Number of seconds simulated -sim_ticks 26911413000 # Number of ticks simulated -final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026912 # Number of seconds simulated +sim_ticks 26911921000 # Number of ticks simulated +final_tick 26911921000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180996 # Simulator instruction rate (inst/s) -host_op_rate 182296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53768206 # Simulator tick rate (ticks/s) -host_mem_usage 381936 # Number of bytes of host memory used -host_seconds 500.51 # Real time elapsed on the host +host_inst_rate 176190 # Simulator instruction rate (inst/s) +host_op_rate 177456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52341651 # Simulator tick rate (ticks/s) +host_mem_usage 402844 # Number of bytes of host memory used +host_seconds 514.16 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory -system.physmem.bytes_read::total 993152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14808 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15518 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1688503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35215988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36904491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1688503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1688503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1688503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35215988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36904491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15518 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947776 # Number of bytes read from this memory +system.physmem.bytes_read::total 993280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14809 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1690849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35217701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36908551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1690849 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1690849 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1690849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35217701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36908551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15520 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15518 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15520 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 993152 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 993280 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 993152 # Total read bytes from the system interface side +system.physmem.bytesReadSys 993280 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 987 # Per bank write bursts +system.physmem.perBankRdBursts::0 989 # Per bank write bursts system.physmem.perBankRdBursts::1 886 # Per bank write bursts system.physmem.perBankRdBursts::2 942 # Per bank write bursts -system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1050 # Per bank write bursts +system.physmem.perBankRdBursts::3 1029 # Per bank write bursts +system.physmem.perBankRdBursts::4 1049 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts -system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1080 # Per bank write bursts +system.physmem.perBankRdBursts::6 1079 # Per bank write bursts +system.physmem.perBankRdBursts::7 1079 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 959 # Per bank write bursts system.physmem.perBankRdBursts::10 938 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26911220500 # Total gap between requests +system.physmem.totGap 26911727500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15518 # Read request sizes (log2) +system.physmem.readPktSize::6 15520 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -154,126 +154,126 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1598.759289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 481.680955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2200.761860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 153 24.72% 24.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 75 12.12% 36.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 40 6.46% 43.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 20 3.23% 46.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 12 1.94% 48.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 0.97% 49.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 27 4.36% 53.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 12 1.94% 55.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.81% 56.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.62% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.48% 58.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.65% 59.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.81% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.29% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.48% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 19 3.07% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.48% 71.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.81% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 6 0.97% 91.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 619 # Bytes accessed per row activation -system.physmem.totQLat 103760250 # Total ticks spent queuing -system.physmem.totMemAccLat 357130250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77590000 # Total ticks spent in databus transfers -system.physmem.totBankLat 175780000 # Total ticks spent accessing banks -system.physmem.avgQLat 6686.44 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11327.49 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 622 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1591.562701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 476.433802 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2197.906875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 160 25.72% 25.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 68 10.93% 36.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 41 6.59% 43.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 21 3.38% 46.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 13 2.09% 48.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 0.96% 49.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 27 4.34% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 12 1.93% 55.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.80% 56.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 10 1.61% 58.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.48% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.64% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.80% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.29% 61.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.48% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 0.96% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.32% 64.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.64% 65.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6 0.96% 66.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 19 3.05% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 6 0.96% 70.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.96% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.48% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 6 0.96% 73.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 6 0.96% 74.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.16% 76.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 5 0.80% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.64% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.64% 79.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.32% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.16% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.64% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.64% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.80% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.64% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 6 0.96% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.32% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 12 1.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 622 # Bytes accessed per row activation +system.physmem.totQLat 103005000 # Total ticks spent queuing +system.physmem.totMemAccLat 356453750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77600000 # Total ticks spent in databus transfers +system.physmem.totBankLat 175848750 # Total ticks spent accessing banks +system.physmem.avgQLat 6636.92 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11330.46 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23013.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 22967.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage @@ -281,40 +281,61 @@ system.physmem.busUtilRead 0.29 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14899 # Number of row buffer hits during reads +system.physmem.readRowHits 14898 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.01 # Row buffer hit rate for reads +system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734193.87 # Average gap between requests -system.physmem.pageHitRate 96.01 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 36904491 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 980 # Transaction distribution -system.membus.trans_dist::ReadResp 980 # Transaction distribution +system.physmem.avgGap 1734003.06 # Average gap between requests +system.physmem.pageHitRate 95.99 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.99 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36908551 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 982 # Transaction distribution +system.membus.trans_dist::ReadResp 982 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31038 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 993152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 993152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31042 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31042 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 993280 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 993280 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19253000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19254500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145212249 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 26686306 # Number of BP lookups -system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11366672 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11283030 # Number of BTB hits +system.cpu.branchPred.lookups 26683530 # Number of BP lookups +system.cpu.branchPred.condPredicted 22001633 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 843091 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11366562 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11283436 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.264147 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70474 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 170 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.268679 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69998 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 165 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -336,6 +357,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -358,99 +400,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53822827 # number of cpu cycles simulated +system.cpu.numCycles 53823843 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14174375 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127897951 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26686306 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11353504 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24037647 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4766390 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11312706 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 108 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 14173676 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127895760 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26683530 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11353434 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24037387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4765940 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11314746 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13845393 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329438 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53431463 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410222 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13845039 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329540 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53432137 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214797 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29432152 55.08% 55.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389873 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028658 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1553769 2.91% 68.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668148 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2920061 5.47% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1509677 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090745 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9838380 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29433098 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389468 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2029496 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1553729 2.91% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1668795 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2919650 5.46% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1509735 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090422 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9837744 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53431463 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495818 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.376277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16937925 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9159010 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22405754 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1030805 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3897969 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4444268 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8691 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126081524 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42632 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3897969 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18719458 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3589629 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 186437 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21552986 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5484984 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123156725 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 425837 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4596994 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1284 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143603336 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536446832 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 500029218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 672 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53432137 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495757 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.376192 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16937041 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9161066 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22405812 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1030640 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3897578 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444113 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8703 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126077551 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42669 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3897578 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18718868 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3591285 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186478 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21552610 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5485318 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123153621 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 426233 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4596906 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1480 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143604331 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536493258 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 499981919 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 760 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36189150 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4635 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4633 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12540789 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29477429 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5520545 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2151265 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1294097 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118170448 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8500 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105167442 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79307 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26742090 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65583646 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53431463 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968268 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908949 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36190145 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4605 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4603 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12541075 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29476574 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5520683 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2151148 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1293650 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118168195 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8471 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105168426 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79356 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26740210 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65568590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53432137 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908954 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15374280 28.77% 28.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11649569 21.80% 50.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8250468 15.44% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6827782 12.78% 78.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4953380 9.27% 88.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2948609 5.52% 93.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2456731 4.60% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 528512 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442132 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15374181 28.77% 28.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11650585 21.80% 50.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8250698 15.44% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6826591 12.78% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4953996 9.27% 88.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2948586 5.52% 93.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2456814 4.60% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 528614 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442072 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53431463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53432137 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45750 6.92% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45737 6.91% 6.91% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available @@ -479,13 +521,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340320 51.44% 58.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275443 41.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340297 51.45% 58.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275411 41.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74429619 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10979 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74430007 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10980 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -507,90 +549,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 129 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 130 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 165 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 172 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25613153 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5113394 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25613380 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5113753 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105167442 # Type of FU issued -system.cpu.iq.rate 1.953956 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661540 # FU busy when requested +system.cpu.iq.FU_type_0::total 105168426 # Type of FU issued +system.cpu.iq.rate 1.953938 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661472 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264506537 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144925816 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102691564 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 657 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 923 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105828655 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 441760 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 264509133 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144921601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102693545 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 684 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 985 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 281 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105829562 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441614 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6903463 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6716 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6442 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 775701 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6902608 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6756 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6465 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 775839 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31606 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31615 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3897969 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 957023 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126637 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118191644 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310003 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29477429 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5520545 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4612 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65722 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6738 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6442 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 447212 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446019 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 893231 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104191675 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25292948 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 975767 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3897578 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 958412 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126923 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118189357 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 310100 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29476574 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5520683 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4583 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65855 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6705 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6465 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447219 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445977 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 893196 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104191790 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25292626 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 976636 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12696 # number of nop insts executed -system.cpu.iew.exec_refs 30349771 # number of memory reference insts executed -system.cpu.iew.exec_branches 21326762 # Number of branches executed -system.cpu.iew.exec_stores 5056823 # Number of stores executed -system.cpu.iew.exec_rate 1.935827 # Inst execution rate -system.cpu.iew.wb_sent 102970942 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102691851 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62249009 # num instructions producing a value -system.cpu.iew.wb_consumers 104309545 # num instructions consuming a value +system.cpu.iew.exec_nop 12691 # number of nop insts executed +system.cpu.iew.exec_refs 30349836 # number of memory reference insts executed +system.cpu.iew.exec_branches 21326689 # Number of branches executed +system.cpu.iew.exec_stores 5057210 # Number of stores executed +system.cpu.iew.exec_rate 1.935792 # Inst execution rate +system.cpu.iew.wb_sent 102971901 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102693826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62250392 # num instructions producing a value +system.cpu.iew.wb_consumers 104309215 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907961 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907962 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596787 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26941617 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26939334 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834570 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49533494 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842248 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540561 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834485 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49534559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842208 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540547 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20042935 40.46% 40.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13146551 26.54% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4167484 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431298 6.93% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1535317 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 726626 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954928 1.93% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253259 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275096 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20043988 40.46% 40.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13146531 26.54% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4167490 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431351 6.93% 82.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1535298 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 726633 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 954931 1.93% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253243 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275094 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49533494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49534559 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,105 +643,105 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275096 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275094 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162447241 # The number of ROB reads -system.cpu.rob.rob_writes 240306728 # The number of ROB writes -system.cpu.timesIdled 46009 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 391364 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162446025 # The number of ROB reads +system.cpu.rob.rob_writes 240301749 # The number of ROB writes +system.cpu.timesIdled 46102 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 391706 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.594138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594138 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683111 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683111 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495604527 # number of integer regfile reads -system.cpu.int_regfile_writes 120552200 # number of integer regfile writes -system.cpu.fp_regfile_reads 148 # number of floating regfile reads -system.cpu.fp_regfile_writes 360 # number of floating regfile writes -system.cpu.misc_regfile_reads 29090078 # number of misc regfile reads +system.cpu.cpi 0.594149 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594149 # CPI: Total CPI of All Threads +system.cpu.ipc 1.683079 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.683079 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495606364 # number of integer regfile reads +system.cpu.int_regfile_writes 120553547 # number of integer regfile writes +system.cpu.fp_regfile_reads 143 # number of floating regfile reads +system.cpu.fp_regfile_writes 349 # number of floating regfile writes +system.cpu.misc_regfile_reads 29209842 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4497665284 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942892 # Transaction distribution +system.cpu.toL2Bus.throughput 4497544713 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942884 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43700 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43700 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1472 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839564 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120991360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121038400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121038400 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 43696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43696 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1476 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838066 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120990272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121037440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121037440 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888506500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 1888491000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1222499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1225749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424110491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424096491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 632.612747 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13844401 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 735 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18835.919728 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 632.652083 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13844045 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 737 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18784.321574 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 732 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 632.652083 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 734 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.357422 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27691521 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27691521 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13844401 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13844401 # number of overall hits -system.cpu.icache.overall_hits::total 13844401 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 991 # number of overall misses -system.cpu.icache.overall_misses::total 991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67770748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67770748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67770748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67770748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67770748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67770748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13845392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13845392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13845392 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13845392 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13845392 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13845392 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_task_id_percent::1024 0.358398 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 27690815 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27690815 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13844045 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13844045 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13844045 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13844045 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13844045 # number of overall hits +system.cpu.icache.overall_hits::total 13844045 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 993 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 993 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 993 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 993 # number of overall misses +system.cpu.icache.overall_misses::total 993 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66969998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66969998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66969998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66969998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66969998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66969998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13845038 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13845038 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13845038 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13845038 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13845038 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13845038 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68386.224016 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68386.224016 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68386.224016 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68386.224016 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 651 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67442.092649 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67442.092649 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67442.092649 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67442.092649 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 594 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of 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of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 838638750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40836000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797802750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 838638750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001086 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 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miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60433.418367 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016366 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016366 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57434.599156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63724.169742 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59170.315682 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53656.194112 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53656.194112 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53689.193837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53689.193837 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57434.599156 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53872.830711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54036.001933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57434.599156 # average overall mshr miss latency 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.701049 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.741279 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896421 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896421 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 448 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3128 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3140 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 59988680 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 59988680 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532846 # number of WriteReq hits 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miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8458649331 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1376014 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1376014 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1376014 # number of overall misses +system.cpu.dcache.overall_misses::total 1376014 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893935229 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13893935229 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8459874583 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8459874583 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22353097810 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22353097810 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22353097810 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22353097810 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24777753 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24777753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 22353809812 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22353809812 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22353809812 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22353809812 # number of overall miss cycles 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-system.cpu.dcache.demand_accesses::cpu.data 29512734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29512734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29512734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29512734 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047380 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047380 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042690 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042690 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046628 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046628 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046628 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046628 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.326533 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.326533 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41846.534895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41846.534895 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29512602 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29512602 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29512602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29512602 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047377 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047377 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042689 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042689 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.877365 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.877365 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41853.424675 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41853.424675 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16243.614499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16243.614499 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154190 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16245.336030 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16245.336030 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154233 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23957 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.436115 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.439522 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks -system.cpu.dcache.writebacks::total 942892 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270066 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 270066 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks +system.cpu.dcache.writebacks::total 942884 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269973 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269973 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428516 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428516 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428516 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428516 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903915 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903915 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43685 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43685 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947600 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947600 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947600 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947600 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994483010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994483010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1318924416 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1318924416 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313407426 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11313407426 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313407426 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11313407426 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 428423 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428423 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428423 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428423 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903910 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903910 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43681 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43681 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947591 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947591 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947591 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947591 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994274260 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994274260 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319346668 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319346668 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313620928 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11313620928 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313620928 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11313620928 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009226 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009226 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.883678 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.883678 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30191.700034 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30191.700034 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.713899 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.713899 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30204.131499 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30204.131499 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 8155e41d5..000056a51 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index 35b926dc8..c759bbe65 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:39:34 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:11:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x63b66c0 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index be3e03048..0430a3e3f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240661000 # Number of ticks simulated final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2327254 # Simulator instruction rate (inst/s) -host_op_rate 2343964 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1393249116 # Simulator tick rate (ticks/s) -host_mem_usage 371180 # Number of bytes of host memory used -host_seconds 38.93 # Real time elapsed on the host +host_inst_rate 2151308 # Simulator instruction rate (inst/s) +host_op_rate 2166754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1287915883 # Simulator tick rate (ticks/s) +host_mem_usage 391064 # Number of bytes of host memory used +host_seconds 42.12 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91252960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9960199711 # Th system.membus.data_through_bus 540247816 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 112245 # nu system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 396912478 # number of times the integer registers were read +system.cpu.num_int_register_reads 396967282 # number of times the integer registers were read system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index f9a7d69b3..5e43af11f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 92da3b737..ea901fcca 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:40:24 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:12:31 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5565040 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index f99edcca6..a1028c3a3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1334589 # Simulator instruction rate (inst/s) -host_op_rate 1344158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2167949307 # Simulator tick rate (ticks/s) -host_mem_usage 379884 # Number of bytes of host memory used -host_seconds 67.87 # Real time elapsed on the host +host_inst_rate 1098833 # Simulator instruction rate (inst/s) +host_op_rate 1106711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1784978875 # Simulator tick rate (ticks/s) +host_mem_usage 400800 # Number of bytes of host memory used +host_seconds 82.43 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 112245 # nu system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read +system.cpu.num_int_register_reads 464618159 # number of times the integer registers were read system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index d70753e9b..b9d303473 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 0f922bcc1..980a69a9d 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:41:42 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:14:04 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4cfd380 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -67,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 202741893000 because target called exit() +Exiting @ tick 202696649500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 3185557ef..4ea8f08d5 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202742 # Number of seconds simulated -sim_ticks 202741893000 # Number of ticks simulated -final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202697 # Number of seconds simulated +sim_ticks 202696649500 # Number of ticks simulated +final_tick 202696649500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148118 # Simulator instruction rate (inst/s) -host_op_rate 166994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59436990 # Simulator tick rate (ticks/s) -host_mem_usage 253144 # Number of bytes of host memory used -host_seconds 3411.04 # Real time elapsed on the host +host_inst_rate 142513 # Simulator instruction rate (inst/s) +host_op_rate 160675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57175030 # Simulator tick rate (ticks/s) +host_mem_usage 274024 # Number of bytes of host memory used +host_seconds 3545.20 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory -system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory -system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148209 # Number of read requests accepted -system.physmem.writeReqs 97655 # Number of write requests accepted -system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue -system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 215936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9269696 # Number of bytes read from this memory +system.physmem.bytes_read::total 9485632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 215936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 215936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6249792 # Number of bytes written to this memory +system.physmem.bytes_written::total 6249792 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3374 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144839 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148213 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97653 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97653 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1065316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45731866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46797182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1065316 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1065316 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30833228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30833228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30833228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1065316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45731866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77630410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148213 # Number of read requests accepted +system.physmem.writeReqs 97653 # Number of write requests accepted +system.physmem.readBursts 148213 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97653 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9481152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4480 # Total number of bytes read from write queue +system.physmem.bytesWritten 6249152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9485632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6249792 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 70 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9585 # Per bank write bursts -system.physmem.perBankRdBursts::1 9243 # Per bank write bursts -system.physmem.perBankRdBursts::2 9257 # Per bank write bursts -system.physmem.perBankRdBursts::3 8972 # Per bank write bursts -system.physmem.perBankRdBursts::4 9761 # Per bank write bursts -system.physmem.perBankRdBursts::5 9639 # Per bank write bursts -system.physmem.perBankRdBursts::6 9125 # Per bank write bursts -system.physmem.perBankRdBursts::7 8321 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 7 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9594 # Per bank write bursts +system.physmem.perBankRdBursts::1 9237 # Per bank write bursts +system.physmem.perBankRdBursts::2 9258 # Per bank write bursts +system.physmem.perBankRdBursts::3 8983 # Per bank write bursts +system.physmem.perBankRdBursts::4 9776 # Per bank write bursts +system.physmem.perBankRdBursts::5 9641 # Per bank write bursts +system.physmem.perBankRdBursts::6 9120 # Per bank write bursts +system.physmem.perBankRdBursts::7 8318 # Per bank write bursts system.physmem.perBankRdBursts::8 8799 # Per bank write bursts -system.physmem.perBankRdBursts::9 8911 # Per bank write bursts -system.physmem.perBankRdBursts::10 8951 # Per bank write bursts -system.physmem.perBankRdBursts::11 9736 # Per bank write bursts -system.physmem.perBankRdBursts::12 9644 # Per bank write bursts -system.physmem.perBankRdBursts::13 9766 # Per bank write bursts -system.physmem.perBankRdBursts::14 8945 # Per bank write bursts -system.physmem.perBankRdBursts::15 9461 # Per bank write bursts -system.physmem.perBankWrBursts::0 6262 # Per bank write bursts -system.physmem.perBankWrBursts::1 6160 # Per bank write bursts -system.physmem.perBankWrBursts::2 6087 # Per bank write bursts -system.physmem.perBankWrBursts::3 5881 # Per bank write bursts -system.physmem.perBankWrBursts::4 6253 # Per bank write bursts -system.physmem.perBankWrBursts::5 6276 # Per bank write bursts -system.physmem.perBankWrBursts::6 6048 # Per bank write bursts -system.physmem.perBankWrBursts::7 5555 # Per bank write bursts -system.physmem.perBankWrBursts::8 5811 # Per bank write bursts -system.physmem.perBankWrBursts::9 5907 # Per bank write bursts -system.physmem.perBankWrBursts::10 5994 # Per bank write bursts -system.physmem.perBankWrBursts::11 6518 # Per bank write bursts -system.physmem.perBankWrBursts::12 6370 # Per bank write bursts -system.physmem.perBankWrBursts::13 6328 # Per bank write bursts -system.physmem.perBankWrBursts::14 6055 # Per bank write bursts -system.physmem.perBankWrBursts::15 6145 # Per bank write bursts +system.physmem.perBankRdBursts::9 8914 # Per bank write bursts +system.physmem.perBankRdBursts::10 8952 # Per bank write bursts +system.physmem.perBankRdBursts::11 9727 # Per bank write bursts +system.physmem.perBankRdBursts::12 9657 # Per bank write bursts +system.physmem.perBankRdBursts::13 9778 # Per bank write bursts +system.physmem.perBankRdBursts::14 8939 # Per bank write bursts +system.physmem.perBankRdBursts::15 9450 # Per bank write bursts +system.physmem.perBankWrBursts::0 6271 # Per bank write bursts +system.physmem.perBankWrBursts::1 6158 # Per bank write bursts +system.physmem.perBankWrBursts::2 6091 # Per bank write bursts +system.physmem.perBankWrBursts::3 5883 # Per bank write bursts +system.physmem.perBankWrBursts::4 6254 # Per bank write bursts +system.physmem.perBankWrBursts::5 6272 # Per bank write bursts +system.physmem.perBankWrBursts::6 6041 # Per bank write bursts +system.physmem.perBankWrBursts::7 5553 # Per bank write bursts +system.physmem.perBankWrBursts::8 5808 # Per bank write bursts +system.physmem.perBankWrBursts::9 5908 # Per bank write bursts +system.physmem.perBankWrBursts::10 5990 # Per bank write bursts +system.physmem.perBankWrBursts::11 6516 # Per bank write bursts +system.physmem.perBankWrBursts::12 6373 # Per bank write bursts +system.physmem.perBankWrBursts::13 6333 # Per bank write bursts +system.physmem.perBankWrBursts::14 6051 # Per bank write bursts +system.physmem.perBankWrBursts::15 6141 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202741873000 # Total gap between requests +system.physmem.totGap 202696525000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148209 # Read request sizes (log2) +system.physmem.readPktSize::6 148213 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97655 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97653 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -130,175 +130,197 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4501 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.469277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.950297 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.311281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 32073 46.38% 46.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 12750 18.44% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5391 7.80% 72.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3340 4.83% 77.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2388 3.45% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2364 3.42% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3443 4.98% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1961 2.84% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 807 1.17% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 577 0.83% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 471 0.68% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 358 0.52% 95.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 272 0.39% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 260 0.38% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 188 0.27% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 160 0.23% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 170 0.25% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 142 0.21% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 124 0.18% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 152 0.22% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 134 0.19% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 815 1.18% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 105 0.15% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 136 0.20% 99.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 89 0.13% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 48 0.07% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 64 0.09% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 20 0.03% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 34 0.05% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 21 0.03% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 9 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 15 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 7 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 10 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 5 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 7 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 7 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 10 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 8 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 7 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 2 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 3 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 4 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 5 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 2 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 1 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 4 0.01% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 4 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 1 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 1 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 3 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 8 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 4 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation -system.physmem.totQLat 1735354000 # Total ticks spent queuing -system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks -system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::5376 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69151 # Bytes accessed per row activation +system.physmem.totQLat 1733842500 # Total ticks spent queuing +system.physmem.totMemAccLat 4938805000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740715000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2464247500 # Total ticks spent accessing banks +system.physmem.avgQLat 11703.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16634.25 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33338.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 46.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 46.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing -system.physmem.readRowHits 118629 # Number of row buffer hits during reads -system.physmem.writeRowHits 57942 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes -system.physmem.avgGap 824609.84 # Average gap between requests -system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 77612139 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46927 # Transaction distribution -system.membus.trans_dist::ReadResp 46926 # Transaction distribution -system.membus.trans_dist::Writeback 97655 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 101282 # Transaction distribution -system.membus.trans_dist::ReadExResp 101282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15735232 # Total data (bytes) +system.physmem.avgWrQLen 8.92 # Average write queue length when enqueuing +system.physmem.readRowHits 118670 # Number of row buffer hits during reads +system.physmem.writeRowHits 57965 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes +system.physmem.avgGap 824418.69 # Average gap between requests +system.physmem.pageHitRate 71.86 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.58 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 77630410 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46935 # Transaction distribution +system.membus.trans_dist::ReadResp 46935 # Transaction distribution +system.membus.trans_dist::Writeback 97653 # Transaction distribution +system.membus.trans_dist::UpgradeReq 7 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 101278 # Transaction distribution +system.membus.trans_dist::ReadExResp 101278 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394093 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394093 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735424 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15735424 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15735424 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083458000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1398218993 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 182821881 # Number of BP lookups -system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits +system.cpu.branchPred.lookups 182767812 # Number of BP lookups +system.cpu.branchPred.condPredicted 143090812 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7262422 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93142512 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87193307 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.612793 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12680291 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116092 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -320,6 +342,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -342,99 +385,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 405483787 # number of cpu cycles simulated +system.cpu.numCycles 405393300 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119358761 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761461935 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182767812 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99873598 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170116443 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35667741 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77537943 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 427 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114511433 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2436940 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394614975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164245 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986660 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224511182 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14185619 3.59% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22882928 5.80% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22735959 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20902964 5.30% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11599090 2.94% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13052635 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11995684 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52748914 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 394614975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.450841 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.878329 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129045860 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73029235 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158776788 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6235766 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27527326 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26113836 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76704 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825433505 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295928 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27527326 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135634392 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10115343 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47882338 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158241210 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15214366 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800503248 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1357 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3055222 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8963577 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 323 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954180101 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3518022066 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3236814887 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 287927810 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293035 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293033 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41823481 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170244853 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73468690 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28584671 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15947575 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 754970143 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775446 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665247715 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1368678 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187299729 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479807189 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797814 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394614975 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734907 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139112608 35.25% 35.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69963718 17.73% 52.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71480339 18.11% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53412881 13.54% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31169155 7.90% 92.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15993671 4.05% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8759011 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2903101 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1820491 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394614975 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 480625 5.03% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available @@ -463,15 +506,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6529255 68.28% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2553152 26.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447743251 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383309 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -497,84 +540,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153363071 23.05% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63757987 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued -system.cpu.iq.rate 1.640858 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665247715 # Type of FU issued +system.cpu.iq.rate 1.640993 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9563032 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014375 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736041890 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 946851577 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 645982069 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 225 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674810634 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8546846 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44215298 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41270 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810207 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16608213 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19520 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8279 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27527326 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5271033 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 384981 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760303523 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1119045 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170244853 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73468690 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286904 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219731 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11453 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810207 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4335544 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4001823 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8337367 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655831134 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150081839 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9416581 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558919 # number of nop insts executed -system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed -system.cpu.iew.exec_branches 138505177 # Number of branches executed -system.cpu.iew.exec_stores 62475461 # Number of stores executed -system.cpu.iew.exec_rate 1.617619 # Inst execution rate -system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374710129 # num instructions producing a value -system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value +system.cpu.iew.exec_nop 1557934 # number of nop insts executed +system.cpu.iew.exec_refs 212547196 # number of memory reference insts executed +system.cpu.iew.exec_branches 138487054 # Number of branches executed +system.cpu.iew.exec_stores 62465357 # Number of stores executed +system.cpu.iew.exec_rate 1.617765 # Inst execution rate +system.cpu.iew.wb_sent 650951989 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 645982085 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374676308 # num instructions producing a value +system.cpu.iew.wb_consumers 646230138 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back +system.cpu.iew.wb_rate 1.593470 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579788 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189364408 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7188399 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367087649 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.230509 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159393543 43.42% 43.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98511772 26.84% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33830447 9.22% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18783252 5.12% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16176645 4.41% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7442765 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6952611 1.89% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3163238 0.86% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22833376 6.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367087649 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -585,239 +628,239 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22833376 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104828701 # The number of ROB reads -system.cpu.rob.rob_writes 1548619548 # The number of ROB writes -system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104579710 # The number of ROB reads +system.cpu.rob.rob_writes 1548313166 # The number of ROB writes +system.cpu.timesIdled 328667 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10778325 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads -system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads -system.cpu.int_regfile_writes 752019512 # number of integer regfile writes +system.cpu.cpi 0.802381 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.802381 # CPI: Total CPI of All Threads +system.cpu.ipc 1.246290 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.246290 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058357965 # number of integer regfile reads +system.cpu.int_regfile_writes 751931601 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads +system.cpu.misc_regfile_reads 237823379 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 733902057 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110906 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 71 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 71 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348829 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504262 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3537891 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1073600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147680832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148754432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148754432 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273126497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25848480 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1823961981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15017 # number of replacements -system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 14927 # number of replacements +system.cpu.icache.tags.tagsinuse 1097.546967 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114490465 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16785 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6820.998808 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1849 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.902832 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 229105594 # Number of tag accesses -system.cpu.icache.tags.data_accesses 229105594 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114523215 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114523215 # number of overall hits -system.cpu.icache.overall_hits::total 114523215 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21116 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21116 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21116 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21116 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21116 # number of overall misses -system.cpu.icache.overall_misses::total 21116 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 569003980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 569003980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 569003980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 569003980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 569003980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 569003980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114544331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114544331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114544331 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114544331 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114544331 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114544331 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26946.579845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26946.579845 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26946.579845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26946.579845 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1001 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1097.546967 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.535912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.535912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 229039718 # Number of tag accesses +system.cpu.icache.tags.data_accesses 229039718 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 114490465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114490465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114490465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114490465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114490465 # number of overall hits +system.cpu.icache.overall_hits::total 114490465 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20967 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20967 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20967 # number of overall misses +system.cpu.icache.overall_misses::total 20967 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 566965977 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 566965977 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 566965977 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 566965977 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 566965977 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 566965977 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114511432 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114511432 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114511432 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114511432 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114511432 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114511432 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000183 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000183 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000183 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000183 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000183 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000183 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27040.872657 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27040.872657 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27040.872657 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27040.872657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27040.872657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27040.872657 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 85.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4183 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4183 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4183 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4183 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4183 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4183 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16933 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16933 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16933 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16933 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16933 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16933 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 412315016 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 412315016 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 412315016 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 412315016 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 412315016 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 412315016 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24349.791295 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24349.791295 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4113 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4113 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4113 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4113 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16854 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16854 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16854 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16854 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16854 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16854 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 413760769 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 413760769 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 413760769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 413760769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 413760769 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 413760769 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000147 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000147 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000147 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24549.707429 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24549.707429 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24549.707429 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24549.707429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24549.707429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24549.707429 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that 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MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3374 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43561 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46935 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101280 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101280 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3374 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144841 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148215 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3374 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144841 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148215 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 219732000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944554000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3164286000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 50005 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 50005 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6265225502 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6265225502 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 219732000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9209779502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9429511502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 219732000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9209779502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9429511502 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201133 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051383 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054288 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.070423 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.070423 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290343 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290343 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121043 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122150 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121043 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122150 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65125.074096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67596.106609 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67418.472355 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61835.189528 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61835.189528 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860.441370 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860.441370 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65125.074096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63585.445433 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63620.493891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65125.074096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63585.445433 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63620.493891 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192730 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.514955 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190201285 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196826 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.921418 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1192511 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.506365 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190177939 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196607 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.930993 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.506365 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990602 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990602 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2352 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 391502938 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 391502938 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50988251 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488825 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488825 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 391455847 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 391455847 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 136212044 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136212044 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50988351 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50988351 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488804 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488804 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits -system.cpu.dcache.overall_hits::total 187223724 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1700874 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3251055 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4951929 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4951929 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4951929 # number of overall misses -system.cpu.dcache.overall_misses::total 4951929 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29724371713 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 72455016224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187200395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187200395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187200395 # number of overall hits +system.cpu.dcache.overall_hits::total 187200395 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1700889 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1700889 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3250955 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3250955 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4951844 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4951844 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4951844 # number of overall misses +system.cpu.dcache.overall_misses::total 4951844 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29691567711 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29691567711 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 72513714730 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 72513714730 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 595500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 595500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102205282441 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102205282441 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102205282441 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102205282441 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137912933 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137912933 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488840 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488840 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192152239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192152239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192152239 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192152239 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012333 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012333 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059937 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059937 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025770 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025770 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025770 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025770 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17456.499343 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17456.499343 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22305.357881 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 22305.357881 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16541.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16541.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20639.842944 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20639.842944 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20639.842944 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20639.842944 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17574 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52604 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1663 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.567649 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.582451 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks -system.cpu.dcache.writebacks::total 1110997 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1110906 # number of writebacks +system.cpu.dcache.writebacks::total 1110906 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852565 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 852565 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902601 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902601 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3755166 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3755166 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3755166 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3755166 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848324 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848324 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348354 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348354 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196678 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196678 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196678 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196678 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12420423026 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12420423026 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10423297989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10423297989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22843721015 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22843721015 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22843721015 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22843721015 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14641.131249 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14641.131249 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29921.568258 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29921.568258 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.279668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.279668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.279668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.279668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 3b7a89fcb..b14a667a9 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index edefc9939..af6242a6d 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:44:24 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:19:30 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5d016c0 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index d2cbe9ffb..a575cce26 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu sim_ticks 290498967000 # Number of ticks simulated final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2346027 # Simulator instruction rate (inst/s) -host_op_rate 2644207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1345327991 # Simulator tick rate (ticks/s) -host_mem_usage 241300 # Number of bytes of host memory used -host_seconds 215.93 # Real time elapsed on the host +host_inst_rate 2103217 # Simulator instruction rate (inst/s) +host_op_rate 2370536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1206088561 # Simulator tick rate (ticks/s) +host_mem_usage 262216 # Number of bytes of host memory used +host_seconds 240.86 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 570968167 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9312824252 # Th system.membus.data_through_bus 2705365825 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 19311615 # nu system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read +system.cpu.num_int_register_reads 2482508148 # number of times the integer registers were read system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index cc298b9ef..ac28a9b86 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 13fa82ee3..36fd0e9c5 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:45:59 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:21:27 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x6322040 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index feaf610e8..8fb3b6819 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu sim_ticks 717366012000 # Number of ticks simulated final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1243497 # Simulator instruction rate (inst/s) -host_op_rate 1401211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1766466230 # Simulator tick rate (ticks/s) -host_mem_usage 251064 # Number of bytes of host memory used -host_seconds 406.10 # Real time elapsed on the host +host_inst_rate 1131056 # Simulator instruction rate (inst/s) +host_op_rate 1274509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1606737202 # Simulator tick rate (ticks/s) +host_mem_usage 271980 # Number of bytes of host memory used +host_seconds 446.47 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.1 # La system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 19311615 # nu system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read +system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 9e26a822b..2cd58faa0 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 704a64531..d9e911681 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:48:11 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:23:42 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4718040 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 @@ -13,4 +14,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.060000 -Exiting @ tick 68509635500 because target called exit() +Exiting @ tick 68503867000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d1e8937b6..634fe5f9a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068510 # Number of seconds simulated -sim_ticks 68509635500 # Number of ticks simulated -final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068504 # Number of seconds simulated +sim_ticks 68503867000 # Number of ticks simulated +final_tick 68503867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157844 # Simulator instruction rate (inst/s) -host_op_rate 201796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39605771 # Simulator tick rate (ticks/s) -host_mem_usage 257252 # Number of bytes of host memory used -host_seconds 1729.79 # Real time elapsed on the host +host_inst_rate 147835 # Simulator instruction rate (inst/s) +host_op_rate 189000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37091215 # Simulator tick rate (ticks/s) +host_mem_usage 278164 # Number of bytes of host memory used +host_seconds 1846.90 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory -system.physmem.bytes_read::total 466944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194560 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4256 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7296 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2839892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3975849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6815742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2839892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2839892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2839892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3975849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6815742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7296 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 193984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::total 466240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2831723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3974316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6806039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2831723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2831723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2831723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3974316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6806039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7286 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7296 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7286 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466944 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466944 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466304 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 607 # Per bank write bursts -system.physmem.perBankRdBursts::1 801 # Per bank write bursts +system.physmem.perBankRdBursts::0 606 # Per bank write bursts +system.physmem.perBankRdBursts::1 800 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 444 # Per bank write bursts -system.physmem.perBankRdBursts::5 356 # Per bank write bursts -system.physmem.perBankRdBursts::6 162 # Per bank write bursts -system.physmem.perBankRdBursts::7 220 # Per bank write bursts +system.physmem.perBankRdBursts::4 443 # Per bank write bursts +system.physmem.perBankRdBursts::5 354 # Per bank write bursts +system.physmem.perBankRdBursts::6 164 # Per bank write bursts +system.physmem.perBankRdBursts::7 219 # Per bank write bursts system.physmem.perBankRdBursts::8 207 # Per bank write bursts -system.physmem.perBankRdBursts::9 294 # Per bank write bursts -system.physmem.perBankRdBursts::10 324 # Per bank write bursts -system.physmem.perBankRdBursts::11 416 # Per bank write bursts +system.physmem.perBankRdBursts::9 291 # Per bank write bursts +system.physmem.perBankRdBursts::10 322 # Per bank write bursts +system.physmem.perBankRdBursts::11 415 # Per bank write bursts system.physmem.perBankRdBursts::12 529 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts system.physmem.perBankRdBursts::14 611 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68509447000 # Total gap between requests +system.physmem.totGap 68503846500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7296 # Read request sizes (log2) +system.physmem.readPktSize::6 7286 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,80 +154,83 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1278 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 364.419405 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.521659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 755.556461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 528 41.31% 41.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 217 16.98% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 132 10.33% 68.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 73 5.71% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 38 2.97% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 36 2.82% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 30 2.35% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 40 3.13% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 1.17% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 24 1.88% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 7 0.55% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.02% 90.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 4 0.31% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 0.78% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.39% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.47% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 7 0.55% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.55% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.23% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.31% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.23% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 6 0.47% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 5 0.39% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 0.39% 95.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.16% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 5 0.39% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 4 0.31% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.23% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.16% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 361.604977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.647663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 753.981601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 537 41.76% 41.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 220 17.11% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 131 10.19% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 77 5.99% 75.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 39 3.03% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 38 2.95% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 26 2.02% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 31 2.41% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 17 1.32% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 23 1.79% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 0.47% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 16 1.24% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.23% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 0.62% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 0.54% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.54% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 0.39% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 8 0.62% 93.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.47% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.08% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.31% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.31% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 6 0.47% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.23% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.23% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.23% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 4 0.31% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.23% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.16% 96.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.08% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.08% 97.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.08% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.08% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.08% 99.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1278 # Bytes accessed per row activation -system.physmem.totQLat 61296000 # Total ticks spent queuing -system.physmem.totMemAccLat 197202250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36480000 # Total ticks spent in databus transfers -system.physmem.totBankLat 99426250 # Total ticks spent accessing banks -system.physmem.avgQLat 8401.32 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13627.50 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 1286 # Bytes accessed per row activation +system.physmem.totQLat 62980000 # Total ticks spent queuing +system.physmem.totMemAccLat 198080000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36430000 # Total ticks spent in databus transfers +system.physmem.totBankLat 98670000 # Total ticks spent accessing banks +system.physmem.avgQLat 8643.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13542.41 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27028.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27186.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.82 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -235,40 +238,61 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6018 # Number of row buffer hits during reads +system.physmem.readRowHits 6000 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9390000.96 # Average gap between requests -system.physmem.pageHitRate 82.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6815742 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4471 # Transaction distribution -system.membus.trans_dist::ReadResp 4471 # Transaction distribution +system.physmem.avgGap 9402120.02 # Average gap between requests +system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6806039 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4462 # Transaction distribution +system.membus.trans_dist::ReadResp 4461 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 2825 # Transaction distribution -system.membus.trans_dist::ReadExResp 2825 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14596 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466944 # Total data (bytes) +system.membus.trans_dist::ReadExReq 2824 # Transaction distribution +system.membus.trans_dist::ReadExResp 2824 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466240 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466240 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8937500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8931500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67747998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 35425567 # Number of BP lookups -system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19605313 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16823422 # Number of BTB hits +system.cpu.branchPred.lookups 35407535 # Number of BP lookups +system.cpu.branchPred.condPredicted 21210003 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1658535 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19582924 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16814113 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.810525 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6781780 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8434 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.861095 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6780652 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8453 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -290,6 +314,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -312,100 +357,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137019272 # number of cpu cycles simulated +system.cpu.numCycles 137007735 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39008530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 318058207 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35425567 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23605202 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70950828 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6887573 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21494775 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1573 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 38995510 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317974758 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35407535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23594765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70934448 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6878177 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21511393 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1738 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37609299 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 515132 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136671204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454359 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37596145 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 512137 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136651264 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454335 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66353464 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6794042 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5704725 4.17% 57.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6102503 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4920388 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4084365 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3186134 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4139625 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35385958 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66349844 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6791529 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5702360 4.17% 57.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6103499 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4918940 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4085838 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3180821 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4138782 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35379651 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136671204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258544 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.321266 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45524127 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16648036 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66820925 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2531461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5146655 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7342433 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69027 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401839978 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 214083 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5146655 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51074305 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1910036 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63741314 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14466395 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394244633 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 55 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1658642 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10186296 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1132 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432779208 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2333721873 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575557795 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200430073 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136651264 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258435 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.320853 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45513422 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16662187 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66798256 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2538078 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5139321 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7340905 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69056 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401756741 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 208904 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5139321 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51060721 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1905439 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332675 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63727748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14485360 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394162913 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1657895 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10187119 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 22377 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432668253 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2737675688 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575239963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200387111 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48213015 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36510705 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103606610 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91402094 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4304684 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5331956 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384603029 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22794 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374241110 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1211414 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34812310 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 87759919 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136671204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024772 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 48102060 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11946 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11945 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36528458 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103595819 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91394334 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4295156 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5297473 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384542604 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374214780 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1210476 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34753044 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 100302329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136651264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024544 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25129949 18.39% 18.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19927179 14.58% 32.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20562891 15.05% 48.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18173263 13.30% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24036101 17.59% 78.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15736190 11.51% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814920 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3372202 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 918509 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25105050 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19938594 14.59% 32.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20566375 15.05% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18171632 13.30% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24028761 17.58% 78.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15737538 11.52% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814188 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372330 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 916796 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136671204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136651264 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8708 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8713 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -424,22 +469,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46360 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46317 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7648 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 433 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190801 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4328 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241338 1.36% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9265240 52.28% 55.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7952555 44.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3518 0.02% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 440 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 186929 1.05% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4248 0.02% 1.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241299 1.36% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9275439 52.33% 55.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7953254 44.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126474576 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175710 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126461637 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175765 0.58% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued @@ -450,7 +495,7 @@ system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued @@ -458,93 +503,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6781686 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6779975 1.81% 36.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8476200 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430464 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1596092 0.43% 39.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20867035 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7174148 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130628 1.91% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101661693 27.16% 76.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88297588 23.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8474577 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430301 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595259 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20865413 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172902 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130224 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101650995 27.16% 76.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88302442 23.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374241110 # Type of FU issued -system.cpu.iq.rate 2.731303 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17722107 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047355 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654665747 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289075917 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250124446 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249421198 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130376340 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118073548 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263342959 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128620258 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11085750 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374214780 # Type of FU issued +system.cpu.iq.rate 2.731341 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17724852 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047365 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654627146 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288999508 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250114053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249389006 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130333197 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118063719 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263337797 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128601835 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11086522 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8957862 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 109225 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14255 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9026511 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8947071 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 108758 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14277 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9018751 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 173986 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1905 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 174712 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1900 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5146655 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 274797 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35672 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384627381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 873173 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103606610 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91402094 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11760 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14255 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1300817 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370830 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1671647 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370280641 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100372061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3960469 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5139321 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 272764 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35129 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384567184 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 874047 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103595819 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91394334 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11885 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 280 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14277 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1299093 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 369514 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1668607 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370257441 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100364532 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3957339 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558 # number of nop insts executed -system.cpu.iew.exec_refs 187586293 # number of memory reference insts executed -system.cpu.iew.exec_branches 32011507 # Number of branches executed -system.cpu.iew.exec_stores 87214232 # Number of stores executed -system.cpu.iew.exec_rate 2.702398 # Inst execution rate -system.cpu.iew.wb_sent 368867964 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368197994 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183086265 # num instructions producing a value -system.cpu.iew.wb_consumers 363871713 # num instructions consuming a value +system.cpu.iew.exec_nop 1661 # number of nop insts executed +system.cpu.iew.exec_refs 187583075 # number of memory reference insts executed +system.cpu.iew.exec_branches 32009347 # Number of branches executed +system.cpu.iew.exec_stores 87218543 # Number of stores executed +system.cpu.iew.exec_rate 2.702456 # Inst execution rate +system.cpu.iew.wb_sent 368846220 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368177772 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183055174 # num instructions producing a value +system.cpu.iew.wb_consumers 363803620 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687199 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503162 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687277 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503170 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35562440 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35502239 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1591916 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131524549 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.653992 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659233 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1589851 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131511943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.654246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.658719 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34720675 26.40% 26.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28457654 21.64% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13339371 10.14% 58.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11431101 8.69% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13773309 10.47% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7413510 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3874860 2.95% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3887136 2.96% 88.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14626933 11.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34696225 26.38% 26.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28452590 21.63% 48.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13345612 10.15% 58.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11442919 8.70% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13780020 10.48% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7417113 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3869989 2.94% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3892889 2.96% 88.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14614586 11.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131524549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131511943 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,238 +600,238 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14626933 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14614586 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501522594 # The number of ROB reads -system.cpu.rob.rob_writes 774405807 # The number of ROB writes -system.cpu.timesIdled 6645 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 348068 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501462134 # The number of ROB reads +system.cpu.rob.rob_writes 774278104 # The number of ROB writes +system.cpu.timesIdled 6640 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 356471 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501835 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501835 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992688 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992688 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769988396 # number of integer regfile reads -system.cpu.int_regfile_writes 233047297 # number of integer regfile writes -system.cpu.fp_regfile_reads 188164665 # number of floating regfile reads -system.cpu.fp_regfile_writes 132532739 # number of floating regfile writes -system.cpu.misc_regfile_reads 566941334 # number of misc regfile reads +system.cpu.cpi 0.501792 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501792 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992856 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992856 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769894079 # number of integer regfile reads +system.cpu.int_regfile_writes 233026497 # number of integer regfile writes +system.cpu.fp_regfile_reads 188140638 # number of floating regfile reads +system.cpu.fp_regfile_writes 132514898 # number of floating regfile writes +system.cpu.misc_regfile_reads 1201076625 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20093174 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1036 # Transaction distribution +system.cpu.toL2Bus.throughput 20069641 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1035 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1376320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1376320 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 2841 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2841 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1374592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1374592 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11791500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 11777500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24322738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24288488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7408962 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7388212 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13968 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.251388 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37591948 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15858 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2370.535250 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13947 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.346697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37578823 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2372.999684 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.346697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 75234453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 75234453 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37591948 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37591948 # number of overall hits -system.cpu.icache.overall_hits::total 37591948 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17349 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17349 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17349 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17349 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17349 # number of overall misses -system.cpu.icache.overall_misses::total 17349 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 451171984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 451171984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 451171984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 451171984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 451171984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 451171984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37609297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37609297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37609297 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37609297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37609297 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37609297 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1530 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 75208123 # Number of tag accesses +system.cpu.icache.tags.data_accesses 75208123 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 37578823 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37578823 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37578823 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37578823 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37578823 # number of overall hits +system.cpu.icache.overall_hits::total 37578823 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17320 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17320 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17320 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17320 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17320 # number of overall misses +system.cpu.icache.overall_misses::total 17320 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 450229234 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 450229234 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 450229234 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 450229234 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 450229234 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 450229234 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37596143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37596143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37596143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37596143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37596143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37596143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26005.647818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26005.647818 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26005.647818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26005.647818 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2002 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25994.759469 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25994.759469 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2351 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 87.043478 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.040000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15859 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15859 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15859 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15859 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15859 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359132259 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359132259 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359132259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359132259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359132259 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359132259 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22645.328142 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22645.328142 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1482 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1482 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1482 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1482 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1482 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1482 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15838 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15838 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15838 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15838 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15838 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15838 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359653509 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359653509 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359653509 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359653509 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359653509 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359653509 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22708.265501 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22708.265501 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22708.265501 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22708.265501 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22708.265501 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22708.265501 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3941.799565 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13198 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.446793 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3937.367139 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13183 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5383 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.449006 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 379.005926 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.464306 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 776.329333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085036 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120294 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5394 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1235 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 378.211483 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2780.743240 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 778.412416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011542 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.023755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.120159 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5383 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1236 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4014 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164612 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180292 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180292 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13104 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1036 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1036 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4007 # Occupied blocks per task id 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(read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12803 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 318 # number of overall hits -system.cpu.l2cache.overall_hits::total 13121 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3052 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1471 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4523 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 12790 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 316 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13106 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12790 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 316 # number of overall hits +system.cpu.l2cache.overall_hits::total 13106 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3044 # number of ReadReq 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ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62957.342657 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59879.594352 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58489.734513 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58489.734513 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency 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count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37087.576573 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3102.941006 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757554 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757554 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3103.986618 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757809 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 684 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 682 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2449 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342019754 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342019754 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88929043 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88929043 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 342002086 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 342002086 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88920204 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88920204 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031597 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11020 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11020 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170960424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170960424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170960424 # number of overall hits -system.cpu.dcache.overall_hits::total 170960424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3956 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3956 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170951801 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170951801 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170951801 # number of overall hits +system.cpu.dcache.overall_hits::total 170951801 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3952 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3952 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21068 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21068 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25240 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25240 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25240 # number of overall misses -system.cpu.dcache.overall_misses::total 25240 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 235586955 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 235586955 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1260992389 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1260992389 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25020 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25020 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25020 # number of overall misses +system.cpu.dcache.overall_misses::total 25020 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 237491705 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 237491705 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1258064893 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1258064893 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1496579344 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1496579344 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1496579344 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1496579344 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88932999 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88932999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1495556598 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1495556598 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1495556598 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1495556598 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88924156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88924156 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11022 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170985664 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170985664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170985664 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170985664 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170976821 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170976821 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170976821 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170976821 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59551.808645 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59551.808645 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59246.024666 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59246.024666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59293.951823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59293.951823 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28312 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59774.444365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59774.444365 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 27944 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 411 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 406 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.885645 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.827586 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks -system.cpu.dcache.writebacks::total 1036 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks +system.cpu.dcache.writebacks::total 1035 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2181 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2181 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18227 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18227 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20624 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20624 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20624 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20624 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114384040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 114384040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203208498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 203208498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317592538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 317592538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317592538 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 317592538 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20408 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20408 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20408 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20408 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115481540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 115481540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201937248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 201937248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317418788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 317418788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317418788 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317418788 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -983,14 +1028,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64478.038331 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64478.038331 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71501.934553 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71501.934553 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 098c10a60..d33135638 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index b3ebb4d02..563fc0af8 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:52:31 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:27:26 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x56d96c0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 02fd51087..b6b6bed83 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu sim_ticks 212344043000 # Number of ticks simulated final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1679583 # Simulator instruction rate (inst/s) -host_op_rate 2147266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1306228104 # Simulator tick rate (ticks/s) -host_mem_usage 246496 # Number of bytes of host memory used -host_seconds 162.56 # Real time elapsed on the host +host_inst_rate 1312619 # Simulator instruction rate (inst/s) +host_op_rate 1678120 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1020836459 # Simulator tick rate (ticks/s) +host_mem_usage 266392 # Number of bytes of host memory used +host_seconds 208.01 # Real time elapsed on the host sim_insts 273037663 # Number of instructions simulated sim_ops 349065399 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 10715621794 # Th system.membus.data_through_bus 2275398455 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 12448615 # nu system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls system.cpu.num_int_insts 279584918 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 1887652153 # number of times the integer registers were read +system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index aa5380744..3089e084a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 32b55c30c..9d7fb2434 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:52:55 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:29:04 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4c37d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 5bfa9270c..7d607329f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu sim_ticks 525834342000 # Number of ticks simulated final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 870200 # Simulator instruction rate (inst/s) -host_op_rate 1112519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1677723175 # Simulator tick rate (ticks/s) -host_mem_usage 255236 # Number of bytes of host memory used -host_seconds 313.42 # Real time elapsed on the host +host_inst_rate 719381 # Simulator instruction rate (inst/s) +host_op_rate 919702 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1386947293 # Simulator tick rate (ticks/s) +host_mem_usage 276148 # Number of bytes of host memory used +host_seconds 379.13 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 12448615 # nu system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls system.cpu.num_int_insts 279584917 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read +system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 116b954da..1aaeea9d1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index f17e243b1..542867b6f 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:55:24 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:31:04 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4c3a340 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index f4aa63ff2..b6f8c26dc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.629535 # Nu sim_ticks 629535413500 # Number of ticks simulated final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111054 # Simulator instruction rate (inst/s) -host_op_rate 151240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50501117 # Simulator tick rate (ticks/s) -host_mem_usage 257896 # Number of bytes of host memory used -host_seconds 12465.77 # Real time elapsed on the host +host_inst_rate 106173 # Simulator instruction rate (inst/s) +host_op_rate 144593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48281629 # Simulator tick rate (ticks/s) +host_mem_usage 278772 # Number of bytes of host memory used +host_seconds 13038.82 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -264,14 +264,14 @@ system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # By system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation -system.physmem.totQLat 3804882250 # Total ticks spent queuing -system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3804806750 # Total ticks spent queuing +system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks -system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s @@ -303,20 +303,41 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34627840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 438247561 # Number of BP lookups -system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted +system.cpu.branchPred.lookups 438247722 # Number of BP lookups +system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups -system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits +system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups +system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -338,6 +359,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -363,94 +405,94 @@ system.cpu.workload.num_syscalls 1411 # Nu system.cpu.numCycles 1259070828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch +system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available @@ -486,7 +528,7 @@ system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued @@ -519,17 +561,17 @@ system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Ty system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued -system.cpu.iq.rate 1.934087 # Inst issue rate +system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued +system.cpu.iq.rate 1.934086 # Inst issue rate system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -540,13 +582,13 @@ system.cpu.iew.lsq.thread0.squashedStores 208692629 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions @@ -556,43 +598,43 @@ system.cpu.iew.memOrderViolationEvents 1430281 # Nu system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12446 # number of nop insts executed -system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed +system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed system.cpu.iew.exec_branches 319532182 # Number of branches executed system.cpu.iew.exec_stores 423276586 # Number of stores executed system.cpu.iew.exec_rate 1.874346 # Inst execution rate -system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1349155886 # num instructions producing a value -system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value +system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1349155649 # num instructions producing a value +system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle +system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -605,10 +647,10 @@ system.cpu.commit.int_insts 1653698867 # Nu system.cpu.commit.function_calls 41577833 # Number of function calls committed. system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791959297 # The number of ROB reads -system.cpu.rob.rob_writes 5711929091 # The number of ROB writes +system.cpu.rob.rob_reads 3791959363 # The number of ROB reads +system.cpu.rob.rob_writes 5711929117 # The number of ROB writes system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated @@ -616,11 +658,11 @@ system.cpu.cpi 0.909490 # CP system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads -system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes +system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads +system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes -system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads +system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution @@ -743,7 +785,7 @@ system.cpu.l2cache.tags.total_refs 1110777 # To system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536898 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy @@ -788,16 +830,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2426 # system.cpu.l2cache.overall_misses::cpu.data 472563 # number of overall misses system.cpu.l2cache.overall_misses::total 474989 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176218750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746506500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30922725250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4757394750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4757394750 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 176218750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35503901250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35680120000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35503901250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35680120000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 25018 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1464549 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1489567 # number of ReadReq accesses(hits+misses) @@ -827,16 +869,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970 system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,18 +912,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686438000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832075750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611416750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29757054500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611416750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29757054500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses @@ -896,24 +938,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1532970 # number of replacements system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 971409331 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 631.989343 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy @@ -925,20 +967,20 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 977 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1949922006 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1949922006 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits -system.cpu.dcache.overall_hits::total 971375738 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 971375795 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 971375795 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 971375795 # number of overall hits +system.cpu.dcache.overall_hits::total 971375795 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses @@ -949,28 +991,28 @@ system.cpu.dcache.demand_misses::cpu.data 2796744 # n system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses system.cpu.dcache.overall_misses::total 2796744 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses @@ -981,16 +1023,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked @@ -1019,14 +1061,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -1035,14 +1077,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 879581bbb..1d7b4f375 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 6d065fef8..c4e0dd481 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:58:19 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:35:34 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x49db380 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 982d92f29..059b5a3b1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu sim_ticks 945613126000 # Number of ticks simulated final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1817390 # Simulator instruction rate (inst/s) -host_op_rate 2475033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1241382789 # Simulator tick rate (ticks/s) -host_mem_usage 247108 # Number of bytes of host memory used -host_seconds 761.74 # Real time elapsed on the host +host_inst_rate 1603190 # Simulator instruction rate (inst/s) +host_op_rate 2183323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1095071931 # Simulator tick rate (ticks/s) +host_mem_usage 266996 # Number of bytes of host memory used +host_seconds 863.52 # Real time elapsed on the host sim_insts 1384381606 # Number of instructions simulated sim_ops 1885336358 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9675679644 # Th system.membus.data_through_bus 9149449674 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 80372855 # nu system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 8601515912 # number of times the integer registers were read +system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 0bdfc6610..11c9b066a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 973b4e1bf..f8adf17ee 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:11:12 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:50:08 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x56b7d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index ecd5fda89..f64dc7529 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu sim_ticks 2326118592000 # Number of ticks simulated final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 968971 # Simulator instruction rate (inst/s) -host_op_rate 1314478 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1631393565 # Simulator tick rate (ticks/s) -host_mem_usage 255816 # Number of bytes of host memory used -host_seconds 1425.85 # Real time elapsed on the host +host_inst_rate 908275 # Simulator instruction rate (inst/s) +host_op_rate 1232140 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1529204664 # Simulator tick rate (ticks/s) +host_mem_usage 276728 # Number of bytes of host memory used +host_seconds 1521.13 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 80372855 # nu system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read +system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 3a6f7de14..20429e4aa 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index 1a4f96712..78695e4f1 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1 +1,2 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 51d96dffd..0fe32cbd7 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:17:11 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:54:40 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5a6c340 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 26810051000 because target called exit() +Exiting @ tick 26790388000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 044953ad0..9978094b9 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026810 # Number of seconds simulated -sim_ticks 26810051000 # Number of ticks simulated -final_tick 26810051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026790 # Number of seconds simulated +sim_ticks 26790388000 # Number of ticks simulated +final_tick 26790388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140336 # Simulator instruction rate (inst/s) -host_op_rate 199155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53060871 # Simulator tick rate (ticks/s) -host_mem_usage 257660 # Number of bytes of host memory used -host_seconds 505.27 # Real time elapsed on the host +host_inst_rate 134448 # Simulator instruction rate (inst/s) +host_op_rate 190799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50797444 # Simulator tick rate (ticks/s) +host_mem_usage 278572 # Number of bytes of host memory used +host_seconds 527.40 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 299136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory -system.physmem.bytes_read::total 8242368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 299136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 299136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4674 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128787 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11157607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296278138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307435745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11157607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11157607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200395292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200395292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200395292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11157607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296278138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 507831037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128788 # Number of read requests accepted -system.physmem.writeReqs 83947 # Number of write requests accepted -system.physmem.readBursts 128788 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83947 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8242304 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 297344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942912 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5371968 # Number of bytes written to this memory +system.physmem.bytes_written::total 5371968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124108 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128754 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83937 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83937 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11098906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296483649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307582555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11098906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11098906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200518484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200518484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200518484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11098906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296483649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508101040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128754 # Number of read requests accepted +system.physmem.writeReqs 83937 # Number of write requests accepted +system.physmem.readBursts 128754 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83937 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8240128 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8242432 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372608 # Total written bytes from the system interface side +system.physmem.bytesWritten 5371648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8240256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5371968 # Total written bytes from the system interface side system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8141 # Per bank write bursts -system.physmem.perBankRdBursts::1 8391 # Per bank write bursts -system.physmem.perBankRdBursts::2 8249 # Per bank write bursts -system.physmem.perBankRdBursts::3 8162 # Per bank write bursts -system.physmem.perBankRdBursts::4 8307 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts +system.physmem.perBankRdBursts::0 8131 # Per bank write bursts +system.physmem.perBankRdBursts::1 8390 # Per bank write bursts +system.physmem.perBankRdBursts::2 8247 # Per bank write bursts +system.physmem.perBankRdBursts::3 8163 # Per bank write bursts +system.physmem.perBankRdBursts::4 8302 # Per bank write bursts +system.physmem.perBankRdBursts::5 8446 # Per bank write bursts system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7966 # Per bank write bursts +system.physmem.perBankRdBursts::7 7962 # Per bank write bursts system.physmem.perBankRdBursts::8 8060 # Per bank write bursts -system.physmem.perBankRdBursts::9 7616 # Per bank write bursts -system.physmem.perBankRdBursts::10 7784 # Per bank write bursts -system.physmem.perBankRdBursts::11 7815 # Per bank write bursts -system.physmem.perBankRdBursts::12 7881 # Per bank write bursts -system.physmem.perBankRdBursts::13 7887 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8012 # Per bank write bursts -system.physmem.perBankWrBursts::0 5178 # Per bank write bursts +system.physmem.perBankRdBursts::9 7613 # Per bank write bursts +system.physmem.perBankRdBursts::10 7786 # Per bank write bursts +system.physmem.perBankRdBursts::11 7812 # Per bank write bursts +system.physmem.perBankRdBursts::12 7879 # Per bank write bursts +system.physmem.perBankRdBursts::13 7885 # Per bank write bursts +system.physmem.perBankRdBursts::14 7978 # Per bank write bursts +system.physmem.perBankRdBursts::15 8010 # Per bank write bursts +system.physmem.perBankWrBursts::0 5179 # Per bank write bursts system.physmem.perBankWrBursts::1 5375 # Per bank write bursts -system.physmem.perBankWrBursts::2 5292 # Per bank write bursts +system.physmem.perBankWrBursts::2 5289 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5267 # Per bank write bursts +system.physmem.perBankWrBursts::4 5265 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5206 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts -system.physmem.perBankWrBursts::8 5028 # Per bank write bursts -system.physmem.perBankWrBursts::9 5090 # Per bank write bursts -system.physmem.perBankWrBursts::10 5248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5142 # Per bank write bursts +system.physmem.perBankWrBursts::6 5207 # Per bank write bursts +system.physmem.perBankWrBursts::7 5048 # Per bank write bursts +system.physmem.perBankWrBursts::8 5029 # Per bank write bursts +system.physmem.perBankWrBursts::9 5089 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5144 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5222 # Per bank write bursts +system.physmem.perBankWrBursts::15 5226 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26810034000 # Total gap between requests +system.physmem.totGap 26790282500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128788 # Read request sizes (log2) +system.physmem.readPktSize::6 128754 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83947 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 72914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83937 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,31 +129,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3683 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3683 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -161,190 +161,208 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 358.604352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.758574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 692.410978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15190 40.02% 40.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5700 15.02% 55.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3416 9.00% 64.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2313 6.09% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1704 4.49% 74.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1539 4.05% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1108 2.92% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 903 2.38% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 681 1.79% 85.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 548 1.44% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 355 0.94% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 578 1.52% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 299 0.79% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 386 1.02% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 183 0.48% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 223 0.59% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 117 0.31% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 252 0.66% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 118 0.31% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 257 0.68% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 108 0.28% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 421 1.11% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 88 0.23% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 246 0.65% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 122 0.32% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 43 0.11% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 88 0.23% 97.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 65 0.17% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 27 0.07% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 45 0.12% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 16 0.04% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 15 0.04% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 29 0.08% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 15 0.04% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.276222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.215706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 692.456870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15075 39.80% 39.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5750 15.18% 54.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3421 9.03% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2320 6.12% 70.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1668 4.40% 74.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1547 4.08% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1100 2.90% 81.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 895 2.36% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 687 1.81% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 539 1.42% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 385 1.02% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 594 1.57% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 272 0.72% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 354 0.93% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 173 0.46% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 239 0.63% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 118 0.31% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 108 0.29% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 279 0.74% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 118 0.31% 94.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 446 1.18% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 106 0.28% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 237 0.63% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 118 0.31% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 42 0.11% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 85 0.22% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 20 0.05% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 62 0.16% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 44 0.12% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 19 0.05% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 33 0.09% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 16 0.04% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 33 0.09% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 34 0.09% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 13 0.03% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 17 0.04% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 7 0.02% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 19 0.05% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 33 0.09% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 14 0.04% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 23 0.06% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 10 0.03% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 17 0.04% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 10 0.03% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 27 0.07% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 7 0.02% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 14 0.04% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.03% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 15 0.04% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 11 0.03% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 10 0.03% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 18 0.05% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 17 0.04% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 11 0.03% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 19 0.05% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 26 0.07% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 4 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 10 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 5 0.01% 98.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 13 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 7 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 8 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 13 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 9 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 7 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 8 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 7 0.02% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 6 0.02% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 9 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 7 0.02% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.02% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 16 0.04% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 9 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 10 0.03% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 10 0.03% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 7 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 6 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 7 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 6 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 7 0.02% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 7 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 5 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.01% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 2 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 6 0.02% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 6 0.02% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 6 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 3 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 5 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 35 0.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37958 # Bytes accessed per row activation -system.physmem.totQLat 3020745250 # Total ticks spent queuing -system.physmem.totMemAccLat 4967419000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643930000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1302743750 # Total ticks spent accessing banks -system.physmem.avgQLat 23455.54 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10115.57 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::6464-6465 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 4 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 6 0.02% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 37 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37879 # Bytes accessed per row activation +system.physmem.totQLat 3022726750 # Total ticks spent queuing +system.physmem.totMemAccLat 4971045500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643760000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1304558750 # Total ticks spent accessing banks +system.physmem.avgQLat 23477.12 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10132.34 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38571.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38609.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.51 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.73 # Average write queue length when enqueuing -system.physmem.readRowHits 117878 # Number of row buffer hits during reads -system.physmem.writeRowHits 56878 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.75 # Row buffer hit rate for writes -system.physmem.avgGap 126025.50 # Average gap between requests -system.physmem.pageHitRate 82.15 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 507831037 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26531 # Transaction distribution -system.membus.trans_dist::ReadResp 26530 # Transaction distribution -system.membus.trans_dist::Writeback 83947 # Transaction distribution +system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing +system.physmem.readRowHits 117872 # Number of row buffer hits during reads +system.physmem.writeRowHits 56933 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.83 # Row buffer hit rate for writes +system.physmem.avgGap 125958.70 # Average gap between requests +system.physmem.pageHitRate 82.19 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.78 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 508101040 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26500 # Transaction distribution +system.membus.trans_dist::ReadResp 26500 # Transaction distribution +system.membus.trans_dist::Writeback 83937 # Transaction distribution system.membus.trans_dist::UpgradeReq 308 # Transaction distribution system.membus.trans_dist::UpgradeResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 102257 # Transaction distribution -system.membus.trans_dist::ReadExResp 102257 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342138 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13614976 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13614976 # Total data (bytes) +system.membus.trans_dist::ReadExReq 102254 # Transaction distribution +system.membus.trans_dist::ReadExResp 102254 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13612224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13612224 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13612224 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934752500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934459500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203686693 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203485442 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16646392 # Number of BP lookups -system.cpu.branchPred.condPredicted 12773976 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 607235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10818826 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7781096 # Number of BTB hits +system.cpu.branchPred.lookups 16615535 # Number of BP lookups +system.cpu.branchPred.condPredicted 12754556 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602333 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10795457 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7770077 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.921815 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825486 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113411 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.975434 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823925 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112966 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -366,6 +384,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -388,239 +427,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53620103 # number of cpu cycles simulated +system.cpu.numCycles 53580777 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12555863 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85327612 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16646392 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9606582 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21220606 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2386309 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10655499 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 479 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11697004 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 183631 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46184612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.586702 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12546836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85170403 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16615535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9594002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21183792 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2362024 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10685029 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 557 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11675856 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179932 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46149323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.583841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333163 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24984951 54.10% 54.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2138585 4.63% 58.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1966197 4.26% 62.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2046003 4.43% 67.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1469884 3.18% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1382868 2.99% 73.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958032 2.07% 75.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1189943 2.58% 78.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10048149 21.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24986446 54.14% 54.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2137638 4.63% 58.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1962079 4.25% 63.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2043997 4.43% 67.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466310 3.18% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1377582 2.99% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 960310 2.08% 75.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1185958 2.57% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10029003 21.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46184612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310451 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.591336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14642918 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9005955 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19517473 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1369283 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1648983 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334820 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105179 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116999070 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363013 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1648983 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16350179 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2575616 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1030832 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19130431 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5448571 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115098604 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17023 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4589680 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115425064 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 530260724 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476967295 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2691 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46149323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310103 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.589570 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14635353 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9029918 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19485051 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1368887 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1630114 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3325603 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104819 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116788167 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1630114 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16340014 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2585458 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1028005 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19100045 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5465687 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114914880 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17272 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4606354 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 316 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115243032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529540867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476170049 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2600 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16292392 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16110360 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12970121 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29626660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22464166 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3855353 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4357218 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111639066 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36000 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107318490 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 273494 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10897204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26020912 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46184612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.323685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.992080 # Number of insts issued each cycle +system.cpu.rename.skidInsts 12995984 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29602749 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22439249 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3932152 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4401403 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111507434 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36062 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107242523 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272405 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10768427 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25739903 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46149323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.323816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990206 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10954733 23.72% 23.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8081116 17.50% 41.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7387326 16.00% 57.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7126917 15.43% 72.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5408207 11.71% 84.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3931545 8.51% 92.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1847862 4.00% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 871002 1.89% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 575904 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10919279 23.66% 23.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8079518 17.51% 41.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7423472 16.09% 57.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7094481 15.37% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5420902 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3930329 8.52% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1841974 3.99% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869423 1.88% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 569945 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46184612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46149323 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112087 4.51% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 3 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1355242 54.58% 59.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1015813 40.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112279 4.53% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1361817 54.98% 59.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1002641 40.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56685703 52.82% 52.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91410 0.09% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 203 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28899327 26.93% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21641840 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56635396 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91455 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 208 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28883502 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21631955 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107318490 # Type of FU issued -system.cpu.iq.rate 2.001460 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2483145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023138 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263577666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122600736 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105627540 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 565 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 906 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109801353 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 282 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2178214 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107242523 # Type of FU issued +system.cpu.iq.rate 2.001511 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2476739 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023095 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263382945 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122340040 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105564996 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 568 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 856 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109718975 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 287 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181751 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2319552 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6675 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30486 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1908428 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2295641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6455 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29983 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1883511 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 694 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 679 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1648983 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1092293 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45577 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111684840 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 295051 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29626660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22464166 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20080 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6356 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5380 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30486 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 395595 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 182079 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 577674 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106281813 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28597262 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1036677 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1630114 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1093825 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45147 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111553302 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 294819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29602749 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22439249 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20142 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6322 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5200 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29983 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 180696 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 572523 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106211851 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28585179 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030672 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9774 # number of nop insts executed -system.cpu.iew.exec_refs 49953963 # number of memory reference insts executed -system.cpu.iew.exec_branches 14606559 # Number of branches executed -system.cpu.iew.exec_stores 21356701 # Number of stores executed -system.cpu.iew.exec_rate 1.982126 # Inst execution rate -system.cpu.iew.wb_sent 105847179 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105627710 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53336530 # num instructions producing a value -system.cpu.iew.wb_consumers 104015656 # num instructions consuming a value +system.cpu.iew.exec_nop 9806 # number of nop insts executed +system.cpu.iew.exec_refs 49926975 # number of memory reference insts executed +system.cpu.iew.exec_branches 14599283 # Number of branches executed +system.cpu.iew.exec_stores 21341796 # Number of stores executed +system.cpu.iew.exec_rate 1.982275 # Inst execution rate +system.cpu.iew.wb_sent 105782073 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105565164 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53316718 # num instructions producing a value +system.cpu.iew.wb_consumers 103963305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.969927 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512774 # average fanout of values written-back +system.cpu.iew.wb_rate 1.970206 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512842 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11053294 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10921742 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 504169 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44535629 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.259594 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.766011 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499421 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44519209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.260427 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.765009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15484235 34.77% 34.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11649742 26.16% 60.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3457573 7.76% 68.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2865921 6.44% 75.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1843682 4.14% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1946516 4.37% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 688008 1.54% 85.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565195 1.27% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6034757 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15470185 34.75% 34.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11634994 26.13% 60.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3452010 7.75% 68.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2868846 6.44% 75.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1865323 4.19% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1954753 4.39% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 686748 1.54% 85.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 559469 1.26% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6026881 13.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44535629 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44519209 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -631,243 +670,243 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6034757 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6026881 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150161295 # The number of ROB reads -system.cpu.rob.rob_writes 225029668 # The number of ROB writes -system.cpu.timesIdled 76463 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7435491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150021199 # The number of ROB reads +system.cpu.rob.rob_writes 224747411 # The number of ROB writes +system.cpu.timesIdled 76674 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7431454 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.756197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.756197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.322408 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.322408 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511842322 # number of integer regfile reads -system.cpu.int_regfile_writes 103400028 # number of integer regfile writes -system.cpu.fp_regfile_reads 836 # number of floating regfile reads -system.cpu.fp_regfile_writes 732 # number of floating regfile writes -system.cpu.misc_regfile_reads 49193821 # number of misc regfile reads +system.cpu.cpi 0.755642 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755642 # CPI: Total CPI of All Threads +system.cpu.ipc 1.323378 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.323378 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511545132 # number of integer regfile reads +system.cpu.int_regfile_writes 103340839 # number of integer regfile writes +system.cpu.fp_regfile_reads 806 # number of floating regfile reads +system.cpu.fp_regfile_writes 694 # number of floating regfile writes +system.cpu.misc_regfile_reads 49339612 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 770392865 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 86565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 86563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107049 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107049 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61854 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 516494 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20623232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20623232 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 31040 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290637496 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 773036658 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 87363 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 87363 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107048 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454686 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 518138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2013952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18662976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20676928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20676928 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33024 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291143497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47495730 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 48712731 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260347495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260354993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 28815 # number of replacements -system.cpu.icache.tags.tagsinuse 1808.840382 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11662045 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 30854 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377.975141 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 29638 # number of replacements +system.cpu.icache.tags.tagsinuse 1806.211071 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11640103 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 31672 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 367.520302 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1808.840382 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2039 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1260 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 677 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23425177 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23425177 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11662047 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11662047 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11662047 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11662047 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11662047 # number of overall hits -system.cpu.icache.overall_hits::total 11662047 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34957 # number of overall misses -system.cpu.icache.overall_misses::total 34957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 813284976 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 813284976 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 813284976 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 813284976 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 813284976 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 813284976 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11697004 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11697004 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11697004 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11697004 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11697004 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11697004 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002989 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002989 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002989 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002989 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002989 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002989 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23265.296679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23265.296679 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23265.296679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23265.296679 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2987 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1806.211071 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2034 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.993164 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 23383696 # Number of tag accesses +system.cpu.icache.tags.data_accesses 23383696 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 11640118 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11640118 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11640118 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11640118 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11640118 # number of overall hits +system.cpu.icache.overall_hits::total 11640118 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35738 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35738 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35738 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35738 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35738 # number of overall misses +system.cpu.icache.overall_misses::total 35738 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 828271479 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 828271479 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 828271479 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 828271479 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 828271479 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 828271479 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11675856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11675856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11675856 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11675856 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11675856 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11675856 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003061 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003061 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003061 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003061 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003061 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003061 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23176.212407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23176.212407 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 856 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 129.869565 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3787 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3787 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3787 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3787 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3787 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3787 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31170 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31170 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31170 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31170 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31170 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31170 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 659799769 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 659799769 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 659799769 # number of demand (read+write) MSHR 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+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79472.925155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83633.144077 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83482.568519 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79472.925155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83633.144077 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83482.568519 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -876,202 +915,202 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks -system.cpu.l2cache.writebacks::total 83947 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 83937 # number of writebacks +system.cpu.l2cache.writebacks::total 83937 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4674 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26531 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 79 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4646 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21854 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26500 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4674 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124114 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128788 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4674 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124114 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128788 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 308414000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1593918750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1902332750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3088307 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3088307 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7239546250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7239546250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 308414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8833465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9141879000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 308414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8833465000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9141879000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308213 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.959502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.959502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955235 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955235 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.666850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.666850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65985.023534 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72924.863888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71702.263390 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.970779 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.970779 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70797.561536 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70797.561536 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102254 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102254 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4646 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124108 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4646 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124108 # number of overall MSHR misses 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9143383750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 311360750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8832023000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9143383750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses 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miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71880.594340 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70789.876191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70789.876191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71164.010378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71014.366544 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.032790 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.859504 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993374 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.839586 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993369 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1767 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2268 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2254 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 92301717 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 92301717 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 26063246 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26063246 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266759 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266759 # number of WriteReq hits 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of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44330005 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44330005 # number of overall hits -system.cpu.dcache.overall_hits::total 44330005 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124539 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124539 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583142 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583142 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707681 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707681 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707681 # number of overall misses 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-system.cpu.dcache.overall_miss_latency::total 132215195206 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26187785 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26187785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44315381 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44315381 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44315381 # number of overall hits +system.cpu.dcache.overall_hits::total 44315381 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125140 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125140 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583322 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583322 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708462 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708462 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708462 # number of overall misses +system.cpu.dcache.overall_misses::total 1708462 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205484954 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5205484954 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127036653749 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127036653749 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 856750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 856750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 132242138703 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 132242138703 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132242138703 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132242138703 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26173942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26173942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16032 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16032 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16022 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46037686 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46037686 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46037686 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46037686 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004756 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004756 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079756 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079756 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002682 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002682 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037093 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037093 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037093 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037093 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41885.262568 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41885.262568 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80219.491676 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80219.491676 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24104.651163 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24104.651163 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77423.825179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77423.825179 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3791 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1217 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 149 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.442953 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 93.615385 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46023843 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46023843 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46023843 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46023843 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004781 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004781 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079765 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079765 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037121 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037121 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037121 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037121 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77404.202554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77404.202554 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4865 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1223 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.510949 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 87.357143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129111 # number of writebacks -system.cpu.dcache.writebacks::total 129111 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69110 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69110 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475806 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475806 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55429 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55429 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107336 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107336 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162765 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162765 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162765 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162765 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263965562 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263965562 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8681187684 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8681187684 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945153246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10945153246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945153246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129182 # number of writebacks +system.cpu.dcache.writebacks::total 129182 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69727 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69727 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475983 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475983 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545710 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545710 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545710 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545710 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107339 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107339 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162752 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162752 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162752 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162752 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263243564 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263243564 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8680214182 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8680214182 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10943457746 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10943457746 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10943457746 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10943457746 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40844.423713 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40844.423713 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80878.621190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80878.621190 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index b4899830a..ba6e5f41a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index fd88c13a1..b32e4875d 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:25:48 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:03:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x49b6380 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Exiting @ tick 53932157000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 130b6bb56..d5e255546 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932157000 # Number of ticks simulated final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1940189 # Simulator instruction rate (inst/s) -host_op_rate 2753308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1475586020 # Simulator tick rate (ticks/s) -host_mem_usage 245844 # Number of bytes of host memory used -host_seconds 36.55 # Real time elapsed on the host +host_inst_rate 1720542 # Simulator instruction rate (inst/s) +host_op_rate 2441608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1308536096 # Simulator tick rate (ticks/s) +host_mem_usage 265732 # Number of bytes of host memory used +host_seconds 41.22 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 100632428 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9230371187 # Th system.membus.data_through_bus 497813828 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 3311620 # nu system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 452177195 # number of times the integer registers were read +system.cpu.num_int_register_reads 452305352 # number of times the integer registers were read system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 8802837e9..de369d8f4 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index 89bb0e0aa..4bb28ef2b 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:26:35 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:04:30 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5604d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Exiting @ tick 132689045000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 7d6b41b45..6c81ce1de 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu sim_ticks 132689045000 # Number of ticks simulated final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019812 # Simulator instruction rate (inst/s) -host_op_rate 1446120 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1922848599 # Simulator tick rate (ticks/s) -host_mem_usage 254584 # Number of bytes of host memory used -host_seconds 69.01 # Real time elapsed on the host +host_inst_rate 945773 # Simulator instruction rate (inst/s) +host_op_rate 1341131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1783248877 # Simulator tick rate (ticks/s) +host_mem_usage 275500 # Number of bytes of host memory used +host_seconds 74.41 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.7 # La system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 3311620 # nu system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read +system.cpu.num_int_register_reads 533671029 # number of times the integer registers were read system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index c32ff375e..56ff7911f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index aa09d1777..c3788cdfe 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:27:54 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:05:55 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5017340 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data @@ -24,4 +25,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 533797009000 because target called exit() +Exiting @ tick 533761922000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 5e5db11e7..8c6f8359f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.533797 # Number of seconds simulated -sim_ticks 533797009000 # Number of ticks simulated -final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.533762 # Number of seconds simulated +sim_ticks 533761922000 # Number of ticks simulated +final_tick 533761922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163502 # Simulator instruction rate (inst/s) -host_op_rate 182399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56505895 # Simulator tick rate (ticks/s) -host_mem_usage 249880 # Number of bytes of host memory used -host_seconds 9446.75 # Real time elapsed on the host +host_inst_rate 155948 # Simulator instruction rate (inst/s) +host_op_rate 173972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53891847 # Simulator tick rate (ticks/s) +host_mem_usage 269768 # Number of bytes of host memory used +host_seconds 9904.32 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory -system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70431872 # Number of bytes written to this memory -system.physmem.bytes_written::total 70431872 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246734 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100498 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100498 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 269284566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 269373889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 131945048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 131945048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 131945048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 269284566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401318937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246734 # Number of read requests accepted -system.physmem.writeReqs 1100498 # Number of write requests accepted -system.physmem.readBursts 2246734 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100498 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143754112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36864 # Total number of bytes read from write queue -system.physmem.bytesWritten 70430784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143790976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70431872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143740736 # Number of bytes read from this memory +system.physmem.bytes_read::total 143788352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70437056 # Number of bytes written to this memory +system.physmem.bytes_written::total 70437056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245949 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246693 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100579 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100579 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 269297472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 269386680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 131963434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 131963434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 131963434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 269297472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401350114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246694 # Number of read requests accepted +system.physmem.writeReqs 1100579 # Number of write requests accepted +system.physmem.readBursts 2246694 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100579 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143750848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37568 # Total number of bytes read from write queue +system.physmem.bytesWritten 70435904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143788416 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70437056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 587 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139750 # Per bank write bursts -system.physmem.perBankRdBursts::1 136273 # Per bank write bursts -system.physmem.perBankRdBursts::2 133708 # Per bank write bursts -system.physmem.perBankRdBursts::3 136246 # Per bank write bursts -system.physmem.perBankRdBursts::4 134906 # Per bank write bursts -system.physmem.perBankRdBursts::5 135253 # Per bank write bursts -system.physmem.perBankRdBursts::6 136175 # Per bank write bursts -system.physmem.perBankRdBursts::7 136295 # Per bank write bursts -system.physmem.perBankRdBursts::8 143732 # Per bank write bursts -system.physmem.perBankRdBursts::9 146555 # Per bank write bursts -system.physmem.perBankRdBursts::10 144302 # Per bank write bursts -system.physmem.perBankRdBursts::11 146237 # Per bank write bursts -system.physmem.perBankRdBursts::12 145788 # Per bank write bursts -system.physmem.perBankRdBursts::13 146277 # Per bank write bursts -system.physmem.perBankRdBursts::14 142119 # Per bank write bursts -system.physmem.perBankRdBursts::15 142542 # Per bank write bursts -system.physmem.perBankWrBursts::0 69128 # Per bank write bursts -system.physmem.perBankWrBursts::1 67452 # Per bank write bursts -system.physmem.perBankWrBursts::2 65650 # Per bank write bursts -system.physmem.perBankWrBursts::3 66298 # Per bank write bursts -system.physmem.perBankWrBursts::4 66182 # Per bank write bursts -system.physmem.perBankWrBursts::5 66379 # Per bank write bursts -system.physmem.perBankWrBursts::6 67939 # Per bank write bursts -system.physmem.perBankWrBursts::7 68869 # Per bank write bursts -system.physmem.perBankWrBursts::8 70353 # Per bank write bursts -system.physmem.perBankWrBursts::9 70986 # Per bank write bursts -system.physmem.perBankWrBursts::10 70505 # Per bank write bursts -system.physmem.perBankWrBursts::11 70955 # Per bank write bursts -system.physmem.perBankWrBursts::12 70250 # Per bank write bursts -system.physmem.perBankWrBursts::13 70819 # Per bank write bursts -system.physmem.perBankWrBursts::14 69624 # Per bank write bursts -system.physmem.perBankWrBursts::15 69092 # Per bank write bursts +system.physmem.perBankRdBursts::0 139629 # Per bank write bursts +system.physmem.perBankRdBursts::1 136292 # Per bank write bursts +system.physmem.perBankRdBursts::2 133828 # Per bank write bursts +system.physmem.perBankRdBursts::3 136435 # Per bank write bursts +system.physmem.perBankRdBursts::4 134766 # Per bank write bursts +system.physmem.perBankRdBursts::5 135151 # Per bank write bursts +system.physmem.perBankRdBursts::6 136244 # Per bank write bursts +system.physmem.perBankRdBursts::7 136309 # Per bank write bursts +system.physmem.perBankRdBursts::8 143829 # Per bank write bursts +system.physmem.perBankRdBursts::9 146501 # Per bank write bursts +system.physmem.perBankRdBursts::10 144298 # Per bank write bursts +system.physmem.perBankRdBursts::11 146295 # Per bank write bursts +system.physmem.perBankRdBursts::12 145712 # Per bank write bursts +system.physmem.perBankRdBursts::13 146106 # Per bank write bursts +system.physmem.perBankRdBursts::14 142241 # Per bank write bursts +system.physmem.perBankRdBursts::15 142471 # Per bank write bursts +system.physmem.perBankWrBursts::0 69077 # Per bank write bursts +system.physmem.perBankWrBursts::1 67426 # Per bank write bursts +system.physmem.perBankWrBursts::2 65726 # Per bank write bursts +system.physmem.perBankWrBursts::3 66343 # Per bank write bursts +system.physmem.perBankWrBursts::4 66130 # Per bank write bursts +system.physmem.perBankWrBursts::5 66357 # Per bank write bursts +system.physmem.perBankWrBursts::6 67984 # Per bank write bursts +system.physmem.perBankWrBursts::7 68878 # Per bank write bursts +system.physmem.perBankWrBursts::8 70373 # Per bank write bursts +system.physmem.perBankWrBursts::9 70997 # Per bank write bursts +system.physmem.perBankWrBursts::10 70493 # Per bank write bursts +system.physmem.perBankWrBursts::11 70981 # Per bank write bursts +system.physmem.perBankWrBursts::12 70269 # Per bank write bursts +system.physmem.perBankWrBursts::13 70812 # Per bank write bursts +system.physmem.perBankWrBursts::14 69646 # Per bank write bursts +system.physmem.perBankWrBursts::15 69069 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 533796944500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 533761847000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246734 # Read request sizes (log2) +system.physmem.readPktSize::6 2246694 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100498 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1621551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 445207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 135727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100579 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 445219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 135704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,216 +129,237 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 48879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 49064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 49063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 49078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 49086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 49106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 49088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 49112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 49888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 50325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 51988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 52147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2077673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.074669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.977753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.400722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1659880 79.89% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 227444 10.95% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 69322 3.34% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 37684 1.81% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 24960 1.20% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12074 0.58% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8168 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4452 0.21% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3374 0.16% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2842 0.14% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2038 0.10% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1716 0.08% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1451 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1190 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1071 0.05% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 949 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 909 0.04% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 717 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 676 0.03% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3081 0.15% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 420 0.02% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 289 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 203 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 186 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 219 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 499 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 143 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 125 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 127 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 94 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 128 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 92 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 97 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 82 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 82 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 62 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 59 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 52 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 72 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 47 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 62 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 51 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 51 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 39 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 48 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 40 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 42 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 28 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 34 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 44 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 23 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 29 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 27 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 28 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 28 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 9 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 25 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 18 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 19 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 22 0.00% 99.97% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 49060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 49089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 49071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 49076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 49104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 49085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 49081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 49079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 49128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 49899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 50373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 52016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 52139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see 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0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 12 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 16 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 38 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 13 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 22 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 20 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 37 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 4 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 82 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2077673 # Bytes accessed per row activation -system.physmem.totQLat 32821468000 # Total ticks spent queuing -system.physmem.totMemAccLat 104059554250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11230790000 # Total ticks spent in databus transfers -system.physmem.totBankLat 60007296250 # Total ticks spent accessing banks -system.physmem.avgQLat 14612.27 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26715.53 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7872-7873 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 6 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 88 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2078319 # Bytes accessed per row activation +system.physmem.totQLat 32815970750 # Total ticks spent queuing +system.physmem.totMemAccLat 104054627000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11230535000 # Total ticks spent in databus transfers +system.physmem.totBankLat 60008121250 # Total ticks spent accessing banks +system.physmem.avgQLat 14610.15 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26716.50 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46327.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 131.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 131.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46326.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 269.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 131.96 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 269.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 131.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.35 # Average write queue length when enqueuing -system.physmem.readRowHits 932509 # Number of row buffer hits during reads -system.physmem.writeRowHits 336457 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.57 # Row buffer hit rate for writes -system.physmem.avgGap 159474.14 # Average gap between requests -system.physmem.pageHitRate 37.92 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.98 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 401318817 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420235 # Transaction distribution -system.membus.trans_dist::ReadResp 1420234 # Transaction distribution -system.membus.trans_dist::Writeback 1100498 # Transaction distribution -system.membus.trans_dist::ReadExReq 826499 # Transaction distribution -system.membus.trans_dist::ReadExResp 826499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593965 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593965 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214222784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214222784 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214222784 # Total data (bytes) +system.physmem.avgWrQLen 10.33 # Average write queue length when enqueuing +system.physmem.readRowHits 932061 # Number of row buffer hits during reads +system.physmem.writeRowHits 336288 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.56 # Row buffer hit rate for writes +system.physmem.avgGap 159461.70 # Average gap between requests +system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.96 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 401350114 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420099 # Transaction distribution +system.membus.trans_dist::ReadResp 1420098 # Transaction distribution +system.membus.trans_dist::Writeback 1100579 # Transaction distribution +system.membus.trans_dist::ReadExReq 826595 # Transaction distribution +system.membus.trans_dist::ReadExResp 826595 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593966 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593966 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214225408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214225408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214225408 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12926153000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12926034750 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21084340000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 303451211 # Number of BP lookups -system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174297258 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161770128 # Number of BTB hits +system.cpu.branchPred.lookups 303426723 # Number of BP lookups +system.cpu.branchPred.condPredicted 249665263 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15197446 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174885075 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161766496 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.812779 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17550277 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.498743 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17552924 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 181 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,6 +381,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -382,132 +424,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1067594019 # number of cpu cycles simulated +system.cpu.numCycles 1067523845 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 299164557 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2189663567 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303451211 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179320405 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435777521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88106670 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 164181608 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 55 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289571528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5986152 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 969098859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.499353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.206220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 299169160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2189552617 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303426723 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179319420 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435766349 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88088140 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 164108706 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 249 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289578845 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5989031 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969003000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.499478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206212 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 533321418 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25465587 2.63% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39057125 4.03% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48306210 4.98% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43759030 4.52% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46389880 4.79% 75.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38408230 3.96% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18944401 1.95% 81.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175446978 18.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 533236766 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25461427 2.63% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39064672 4.03% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48308848 4.99% 66.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43759414 4.52% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46393042 4.79% 75.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38404129 3.96% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18940871 1.95% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175433831 18.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 969098859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284238 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.051026 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 331405346 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 142029656 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405372937 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20316462 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69974458 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46022119 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2369134638 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2461 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69974458 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354905741 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70599540 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400539970 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73059040 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2306329085 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 151792 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5017639 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60125136 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282204226 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10649650977 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9763673843 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 969003000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284234 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.051057 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331406137 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 141956827 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405364012 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20318148 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69957876 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46020737 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2369052643 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2441 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69957876 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354906744 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70525275 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17150 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400533325 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73062630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2306235389 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 151230 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5013278 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60135849 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282078057 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10649208068 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9763247621 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 575884296 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 843 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 840 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160951749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624757210 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220789926 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85935761 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70812981 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2202388527 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 863 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018815703 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4014611 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 474721541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1127548434 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 693 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 969098859 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.083189 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906427 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575758127 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 539 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160926093 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624728249 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220785157 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86065935 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71218939 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202289570 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 584 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018746767 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4010968 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474628449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127376318 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 414 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969003000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.083324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906240 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 286260209 29.54% 29.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153575867 15.85% 45.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160890539 16.60% 61.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120276383 12.41% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123547545 12.75% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73803065 7.62% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38319485 3.95% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9898934 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2526832 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 286111139 29.53% 29.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153618591 15.85% 45.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160911412 16.61% 61.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120366979 12.42% 74.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123454210 12.74% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73801369 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38320646 3.95% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9892378 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2526276 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 969098859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969003000 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 899836 3.76% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5555 0.02% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18259038 76.22% 80.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4790984 20.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 901909 3.77% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5511 0.02% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18267438 76.34% 80.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4754077 19.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236944304 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 924745 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236913920 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925199 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -529,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 39 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 6 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587884247 29.12% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193062337 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587869811 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193037777 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018815703 # Type of FU issued -system.cpu.iq.rate 1.890996 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23955413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011866 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5034700006 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2677299944 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957368325 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 522 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042770975 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64606441 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018746767 # Type of FU issued +system.cpu.iq.rate 1.891055 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23928935 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011853 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5034436167 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2677107941 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957305969 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 270 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 526 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042675566 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64599963 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138830441 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271664 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192064 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45942881 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138801480 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 270727 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192405 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45938112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4771033 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4771665 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69974458 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33522833 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1603829 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2202389482 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7882723 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624757210 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220789926 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 801 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 479284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97151 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192064 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8143428 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9602990 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17746418 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988074209 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574028107 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30741494 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69957876 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33460674 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1602950 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202290297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7880065 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624728249 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220785157 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 522 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 477902 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97314 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192405 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8143338 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9598007 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17741345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988017569 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574014855 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30729198 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 92 # number of nop insts executed -system.cpu.iew.exec_refs 764206037 # number of memory reference insts executed -system.cpu.iew.exec_branches 238324356 # Number of branches executed -system.cpu.iew.exec_stores 190177930 # Number of stores executed -system.cpu.iew.exec_rate 1.862201 # Inst execution rate -system.cpu.iew.wb_sent 1965784253 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957368435 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295422958 # num instructions producing a value -system.cpu.iew.wb_consumers 2059236430 # num instructions consuming a value +system.cpu.iew.exec_nop 143 # number of nop insts executed +system.cpu.iew.exec_refs 764181270 # number of memory reference insts executed +system.cpu.iew.exec_branches 238318975 # Number of branches executed +system.cpu.iew.exec_stores 190166415 # Number of stores executed +system.cpu.iew.exec_rate 1.862270 # Inst execution rate +system.cpu.iew.wb_sent 1965726867 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957306072 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295394361 # num instructions producing a value +system.cpu.iew.wb_consumers 2059160488 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833439 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629079 # average fanout of values written-back +system.cpu.iew.wb_rate 1.833501 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629089 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 479415060 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479315418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15200205 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 899124401 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.916391 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718302 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15196786 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 899045124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.916560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718243 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 410581675 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193287424 21.50% 67.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72783200 8.09% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35268105 3.92% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18874620 2.10% 81.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30803459 3.43% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19949403 2.22% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11408599 1.27% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106167916 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 410462230 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193303811 21.50% 67.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72810970 8.10% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35275316 3.92% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18883906 2.10% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30780783 3.42% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19963318 2.22% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11415613 1.27% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106149177 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 899124401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 899045124 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -623,97 +665,98 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106167916 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106149177 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2995444799 # The number of ROB reads -system.cpu.rob.rob_writes 4475102834 # The number of ROB writes -system.cpu.timesIdled 1153332 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98495160 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2995284619 # The number of ROB reads +system.cpu.rob.rob_writes 4474886700 # The number of ROB writes +system.cpu.timesIdled 1153694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98520845 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.691195 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.691195 # CPI: Total CPI of All Threads -system.cpu.ipc 1.446770 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.446770 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956366000 # number of integer regfile reads -system.cpu.int_regfile_writes 1937254103 # number of integer regfile writes -system.cpu.fp_regfile_reads 112 # number of floating regfile reads -system.cpu.fp_regfile_writes 111 # number of floating regfile writes -system.cpu.misc_regfile_reads 737634139 # number of misc regfile reads +system.cpu.cpi 0.691149 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.691149 # CPI: Total CPI of All Threads +system.cpu.ipc 1.446865 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.446865 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956057659 # number of integer regfile reads +system.cpu.int_regfile_writes 1937206435 # number of integer regfile writes +system.cpu.fp_regfile_reads 98 # number of floating regfile reads +system.cpu.fp_regfile_writes 94 # number of floating regfile writes +system.cpu.misc_regfile_reads 737611057 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1604602532 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709031 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3780837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893445 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984242 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22985790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856482496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856532032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856532032 # Total data (bytes) +system.cpu.toL2Bus.throughput 1604912326 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782070 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893493 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986415 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22987965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856591488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856641088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856641088 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10472653342 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10474747083 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1293249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14769367993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14769977492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 20 # number of replacements -system.cpu.icache.tags.tagsinuse 628.438821 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289570320 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 374121.860465 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 19 # number of replacements +system.cpu.icache.tags.tagsinuse 628.273269 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289577640 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 373648.567742 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 754 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 628.273269 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306774 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306774 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 756 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 726 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.368164 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579143830 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579143830 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289570320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289570320 # number of overall hits -system.cpu.icache.overall_hits::total 289570320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1208 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1208 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1208 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1208 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1208 # number of overall misses -system.cpu.icache.overall_misses::total 1208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 83080499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 83080499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 83080499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 83080499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 83080499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 83080499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289571528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289571528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289571528 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289571528 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289571528 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289571528 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 727 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.369141 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 579158465 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579158465 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289577640 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289577640 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289577640 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289577640 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289577640 # number of overall hits +system.cpu.icache.overall_hits::total 289577640 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses +system.cpu.icache.overall_misses::total 1205 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81284498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81284498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81284498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81284498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81284498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81284498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289578845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289578845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289578845 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289578845 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289578845 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289578845 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68775.247517 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68775.247517 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68775.247517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68775.247517 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67456.014938 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67456.014938 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -722,129 +765,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56793251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56793251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56793251 # number of demand (read+write) MSHR miss cycles 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(read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 173878798500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46285250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173832513250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 173878798500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184230 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436505 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436505 # mshr miss rate for ReadExReq accesses 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ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79742.292792 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 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-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2397 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1056 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 635 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1057 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1355914350 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1355914350 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166956698 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1355899932 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1355899932 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 489056209 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489056209 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166956265 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166956265 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656019351 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656019351 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656019351 # number of overall hits -system.cpu.dcache.overall_hits::total 656019351 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11507496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11507496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5629349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5629349 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656012474 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656012474 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656012474 # number of overall hits +system.cpu.dcache.overall_hits::total 656012474 # number of overall hits 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cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307744962906 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307744962906 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 671447805394 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 671447805394 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 671447805394 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 671447805394 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500570149 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500570149 # number of ReadReq accesses(hits+misses) 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(read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 670926085256 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 670926085256 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 670926085256 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500562707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500562707 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673156196 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673156196 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673156196 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673156196 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032618 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032618 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 673148754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673148754 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673148754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673148754 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022987 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022987 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032620 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31605.732688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31605.732688 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54667.948799 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54667.948799 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39181.529937 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39181.529937 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24597243 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3988018 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1212289 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.289917 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.230720 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39152.376435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39152.376435 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24574937 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3988182 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1212192 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65130 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.273139 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.234178 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3780837 # number of writebacks -system.cpu.dcache.writebacks::total 3780837 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3799238 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3799238 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3735904 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3735904 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782070 # number of writebacks +system.cpu.dcache.writebacks::total 3782070 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3797817 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3797817 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3736290 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7535142 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7535142 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7535142 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7535142 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708258 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708258 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893445 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893445 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601703 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601703 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601703 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601703 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198213123757 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 198213123757 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89346986214 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89346986214 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287560109971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 287560109971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287560109971 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 287560109971 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7534107 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7534107 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7534107 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7534107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708681 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708681 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893492 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893492 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602173 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602173 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89373429339 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89373429339 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 287554345347 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 287554345347 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015400 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015400 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25714.386280 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25714.386280 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47187.526553 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47187.526553 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 1a911e7c2..ad0230a84 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 922328096..e972d8df4 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:35:09 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:13:20 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x571a380 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index de1eec5b4..a0198a23d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538200000 # Number of ticks simulated final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2414882 # Simulator instruction rate (inst/s) -host_op_rate 2693979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1346991470 # Simulator tick rate (ticks/s) -host_mem_usage 238968 # Number of bytes of host memory used -host_seconds 639.60 # Real time elapsed on the host +host_inst_rate 2200753 # Simulator instruction rate (inst/s) +host_op_rate 2455102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1227552560 # Simulator tick rate (ticks/s) +host_mem_usage 258852 # Number of bytes of host memory used +host_seconds 701.83 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1723073853 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9731209155 # Th system.membus.data_through_bus 8383808419 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 27330256 # nu system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read +system.cpu.num_int_register_reads 7861285293 # number of times the integer registers were read system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 05924440e..a5a5a4799 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 684ae1ce5..4d71ca666 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:38:44 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:15:41 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5333d00 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 3ce47f2c9..b8a9db006 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1202285 # Simulator instruction rate (inst/s) -host_op_rate 1341761 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1868329144 # Simulator tick rate (ticks/s) -host_mem_usage 247832 # Number of bytes of host memory used -host_seconds 1279.86 # Real time elapsed on the host +host_inst_rate 1176543 # Simulator instruction rate (inst/s) +host_op_rate 1313033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1828326739 # Simulator tick rate (ticks/s) +host_mem_usage 268744 # Number of bytes of host memory used +host_seconds 1307.87 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.5 # La system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 27330256 # nu system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read +system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 69c7d8edb..03d137b4d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 6ec033969..ce396dba2 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:45:59 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:25:13 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5949040 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 @@ -23,4 +22,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 74219948500 because target called exit() +122 123 124 Exiting @ tick 74219931000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 3723ab1c1..a1592fc7b 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.074220 # Number of seconds simulated -sim_ticks 74219948500 # Number of ticks simulated -final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 74219931000 # Number of ticks simulated +final_tick 74219931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133200 # Simulator instruction rate (inst/s) -host_op_rate 145842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57376166 # Simulator tick rate (ticks/s) -host_mem_usage 253176 # Number of bytes of host memory used -host_seconds 1293.57 # Real time elapsed on the host +host_inst_rate 128899 # Simulator instruction rate (inst/s) +host_op_rate 141133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55523526 # Simulator tick rate (ticks/s) +host_mem_usage 273064 # Number of bytes of host memory used +host_seconds 1336.73 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 131072 # Nu system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1765995 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3270712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1765995 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1765995 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1765995 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3270712 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3794 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74219930000 # Total gap between requests +system.physmem.totGap 74219912500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -199,14 +199,14 @@ system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 25203500 # Total ticks spent queuing -system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 25208000 # Total ticks spent queuing +system.physmem.totMemAccLat 100718000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers system.physmem.totBankLat 56540000 # Total ticks spent accessing banks -system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6644.18 # Average queueing delay per DRAM burst system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26546.65 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s @@ -221,10 +221,10 @@ system.physmem.readRowHits 3077 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19562448.60 # Average gap between requests +system.physmem.avgGap 19562443.99 # Average gap between requests system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 3270711 # Throughput (bytes/s) +system.membus.throughput 3270712 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 2723 # Transaction distribution system.membus.trans_dist::ReadResp 2722 # Transaction distribution system.membus.trans_dist::ReadExReq 1071 # Transaction distribution @@ -235,20 +235,41 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 242752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4681000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35532250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94784274 # Number of BP lookups -system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits +system.cpu.branchPred.lookups 94784239 # Number of BP lookups +system.cpu.branchPred.condPredicted 74783977 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6281559 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44678373 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43049971 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 96.355279 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4356641 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -270,6 +291,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -292,100 +334,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148439898 # number of cpu cycles simulated +system.cpu.numCycles 148439863 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39656875 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380179667 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94784239 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47406612 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80370607 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283097 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220794 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6206 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36850851 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1831977 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148240291 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.801605 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68038529 45.90% 45.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5265458 3.55% 49.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540663 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285699 6.94% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8660453 5.84% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545120 4.42% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6246377 4.21% 77.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8002820 5.40% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655172 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 148240291 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups +system.cpu.fetch.rate 2.561170 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45513767 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5886575 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74804066 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203498 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20832385 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327909 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164350 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392779624 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 733803 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20832385 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50900716 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 730751 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603183 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70558259 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4614997 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371307860 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 339068 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661204 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631703204 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1588513521 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506815662 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 333659065 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 13010227 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43012674 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16416368 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5733538 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3666489 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329189946 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 249456447 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 789359 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139503196 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362394637 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148240291 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.682784 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56059626 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22638758 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24824129 16.75% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20343397 13.72% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12534810 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6516110 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4026087 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1116064 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181310 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148240291 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 965209 38.57% 38.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available @@ -405,21 +447,21 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1158969 46.31% 85.11% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194899827 78.13% 78.13% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued @@ -448,84 +490,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38355265 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13948042 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued -system.cpu.iq.rate 1.680523 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested +system.cpu.iq.FU_type_0::total 249456447 # Type of FU issued +system.cpu.iq.rate 1.680522 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2502650 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 646705187 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466563017 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237885267 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 250082678 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 2013206 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163190 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 3771734 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 20832385 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18544 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 886 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329254297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785292 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43012674 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16416368 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 181 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 3889950 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3760088 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650038 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36851914 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6496103 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17196 # number of nop insts executed -system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed -system.cpu.iew.exec_branches 53426072 # Number of branches executed -system.cpu.iew.exec_stores 13648456 # Number of stores executed -system.cpu.iew.exec_rate 1.636760 # Inst execution rate -system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148474078 # num instructions producing a value -system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value +system.cpu.iew.exec_nop 17197 # number of nop insts executed +system.cpu.iew.exec_refs 50500351 # number of memory reference insts executed +system.cpu.iew.exec_branches 53426054 # Number of branches executed +system.cpu.iew.exec_stores 13648437 # Number of stores executed +system.cpu.iew.exec_rate 1.636759 # Inst execution rate +system.cpu.iew.wb_sent 240785488 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239727880 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148473973 # num instructions producing a value +system.cpu.iew.wb_consumers 267261246 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle +system.cpu.iew.wb_rate 1.614983 # insts written-back per cycle system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583409 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6128231 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127407906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.185453 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57701601 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696921 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13777775 10.81% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7640604 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4387783 3.44% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321955 1.04% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1703214 1.34% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1308007 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7870046 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127407906 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,99 +578,99 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7870046 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448787434 # The number of ROB reads -system.cpu.rob.rob_writes 679451113 # The number of ROB writes -system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448786959 # The number of ROB reads +system.cpu.rob.rob_writes 679450685 # The number of ROB writes +system.cpu.timesIdled 2806 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199572 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads -system.cpu.int_regfile_writes 384871783 # number of integer regfile writes +system.cpu.ipc 1.160760 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160760 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079416198 # number of integer regfile reads +system.cpu.int_regfile_writes 384871537 # number of integer regfile writes system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes -system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads +system.cpu.misc_regfile_reads 64870078 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution +system.cpu.toL2Bus.throughput 5170363 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8253 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11975 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 383744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383744 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3016500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6553746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2394 # number of replacements -system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2395 # number of replacements +system.cpu.icache.tags.tagsinuse 1347.740461 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36845513 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4126 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8930.080708 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740461 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73705913 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73705913 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits -system.cpu.icache.overall_hits::total 36845557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses -system.cpu.icache.overall_misses::total 5337 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 73705828 # Number of tag accesses +system.cpu.icache.tags.data_accesses 73705828 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 36845513 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845513 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845513 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845513 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845513 # number of overall hits +system.cpu.icache.overall_hits::total 36845513 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5338 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5338 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5338 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5338 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5338 # number of overall misses +system.cpu.icache.overall_misses::total 5338 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 225943745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 225943745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 225943745 # number of demand (read+write) miss cycles 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rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42327.415699 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42327.415699 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42327.415699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42327.415699 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -643,40 +685,40 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 1211 system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4127 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4127 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4127 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4127 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4127 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4127 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168102254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168102254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168102254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168102254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168102254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168102254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40732.312576 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40732.312576 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1967.449595 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2163 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. 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0.016384 # Average percentage of cache occupancy @@ -688,21 +730,21 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 604 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1970 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083374 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51779 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51779 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 51787 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51787 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2074 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits 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-system.cpu.l2cache.overall_hits::total 2169 # number of overall hits +system.cpu.l2cache.overall_hits::total 2170 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2053 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 2738 # number of ReadReq misses @@ -714,52 +756,52 @@ system.cpu.l2cache.demand_misses::total 3809 # nu system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses system.cpu.l2cache.overall_misses::total 3809 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51387250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 194615500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 143228250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 123679500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266907750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 143228250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 123679500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266907750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4127 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4900 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4127 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5978 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4126 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5979 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4127 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5978 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497576 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 5979 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497456 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.558890 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.558776 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497456 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.637063 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497456 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::total 0.637063 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.343400 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75017.883212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71079.437546 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70072.919401 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70072.919401 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -788,47 +830,47 @@ system.cpu.l2cache.demand_mshr_misses::total 3794 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117257250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42300250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159557500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117257250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101142000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218399250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117257250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101142000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218399250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555714 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.634554 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.634554 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57226.573939 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62760.014837 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58596.217407 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1406.103051 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46786126 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25262.487041 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103051 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1795 # Occupied blocks per task id @@ -838,52 +880,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.438232 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93593418 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 93593418 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 93593354 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 93593354 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34384681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34384681 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits -system.cpu.dcache.overall_hits::total 46741275 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 46741245 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46741245 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46741245 # number of overall hits +system.cpu.dcache.overall_hits::total 46741245 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1900 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1900 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses -system.cpu.dcache.overall_misses::total 9625 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9623 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9623 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9623 # number of overall misses +system.cpu.dcache.overall_misses::total 9623 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121712227 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121712227 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 587335973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 587335973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 587335973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 587335973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34386581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34386581 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46750868 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46750868 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46750868 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46750868 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses @@ -894,16 +936,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64059.066842 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64059.066842 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61034.601787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61034.601787 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -914,16 +956,16 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7771 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7771 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7771 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7771 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses @@ -932,14 +974,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1852 system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53118011 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53118011 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126511509 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126511509 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126511509 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126511509 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -948,14 +990,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68627.921189 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68627.921189 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 0b27d47af..8a9c45524 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 3a7a72087..cd4551b05 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:00:14 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:37:39 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5fbc6c0 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index c33d29231..0803f6f8f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106766000 # Number of ticks simulated final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2018881 # Simulator instruction rate (inst/s) -host_op_rate 2210479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1208004529 # Simulator tick rate (ticks/s) -host_mem_usage 241364 # Number of bytes of host memory used -host_seconds 85.35 # Real time elapsed on the host +host_inst_rate 1878588 # Simulator instruction rate (inst/s) +host_op_rate 2056872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1124059947 # Simulator tick rate (ticks/s) +host_mem_usage 262308 # Number of bytes of host memory used +host_seconds 91.73 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 188670891 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 8876496088 # Th system.membus.data_through_bus 915226805 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 3545028 # nu system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read +system.cpu.num_int_register_reads 815315678 # number of times the integer registers were read system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index a68b7deda..c1d62d90a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 50f61b81e..aba76e9d8 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:01:50 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:39:21 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5d0ed00 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index daccb0e4d..c455c2ee7 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu sim_ticks 232072304000 # Number of ticks simulated final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1248624 # Simulator instruction rate (inst/s) -host_op_rate 1367377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1686259354 # Simulator tick rate (ticks/s) -host_mem_usage 250108 # Number of bytes of host memory used -host_seconds 137.63 # Real time elapsed on the host +host_inst_rate 1152638 # Simulator instruction rate (inst/s) +host_op_rate 1262262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1556630640 # Simulator tick rate (ticks/s) +host_mem_usage 271024 # Number of bytes of host memory used +host_seconds 149.09 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 3545028 # nu system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read +system.cpu.num_int_register_reads 904571312 # number of times the integer registers were read system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written |