diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/se | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/se')
42 files changed, 17023 insertions, 16006 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index a4eaa28e3..52746e018 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061494 # Nu sim_ticks 61493732000 # Number of ticks simulated final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 280016 # Simulator instruction rate (inst/s) -host_op_rate 281410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 190051649 # Simulator tick rate (ticks/s) -host_mem_usage 385752 # Number of bytes of host memory used -host_seconds 323.56 # Real time elapsed on the host +host_inst_rate 271090 # Simulator instruction rate (inst/s) +host_op_rate 272440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 183993432 # Simulator tick rate (ticks/s) +host_mem_usage 445016 # Number of bytes of host memory used +host_seconds 334.22 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # By system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation -system.physmem.totQLat 73246500 # Total ticks spent queuing -system.physmem.totMemAccLat 365277750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 73247750 # Total ticks spent queuing +system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.83 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.83 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 90.09 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 3948227.51 # Average gap between requests system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 56242943250 # Time in different power states -system.physmem.memoryStateTime::REF 2053220000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 3193793750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6320160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 5261760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3448500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2871000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 63663600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 57462600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2490497865 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2514078765 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34708310250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 34687625250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41288338695 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41283397695 # Total energy per rank (pJ) -system.physmem.averagePower::0 671.483256 # Core power per rank (mW) -system.physmem.averagePower::1 671.402899 # Core power per rank (mW) +system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.483541 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.402933 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20789429 # Number of BP lookups system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 98.812096 # BT system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -383,14 +420,14 @@ system.cpu.dcache.demand_misses::cpu.inst 988866 # n system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910311744 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11910311744 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345697500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2345697500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14256009244 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14256009244 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14256009244 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14256009244 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 14256024494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) @@ -411,14 +448,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14416.522809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14416.522809 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.315542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.478920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,14 +482,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958869756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958869756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333434750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333434750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292304506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11292304506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292304506 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11292304506 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses @@ -461,22 +498,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.411179 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.411179 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id @@ -556,13 +593,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10247.121792 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236502 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885294 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy @@ -593,14 +630,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 15583 # system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71718500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71718500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958069250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 958069250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1029787750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1029787750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1029787750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1029787750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71704250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958084250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1029788500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1029788500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) @@ -619,14 +656,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,14 +686,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58344750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58344750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774500250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774500250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832845000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 832845000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832845000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 832845000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses @@ -665,14 +702,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution @@ -705,7 +742,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # La system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428672494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1031 # Transaction distribution @@ -728,7 +765,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 15575 # Request fanout histogram system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 146202000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 3f4662e45..ea993d96c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057713 # Number of seconds simulated -sim_ticks 57712782000 # Number of ticks simulated -final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057719 # Number of seconds simulated +sim_ticks 57719377000 # Number of ticks simulated +final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133110 # Simulator instruction rate (inst/s) -host_op_rate 133773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84801314 # Simulator tick rate (ticks/s) -host_mem_usage 388280 # Number of bytes of host memory used -host_seconds 680.56 # Real time elapsed on the host +host_inst_rate 125223 # Simulator instruction rate (inst/s) +host_op_rate 125847 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79786059 # Simulator tick rate (ticks/s) +host_mem_usage 443544 # Number of bytes of host memory used +host_seconds 723.43 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory -system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory -system.physmem.bytes_written::total 73600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory -system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 17490 # Number of read requests accepted -system.physmem.writeReqs 1150 # Number of write requests accepted -system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory +system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory +system.physmem.bytes_written::total 19776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory +system.physmem.num_writes::total 309 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15872 # Number of read requests accepted +system.physmem.writeReqs 309 # Number of write requests accepted +system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue +system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1094 # Per bank write bursts -system.physmem.perBankRdBursts::1 953 # Per bank write bursts -system.physmem.perBankRdBursts::2 1083 # Per bank write bursts -system.physmem.perBankRdBursts::3 1113 # Per bank write bursts -system.physmem.perBankRdBursts::4 1125 # Per bank write bursts -system.physmem.perBankRdBursts::5 1235 # Per bank write bursts -system.physmem.perBankRdBursts::6 1314 # Per bank write bursts -system.physmem.perBankRdBursts::7 1243 # Per bank write bursts -system.physmem.perBankRdBursts::8 1060 # Per bank write bursts +system.physmem.perBankRdBursts::0 999 # Per bank write bursts +system.physmem.perBankRdBursts::1 876 # Per bank write bursts +system.physmem.perBankRdBursts::2 956 # Per bank write bursts +system.physmem.perBankRdBursts::3 1023 # Per bank write bursts +system.physmem.perBankRdBursts::4 1064 # Per bank write bursts +system.physmem.perBankRdBursts::5 1127 # Per bank write bursts +system.physmem.perBankRdBursts::6 1115 # Per bank write bursts +system.physmem.perBankRdBursts::7 1101 # Per bank write bursts +system.physmem.perBankRdBursts::8 1033 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 1021 # Per bank write bursts -system.physmem.perBankRdBursts::11 923 # Per bank write bursts -system.physmem.perBankRdBursts::12 921 # Per bank write bursts -system.physmem.perBankRdBursts::13 987 # Per bank write bursts -system.physmem.perBankRdBursts::14 1105 # Per bank write bursts -system.physmem.perBankRdBursts::15 1049 # Per bank write bursts -system.physmem.perBankWrBursts::0 72 # Per bank write bursts +system.physmem.perBankRdBursts::10 937 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 910 # Per bank write bursts +system.physmem.perBankRdBursts::13 886 # Per bank write bursts +system.physmem.perBankRdBursts::14 919 # Per bank write bursts +system.physmem.perBankRdBursts::15 912 # Per bank write bursts +system.physmem.perBankWrBursts::0 23 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 62 # Per bank write bursts -system.physmem.perBankWrBursts::3 19 # Per bank write bursts -system.physmem.perBankWrBursts::4 14 # Per bank write bursts -system.physmem.perBankWrBursts::5 111 # Per bank write bursts -system.physmem.perBankWrBursts::6 193 # Per bank write bursts -system.physmem.perBankWrBursts::7 122 # Per bank write bursts -system.physmem.perBankWrBursts::8 49 # Per bank write bursts +system.physmem.perBankWrBursts::2 4 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 9 # Per bank write bursts +system.physmem.perBankWrBursts::5 29 # Per bank write bursts +system.physmem.perBankWrBursts::6 62 # Per bank write bursts +system.physmem.perBankWrBursts::7 30 # Per bank write bursts +system.physmem.perBankWrBursts::8 15 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 68 # Per bank write bursts -system.physmem.perBankWrBursts::11 20 # Per bank write bursts -system.physmem.perBankWrBursts::12 15 # Per bank write bursts -system.physmem.perBankWrBursts::13 94 # Per bank write bursts -system.physmem.perBankWrBursts::14 168 # Per bank write bursts -system.physmem.perBankWrBursts::15 110 # Per bank write bursts +system.physmem.perBankWrBursts::10 10 # Per bank write bursts +system.physmem.perBankWrBursts::11 1 # Per bank write bursts +system.physmem.perBankWrBursts::12 9 # Per bank write bursts +system.physmem.perBankWrBursts::13 27 # Per bank write bursts +system.physmem.perBankWrBursts::14 48 # Per bank write bursts +system.physmem.perBankWrBursts::15 21 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57712604500 # Total gap between requests +system.physmem.totGap 57719226000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 17490 # Read request sizes (log2) +system.physmem.readPktSize::6 15872 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1150 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,118 +197,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads -system.physmem.totQLat 228948216 # Total ticks spent queuing -system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads +system.physmem.totQLat 179464908 # Total ticks spent queuing +system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.16 # Data bus utilization in percentage -system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing -system.physmem.readRowHits 14950 # Number of row buffer hits during reads -system.physmem.writeRowHits 375 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes -system.physmem.avgGap 3096169.77 # Average gap between requests -system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states -system.physmem.memoryStateTime::REF 1927120000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 11854080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 10636920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 6468000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 5803875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 71299800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 62602800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3842640 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3395520 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2993861160 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3031288785 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 32001000000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 31968168750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 38857772400 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 38851343370 # Total energy per rank (pJ) -system.physmem.averagePower::0 673.305017 # Core power per rank (mW) -system.physmem.averagePower::1 673.193618 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 17158 # Transaction distribution -system.membus.trans_dist::ReadResp 17158 # Transaction distribution -system.membus.trans_dist::Writeback 1150 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 332 # Transaction distribution -system.membus.trans_dist::ReadExResp 332 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 18642 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18642 # Request fanout histogram -system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 28272297 # Number of BP lookups -system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing +system.physmem.readRowHits 14166 # Number of row buffer hits during reads +system.physmem.writeRowHits 92 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes +system.physmem.avgGap 3567098.82 # Average gap between requests +system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.607894 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states +system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.433104 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states +system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 28271166 # Number of BP lookups +system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -330,6 +316,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -351,6 +345,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -372,6 +374,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -394,83 +404,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 115425565 # number of cpu cycles simulated +system.cpu.numCycles 115438755 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679445 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -478,9 +488,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available @@ -509,12 +519,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued @@ -537,90 +547,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued -system.cpu.iq.rate 0.878733 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued +system.cpu.iq.rate 0.878644 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12666 # number of nop insts executed -system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed -system.cpu.iew.exec_branches 20629033 # Number of branches executed -system.cpu.iew.exec_stores 4918889 # Number of stores executed -system.cpu.iew.exec_rate 0.867621 # Inst execution rate -system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59710820 # num instructions producing a value -system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value +system.cpu.iew.exec_nop 12667 # number of nop insts executed +system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed +system.cpu.iew.exec_branches 20629236 # Number of branches executed +system.cpu.iew.exec_stores 4918943 # Number of stores executed +system.cpu.iew.exec_rate 0.867532 # Inst execution rate +system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59706662 # num instructions producing a value +system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back +system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -666,396 +676,79 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction -system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 217038076 # The number of ROB reads -system.cpu.rob.rob_writes 219583065 # The number of ROB writes -system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 217026090 # The number of ROB reads +system.cpu.rob.rob_writes 219584249 # The number of ROB writes +system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads -system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108123923 # number of integer regfile reads -system.cpu.int_regfile_writes 58738896 # number of integer regfile writes +system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads +system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108125012 # number of integer regfile reads +system.cpu.int_regfile_writes 58739124 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 100 # number of floating regfile writes -system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads -system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes -system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads +system.cpu.fp_regfile_writes 99 # number of floating regfile writes +system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads +system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes +system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 28370 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 456 # number of replacements -system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits -system.cpu.icache.overall_hits::total 32315555 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses -system.cpu.icache.overall_misses::total 1024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 1672 # number of replacements -system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10807.797190 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 104.008842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 299.224972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1347.657528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.659656 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006348 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.018263 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082254 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.766522 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1557 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1370 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 12200 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.095032 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.872864 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 174560305 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 174560305 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 753 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5260483 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5261236 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 5407164 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 5407164 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224791 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224791 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 753 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5485274 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5486027 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 753 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5485274 # number of overall hits -system.cpu.l2cache.overall_hits::total 5486027 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 993 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1156 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 496 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 496 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1489 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1652 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1489 # number of overall misses -system.cpu.l2cache.overall_misses::total 1652 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12439500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59393247 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71832747 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31513998 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 31513998 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12439500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 90907245 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 103346745 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12439500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 90907245 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 103346745 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 916 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 5261476 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5262392 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 5407164 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 5407164 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 225287 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 225287 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 916 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5486763 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5487679 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 916 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5486763 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5487679 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177948 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000189 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000220 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002202 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002202 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177948 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000271 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000301 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177948 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000271 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000301 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76315.950920 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59811.930514 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62139.054498 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63536.286290 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63536.286290 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62558.562349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62558.562349 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 50 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16.400000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1150 # number of writebacks -system.cpu.l2cache.writebacks::total 1150 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 256 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 418 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 442 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 418 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 442 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 139 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26554 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10286000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 72273751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 5486251 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5486247 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits -system.cpu.dcache.overall_hits::total 18263549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits +system.cpu.dcache.overall_hits::total 18263472 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses -system.cpu.dcache.overall_misses::total 9970085 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses +system.cpu.dcache.overall_misses::total 9970594 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) @@ -1064,92 +757,452 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks -system.cpu.dcache.writebacks::total 5407164 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks +system.cpu.dcache.writebacks::total 5460017 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154868 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4483830 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4483830 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4483830 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4483830 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263967 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5263967 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222789 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222789 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194331 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.194331 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7256.749186 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7256.749186 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9715.487663 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9715.487663 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50100 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50100 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7356.585936 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7356.585936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 447 # number of replacements +system.cpu.icache.tags.tagsinuse 428.924531 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32314402 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35667.110375 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 64631998 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64631998 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32314402 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32314402 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32314402 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32314402 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32314402 # number of overall hits +system.cpu.icache.overall_hits::total 32314402 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1144 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1144 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 214 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1059 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 21606 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36534500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16113750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52648250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 777111161 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 22591778 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 22591778 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36534500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 38705528 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 75240028 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36534500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 38705528 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 852351189 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 22341 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 15531 # Transaction distribution +system.membus.trans_dist::ReadResp 15531 # Transaction distribution +system.membus.trans_dist::Writeback 309 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 341 # Transaction distribution +system.membus.trans_dist::ReadExResp 341 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 16183 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 16183 # Request fanout histogram +system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 0aa02b40d..16d507b60 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000000 # Number of ticks simulated final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2068738 # Simulator instruction rate (inst/s) -host_op_rate 2079040 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1236208278 # Simulator tick rate (ticks/s) -host_mem_usage 428768 # Number of bytes of host memory used -host_seconds 43.80 # Real time elapsed on the host +host_inst_rate 1669323 # Simulator instruction rate (inst/s) +host_op_rate 1677636 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 997531404 # Simulator tick rate (ticks/s) +host_mem_usage 433488 # Number of bytes of host memory used +host_seconds 54.28 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 349238802 # Wr system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 130287905 # Transaction distribution -system.membus.trans_dist::ReadResp 130291792 # Transaction distribution -system.membus.trans_dist::WriteReq 4734981 # Transaction distribution -system.membus.trans_dist::WriteResp 4734981 # Transaction distribution -system.membus.trans_dist::SoftPFReq 510 # Transaction distribution -system.membus.trans_dist::SoftPFResp 510 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 135031170 # Request fanout histogram -system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 135031170 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction +system.membus.trans_dist::ReadReq 130287905 # Transaction distribution +system.membus.trans_dist::ReadResp 130291792 # Transaction distribution +system.membus.trans_dist::WriteReq 4734981 # Transaction distribution +system.membus.trans_dist::WriteResp 4734981 # Transaction distribution +system.membus.trans_dist::SoftPFReq 510 # Transaction distribution +system.membus.trans_dist::SoftPFResp 510 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 135031170 # Request fanout histogram +system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 135031170 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index b163f38c3..3f9742fb4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147041 # Nu sim_ticks 147041218000 # Number of ticks simulated final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130471 # Simulator instruction rate (inst/s) -host_op_rate 1136089 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1835190843 # Simulator tick rate (ticks/s) -host_mem_usage 438268 # Number of bytes of host memory used -host_seconds 80.12 # Real time elapsed on the host +host_inst_rate 1114927 # Simulator instruction rate (inst/s) +host_op_rate 1120467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1809956176 # Simulator tick rate (ticks/s) +host_mem_usage 442716 # Number of bytes of host memory used +host_seconds 81.24 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 251576 # In system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 792 # Transaction distribution -system.membus.trans_dist::ReadResp 792 # Transaction distribution -system.membus.trans_dist::ReadExReq 14548 # Transaction distribution -system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15340 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,144 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits +system.cpu.dcache.overall_hits::total 26245827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses +system.cpu.dcache.overall_misses::total 946799 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks +system.cpu.dcache.writebacks::total 942334 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. @@ -429,144 +576,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits -system.cpu.dcache.overall_hits::total 26245827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses -system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks -system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution @@ -600,5 +609,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 898500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 792 # Transaction distribution +system.membus.trans_dist::ReadResp 792 # Transaction distribution +system.membus.trans_dist::ReadExReq 14548 # Transaction distribution +system.membus.trans_dist::ReadExResp 14548 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15340 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15340 # Request fanout histogram +system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index afe4ad98b..a20619a99 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061857 # Nu sim_ticks 61857343500 # Number of ticks simulated final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117254 # Simulator instruction rate (inst/s) -host_op_rate 206466 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45908562 # Simulator tick rate (ticks/s) -host_mem_usage 395064 # Number of bytes of host memory used -host_seconds 1347.40 # Real time elapsed on the host +host_inst_rate 113051 # Simulator instruction rate (inst/s) +host_op_rate 199065 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44263102 # Simulator tick rate (ticks/s) +host_mem_usage 453712 # Number of bytes of host memory used +host_seconds 1397.49 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Wr system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads -system.physmem.totQLat 131010750 # Total ticks spent queuing -system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 130999000 # Total ticks spent queuing +system.physmem.totMemAccLat 700455250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4313.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23063.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s @@ -244,56 +244,34 @@ system.physmem.readRowHitRate 91.19 # Ro system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes system.physmem.avgGap 2017525.41 # Average gap between requests system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 55617527500 # Time in different power states -system.physmem.memoryStateTime::REF 2065440000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 10939320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 9623880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 5968875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 5251125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 122226000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 114246600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 1095120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 51840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2776037940 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2977033050 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34677417000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 34501105500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41633684895 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41647312635 # Total energy per rank (pJ) -system.physmem.averagePower::0 673.093577 # Core power per rank (mW) -system.physmem.averagePower::1 673.313897 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1465 # Transaction distribution -system.membus.trans_dist::ReadResp 1462 # Transaction distribution -system.membus.trans_dist::Writeback 197 # Transaction distribution -system.membus.trans_dist::ReadExReq 28998 # Transaction distribution -system.membus.trans_dist::ReadExResp 28998 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30660 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30660 # Request fanout histogram -system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 10939320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5968875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1095120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2776043070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34677412500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41633685525 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.093587 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57673269750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2115534000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 9623880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5251125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114246600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2977027920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34501101750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41647303755 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.313903 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57380456750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2409426750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 37414357 # Number of BP lookups system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect @@ -303,16 +281,17 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 123714688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28240184 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 28240185 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94568947 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 94568946 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1664995 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps @@ -339,22 +318,22 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13285380 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63221157 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 13285381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63221156 # Number of cycles decode is blocked system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18592313 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 18592314 # Number of cycles rename is idle system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54481539 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 54481538 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48119118 # Number of times rename has blocked due to LQ full +system.cpu.rename.LQFullEvents 48119117 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made @@ -380,21 +359,21 @@ system.cpu.iq.issued_per_cycle::samples 123656373 # Nu system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30107103 24.35% 24.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30107102 24.35% 24.35% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16727631 13.53% 53.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16727632 13.53% 53.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16031842 12.96% 80.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12684149 10.26% 90.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5762402 4.66% 95.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4173790 3.38% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1554838 1.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16031841 12.96% 80.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12684150 10.26% 90.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5762404 4.66% 95.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4173789 3.38% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1554837 1.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 316998 7.53% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 316999 7.53% 7.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available @@ -463,17 +442,17 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued system.cpu.iq.rate 2.489411 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4211171 # FU busy when requested +system.cpu.iq.fu_busy_cnt 4211172 # FU busy when requested system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 743874544 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 743874545 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 312154273 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 312154274 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58255906 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 58255905 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed @@ -509,8 +488,8 @@ system.cpu.iew.exec_stores 33824606 # Nu system.cpu.iew.exec_rate 2.480687 # Inst execution rate system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231632885 # num instructions producing a value -system.cpu.iew.wb_consumers 336126878 # num instructions consuming a value +system.cpu.iew.wb_producers 231632886 # num instructions producing a value +system.cpu.iew.wb_consumers 336126880 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back @@ -522,12 +501,12 @@ system.cpu.commit.committed_per_cycle::samples 117208008 system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52857680 45.10% 45.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52857679 45.10% 45.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10970810 9.36% 68.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8748486 7.46% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10970811 9.36% 68.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8748487 7.46% 75.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1731777 1.48% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1731776 1.48% 78.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle @@ -600,37 +579,121 @@ system.cpu.cc_regfile_reads 107699117 # nu system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121417500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 2072433 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68459745 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.968355 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 144502465 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 144502465 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37113882 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37113882 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68459745 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68459745 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68459745 # number of overall hits +system.cpu.dcache.overall_hits::total 68459745 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses +system.cpu.dcache.overall_misses::total 2753223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861027000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31861027000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2765155494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34626182494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34626182494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34626182494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34626182494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39773216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39773216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 71212968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 71212968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 71212968 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 71212968 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.829411 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.829411 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.325437 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.325437 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12576.599314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12576.599314 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks +system.cpu.dcache.writebacks::total 2066654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524097244 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24524097244 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524097244 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24524097244 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.913780 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.913780 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.061317 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.061317 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 62 # number of replacements system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. @@ -660,12 +723,12 @@ system.cpu.icache.demand_misses::cpu.inst 1347 # n system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses system.cpu.icache.overall_misses::total 1347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 92883749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 92883749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 92883749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 92883749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 92883749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 92883749 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 92877749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 92877749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 92877749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 92877749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 92877749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 92877749 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses @@ -678,12 +741,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68956.012621 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68956.012621 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68951.558278 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68951.558278 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68951.558278 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68951.558278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68951.558278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68951.558278 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -704,32 +767,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1026 system.cpu.icache.demand_mshr_misses::total 1026 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1026 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72336999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 72336999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72336999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 72336999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72336999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 72336999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72330999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 72330999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72330999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 72330999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72330999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 72330999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70503.897661 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70503.897661 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70498.049708 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70498.049708 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70498.049708 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70498.049708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70498.049708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70498.049708 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 515 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20693.420536 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20693.420547 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4029533 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30444 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.358856 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319871 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319882 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.987127 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 249.113538 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.603098 # Average percentage of cache occupancy @@ -769,17 +832,17 @@ system.cpu.l2cache.demand_misses::total 30463 # nu system.cpu.l2cache.overall_misses::cpu.inst 1010 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29453 # number of overall misses system.cpu.l2cache.overall_misses::total 30463 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71141750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31680000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 102821750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1901914500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 71141750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1933594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2004736250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 71141750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1933594500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2004736250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71135750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31674000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 102809750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1901914750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 71135750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1933588750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2004724500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 71135750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1933588750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2004724500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1026 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1994467 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1995493 # number of ReadReq accesses(hits+misses) @@ -804,17 +867,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014663 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984405 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014184 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014663 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70437.376238 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69626.373626 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70185.494881 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.781916 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.781916 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65808.891114 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65808.891114 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70431.435644 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69613.186813 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70177.303754 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.790537 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.790537 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70431.435644 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65649.976233 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65808.505400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70431.435644 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65649.976233 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65808.505400 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -836,17 +899,17 @@ system.cpu.l2cache.demand_mshr_misses::total 30463 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58482750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26096500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84579250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58482750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556138500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1614621250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58482750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556138500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1614621250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58476750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26090500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84567250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58476750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556132750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1614609500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58476750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556132750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1614609500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses @@ -858,132 +921,74 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57897.772277 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57341.758242 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57725.085324 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.716463 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.716463 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072433 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68459744 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.968354 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144502463 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144502463 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37113881 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37113881 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68459744 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68459744 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68459744 # number of overall hits -system.cpu.dcache.overall_hits::total 68459744 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses -system.cpu.dcache.overall_misses::total 2753223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861058000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31861058000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155744 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2765155744 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34626213744 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34626213744 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34626213744 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34626213744 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39773215 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39773215 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71212967 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71212967 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71212967 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71212967 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12576.610665 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12576.610665 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks -system.cpu.dcache.writebacks::total 2066654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009130500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009130500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524102994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24524102994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524102994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24524102994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3121417250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1465 # Transaction distribution +system.membus.trans_dist::ReadResp 1462 # Transaction distribution +system.membus.trans_dist::Writeback 197 # Transaction distribution +system.membus.trans_dist::ReadExReq 28998 # Transaction distribution +system.membus.trans_dist::ReadExResp 28998 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30660 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30660 # Request fanout histogram +system.membus.reqLayer0.occupancy 43499500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 291787500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index f1692fa7b..93f93a6a3 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.411003 # Number of seconds simulated -sim_ticks 411003011000 # Number of ticks simulated -final_tick 411003011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410940 # Number of seconds simulated +sim_ticks 410940483000 # Number of ticks simulated +final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279515 # Simulator instruction rate (inst/s) -host_op_rate 279515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187744969 # Simulator tick rate (ticks/s) -host_mem_usage 239248 # Number of bytes of host memory used -host_seconds 2189.16 # Real time elapsed on the host +host_inst_rate 339016 # Simulator instruction rate (inst/s) +host_op_rate 339016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 227676015 # Simulator tick rate (ticks/s) +host_mem_usage 297088 # Number of bytes of host memory used +host_seconds 1804.94 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24320320 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724480 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380005 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292570 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59173094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59173094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 415919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 415919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45558012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45558012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45558012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59173094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104731106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380005 # Number of read requests accepted -system.physmem.writeReqs 292570 # Number of write requests accepted -system.physmem.readBursts 380005 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292570 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24297088 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23232 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 363 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59182721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59182721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380009 # Number of read requests accepted +system.physmem.writeReqs 292569 # Number of write requests accepted +system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292569 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24297024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23737 # Per bank write bursts -system.physmem.perBankRdBursts::1 23219 # Per bank write bursts -system.physmem.perBankRdBursts::2 23515 # Per bank write bursts -system.physmem.perBankRdBursts::3 24536 # Per bank write bursts -system.physmem.perBankRdBursts::4 25458 # Per bank write bursts -system.physmem.perBankRdBursts::5 23589 # Per bank write bursts -system.physmem.perBankRdBursts::6 23674 # Per bank write bursts -system.physmem.perBankRdBursts::7 23973 # Per bank write bursts -system.physmem.perBankRdBursts::8 23176 # Per bank write bursts -system.physmem.perBankRdBursts::9 23944 # Per bank write bursts -system.physmem.perBankRdBursts::10 24674 # Per bank write bursts -system.physmem.perBankRdBursts::11 22747 # Per bank write bursts -system.physmem.perBankRdBursts::12 23719 # Per bank write bursts -system.physmem.perBankRdBursts::13 24413 # Per bank write bursts -system.physmem.perBankRdBursts::14 22804 # Per bank write bursts -system.physmem.perBankRdBursts::15 22464 # Per bank write bursts +system.physmem.perBankRdBursts::0 23736 # Per bank write bursts +system.physmem.perBankRdBursts::1 23216 # Per bank write bursts +system.physmem.perBankRdBursts::2 23510 # Per bank write bursts +system.physmem.perBankRdBursts::3 24529 # Per bank write bursts +system.physmem.perBankRdBursts::4 25457 # Per bank write bursts +system.physmem.perBankRdBursts::5 23594 # Per bank write bursts +system.physmem.perBankRdBursts::6 23677 # Per bank write bursts +system.physmem.perBankRdBursts::7 23981 # Per bank write bursts +system.physmem.perBankRdBursts::8 23173 # Per bank write bursts +system.physmem.perBankRdBursts::9 23945 # Per bank write bursts +system.physmem.perBankRdBursts::10 24675 # Per bank write bursts +system.physmem.perBankRdBursts::11 22741 # Per bank write bursts +system.physmem.perBankRdBursts::12 23723 # Per bank write bursts +system.physmem.perBankRdBursts::13 24409 # Per bank write bursts +system.physmem.perBankRdBursts::14 22807 # Per bank write bursts +system.physmem.perBankRdBursts::15 22468 # Per bank write bursts system.physmem.perBankWrBursts::0 17754 # Per bank write bursts system.physmem.perBankWrBursts::1 17431 # Per bank write bursts -system.physmem.perBankWrBursts::2 17902 # Per bank write bursts +system.physmem.perBankWrBursts::2 17901 # Per bank write bursts system.physmem.perBankWrBursts::3 18773 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18543 # Per bank write bursts -system.physmem.perBankWrBursts::6 18682 # Per bank write bursts -system.physmem.perBankWrBursts::7 18577 # Per bank write bursts -system.physmem.perBankWrBursts::8 18349 # Per bank write bursts +system.physmem.perBankWrBursts::6 18677 # Per bank write bursts +system.physmem.perBankWrBursts::7 18574 # Per bank write bursts +system.physmem.perBankWrBursts::8 18352 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts system.physmem.perBankWrBursts::10 19127 # Per bank write bursts -system.physmem.perBankWrBursts::11 17965 # Per bank write bursts +system.physmem.perBankWrBursts::11 17966 # Per bank write bursts system.physmem.perBankWrBursts::12 18224 # Per bank write bursts -system.physmem.perBankWrBursts::13 18693 # Per bank write bursts +system.physmem.perBankWrBursts::13 18695 # Per bank write bursts system.physmem.perBankWrBursts::14 17148 # Per bank write bursts system.physmem.perBankWrBursts::15 17103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 411002929500 # Total gap between requests +system.physmem.totGap 410940401000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380005 # Read request sizes (log2) +system.physmem.readPktSize::6 380009 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292570 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292569 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,42 +140,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -189,123 +189,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 141657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.679790 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.908631 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.510648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50805 35.86% 35.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38362 27.08% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12861 9.08% 72.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8208 5.79% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5905 4.17% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3832 2.71% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2875 2.03% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2523 1.78% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16286 11.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141657 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17265 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.988184 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 229.046433 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17255 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142331 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.240383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.797095 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.472154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51326 36.06% 36.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38738 27.22% 63.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13057 9.17% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7891 5.54% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5698 4.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3672 2.58% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3107 2.18% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2648 1.86% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16194 11.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142331 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17261 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.992932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.052387 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17249 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17265 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17265 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.944454 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.865388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.133478 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17065 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 148 0.86% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.16% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 9 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17265 # Writes before turning the bus around for reads -system.physmem.totQLat 4080991250 # Total ticks spent queuing -system.physmem.totMemAccLat 11199278750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10749.58 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17261 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17261 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.948207 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.879580 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.601828 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17058 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 154 0.89% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17261 # Writes before turning the bus around for reads +system.physmem.totQLat 4019056000 # Total ticks spent queuing +system.physmem.totMemAccLat 11137324750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10586.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29499.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.17 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29336.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.64 # Average write queue length when enqueuing -system.physmem.readRowHits 314689 # Number of row buffer hits during reads -system.physmem.writeRowHits 215833 # Number of row buffer hits during writes +system.physmem.avgWrQLen 20.74 # Average write queue length when enqueuing +system.physmem.readRowHits 314673 # Number of row buffer hits during reads +system.physmem.writeRowHits 215171 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.77 # Row buffer hit rate for writes -system.physmem.avgGap 611088.62 # Average gap between requests -system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 276203849000 # Time in different power states -system.physmem.memoryStateTime::REF 13724100000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 121069531000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 545847120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 524837880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 297833250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 286369875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1495111800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1465471800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 953117280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 942373440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 26844339600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 26844339600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 61600136265 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 58531832820 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 192563272500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 195254766750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 284299657815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 283849992165 # Total energy per rank (pJ) -system.physmem.averagePower::0 691.730926 # Core power per rank (mW) -system.physmem.averagePower::1 690.636842 # Core power per rank (mW) -system.cpu.branchPred.lookups 124266527 # Number of BP lookups -system.cpu.branchPred.condPredicted 87927203 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6406168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71920312 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67440384 # Number of BTB hits +system.physmem.writeRowHitRate 73.55 # Row buffer hit rate for writes +system.physmem.avgGap 610992.93 # Average gap between requests +system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 547495200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 298732500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1495119600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 953078400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61546767165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 192572713500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 284254177485 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.725104 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 319820574750 # Time in different power states +system.physmem_0.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77392866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 528262560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 288238500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465495200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 942392880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 58539586815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195210595500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 283814842575 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.655981 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 324225356250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 72987820500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 124267347 # Number of BP lookups +system.cpu.branchPred.condPredicted 87926966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6405633 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71910290 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67438494 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.770984 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15061672 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126459 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.781424 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15062581 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126311 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149394307 # DTB read hits -system.cpu.dtb.read_misses 568771 # DTB read misses +system.cpu.dtb.read_hits 149395037 # DTB read hits +system.cpu.dtb.read_misses 569044 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149963078 # DTB read accesses -system.cpu.dtb.write_hits 57322555 # DTB write hits -system.cpu.dtb.write_misses 67010 # DTB write misses +system.cpu.dtb.read_accesses 149964081 # DTB read accesses +system.cpu.dtb.write_hits 57322306 # DTB write hits +system.cpu.dtb.write_misses 67257 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57389565 # DTB write accesses -system.cpu.dtb.data_hits 206716862 # DTB hits -system.cpu.dtb.data_misses 635781 # DTB misses +system.cpu.dtb.write_accesses 57389563 # DTB write accesses +system.cpu.dtb.data_hits 206717343 # DTB hits +system.cpu.dtb.data_misses 636301 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207352643 # DTB accesses -system.cpu.itb.fetch_hits 226799477 # ITB hits +system.cpu.dtb.data_accesses 207353644 # DTB accesses +system.cpu.itb.fetch_hits 226796884 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226799525 # ITB accesses +system.cpu.itb.fetch_accesses 226796932 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -319,66 +322,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 822006022 # number of cpu cycles simulated +system.cpu.numCycles 821880966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12977706 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12979255 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.343363 # CPI: cycles per instruction -system.cpu.ipc 0.744400 # IPC: instructions per cycle -system.cpu.tickCycles 741717254 # Number of cycles that the object actually ticked -system.cpu.idleCycles 80288768 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535461 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.779511 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202630719 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539557 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.789790 # Average number of references to valid blocks. +system.cpu.cpi 1.343159 # CPI: cycles per instruction +system.cpu.ipc 0.744514 # IPC: instructions per cycle +system.cpu.tickCycles 741712966 # Number of cycles that the object actually ticked +system.cpu.idleCycles 80168000 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535450 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.778260 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202631199 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.779511 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.778260 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414705281 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414705281 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 146964513 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146964513 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 55666206 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666206 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 202630719 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202630719 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 202630719 # number of overall hits -system.cpu.dcache.overall_hits::total 202630719 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1908315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543828 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543828 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3452143 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452143 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3452143 # number of overall misses -system.cpu.dcache.overall_misses::total 3452143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36427451000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36427451000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45003472500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45003472500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 81430923500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81430923500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 81430923500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81430923500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 148872828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148872828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 146964985 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 55666214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 202631199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 202631199 # number of overall hits +system.cpu.dcache.overall_hits::total 202631199 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1908330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 1543820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3452150 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3452150 # number of overall misses +system.cpu.dcache.overall_misses::total 3452150 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36414832750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 44905898000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 81320730750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 81320730750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 148873315 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 206082862 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206082862 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 206082862 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206082862 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 206083349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 206083349 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses @@ -387,14 +390,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.016751 system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.016751 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19088.803997 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19088.803997 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29150.574092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29150.574092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23588.514004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23588.514004 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19082.041759 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29087.521861 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,32 +406,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340066 # number of writebacks -system.cpu.dcache.writebacks::total 2340066 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143549 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143549 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769037 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769037 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 912586 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912586 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 912586 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912586 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774791 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774791 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2539557 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539557 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2539557 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539557 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30235919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30235919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21217351500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21217351500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51453271000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51453271000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51453271000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51453271000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2340060 # number of writebacks +system.cpu.dcache.writebacks::total 2340060 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143560 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769044 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769044 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 912604 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912604 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 912604 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912604 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764770 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764770 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774776 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774776 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2539546 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539546 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2539546 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539546 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222614500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222614500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21167535500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21167535500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51390150000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51390150000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51390150000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51390150000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses @@ -437,69 +440,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012323 system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17133.104049 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17133.104049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27384.612754 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27384.612754 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20260.726969 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20260.726969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20260.726969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20260.726969 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17125.525989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17125.525989 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27320.845638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27320.845638 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3180 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.063523 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226794468 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5009 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45277.394290 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3192 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.017357 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226791863 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5021 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45168.664210 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.063523 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545441 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.017357 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545419 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545419 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2544567 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544567 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2544567 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544567 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098154 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.098154 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265541 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.265541 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149340 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149340 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149340 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149340 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73163.045484 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73163.045484 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71470.302768 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71470.302768 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72242.619834 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72242.619834 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72242.619834 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72242.619834 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149341 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149341 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149341 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149341 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73089.081686 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73089.081686 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71230.793801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71230.793801 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72078.656690 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72078.656690 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,93 +616,93 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292570 # number of writebacks -system.cpu.l2cache.writebacks::total 292570 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173378 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173378 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206627 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206627 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380005 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380005 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 380005 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380005 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10473281000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10473281000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12138501750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12138501750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22611782750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22611782750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22611782750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22611782750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 292569 # number of writebacks +system.cpu.l2cache.writebacks::total 292569 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173383 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 173383 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206626 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206626 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 380009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 380009 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380009 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10460839250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460839250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12089060000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12089060000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22549899250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22549899250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22549899250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22549899250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098154 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265541 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149340 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149340 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149340 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149340 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60407.208527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60407.208527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58745.961322 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58745.961322 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59503.908501 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59503.908501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59503.908501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149341 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149341 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60333.707745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60333.707745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58506.964274 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58506.964274 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778137 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778137 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10018 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 320576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312295872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312616448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778132 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 321344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312616128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884632 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4884627 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884632 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884627 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884632 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782382000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4884627 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782373500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8065750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8080250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891629500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173378 # Transaction distribution -system.membus.trans_dist::ReadResp 173378 # Transaction distribution -system.membus.trans_dist::Writeback 292570 # Transaction distribution -system.membus.trans_dist::ReadExReq 206627 # Transaction distribution -system.membus.trans_dist::ReadExResp 206627 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052580 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052580 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43044800 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 173383 # Transaction distribution +system.membus.trans_dist::ReadResp 173383 # Transaction distribution +system.membus.trans_dist::Writeback 292569 # Transaction distribution +system.membus.trans_dist::ReadExReq 206626 # Transaction distribution +system.membus.trans_dist::ReadExResp 206626 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 672575 # Request fanout histogram +system.membus.snoop_fanout::samples 672578 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 672575 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 672578 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 672575 # Request fanout histogram -system.membus.reqLayer0.occupancy 3222733000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 672578 # Request fanout histogram +system.membus.reqLayer0.occupancy 3222626500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3617871750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3617752750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 940b25691..a1fa65b86 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365348 # Number of seconds simulated -sim_ticks 365347511000 # Number of ticks simulated -final_tick 365347511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365317 # Number of seconds simulated +sim_ticks 365317233000 # Number of ticks simulated +final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 224796 # Simulator instruction rate (inst/s) -host_op_rate 243484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162123009 # Simulator tick rate (ticks/s) -host_mem_usage 256924 # Number of bytes of host memory used -host_seconds 2253.52 # Real time elapsed on the host +host_inst_rate 241300 # Simulator instruction rate (inst/s) +host_op_rate 261360 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174011250 # Simulator tick rate (ticks/s) +host_mem_usage 315696 # Number of bytes of host memory used +host_seconds 2099.39 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9224896 # Number of bytes read from this memory -system.physmem.bytes_read::total 9224896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6179008 # Number of bytes written to this memory -system.physmem.bytes_written::total 6179008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144139 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96547 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96547 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25249648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25249648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 605758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16912687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16912687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16912687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25249648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42162335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144139 # Number of read requests accepted -system.physmem.writeReqs 96547 # Number of write requests accepted -system.physmem.readBursts 144139 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96547 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9218048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 6177856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9224896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6179008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 9226048 # Number of bytes read from this memory +system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory +system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25254894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25254894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144157 # Number of read requests accepted +system.physmem.writeReqs 96561 # Number of write requests accepted +system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9344 # Per bank write bursts -system.physmem.perBankRdBursts::1 8969 # Per bank write bursts +system.physmem.perBankRdBursts::0 9347 # Per bank write bursts +system.physmem.perBankRdBursts::1 8970 # Per bank write bursts system.physmem.perBankRdBursts::2 8998 # Per bank write bursts -system.physmem.perBankRdBursts::3 8704 # Per bank write bursts -system.physmem.perBankRdBursts::4 9453 # Per bank write bursts -system.physmem.perBankRdBursts::5 9341 # Per bank write bursts -system.physmem.perBankRdBursts::6 8940 # Per bank write bursts +system.physmem.perBankRdBursts::3 8695 # Per bank write bursts +system.physmem.perBankRdBursts::4 9455 # Per bank write bursts +system.physmem.perBankRdBursts::5 9342 # Per bank write bursts +system.physmem.perBankRdBursts::6 8947 # Per bank write bursts system.physmem.perBankRdBursts::7 8101 # Per bank write bursts -system.physmem.perBankRdBursts::8 8571 # Per bank write bursts -system.physmem.perBankRdBursts::9 8677 # Per bank write bursts -system.physmem.perBankRdBursts::10 8772 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 9379 # Per bank write bursts -system.physmem.perBankRdBursts::13 9523 # Per bank write bursts -system.physmem.perBankRdBursts::14 8710 # Per bank write bursts -system.physmem.perBankRdBursts::15 9074 # Per bank write bursts -system.physmem.perBankWrBursts::0 6191 # Per bank write bursts -system.physmem.perBankWrBursts::1 6093 # Per bank write bursts +system.physmem.perBankRdBursts::8 8578 # Per bank write bursts +system.physmem.perBankRdBursts::9 8679 # Per bank write bursts +system.physmem.perBankRdBursts::10 8774 # Per bank write bursts +system.physmem.perBankRdBursts::11 9477 # Per bank write bursts +system.physmem.perBankRdBursts::12 9374 # Per bank write bursts +system.physmem.perBankRdBursts::13 9525 # Per bank write bursts +system.physmem.perBankRdBursts::14 8712 # Per bank write bursts +system.physmem.perBankRdBursts::15 9087 # Per bank write bursts +system.physmem.perBankWrBursts::0 6196 # Per bank write bursts +system.physmem.perBankWrBursts::1 6092 # Per bank write bursts system.physmem.perBankWrBursts::2 6006 # Per bank write bursts -system.physmem.perBankWrBursts::3 5817 # Per bank write bursts -system.physmem.perBankWrBursts::4 6161 # Per bank write bursts -system.physmem.perBankWrBursts::5 6171 # Per bank write bursts -system.physmem.perBankWrBursts::6 6013 # Per bank write bursts -system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::3 5813 # Per bank write bursts +system.physmem.perBankWrBursts::4 6163 # Per bank write bursts +system.physmem.perBankWrBursts::5 6172 # Per bank write bursts +system.physmem.perBankWrBursts::6 6014 # Per bank write bursts +system.physmem.perBankWrBursts::7 5493 # Per bank write bursts system.physmem.perBankWrBursts::8 5728 # Per bank write bursts -system.physmem.perBankWrBursts::9 5821 # Per bank write bursts -system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6446 # Per bank write bursts +system.physmem.perBankWrBursts::9 5823 # Per bank write bursts +system.physmem.perBankWrBursts::10 5962 # Per bank write bursts +system.physmem.perBankWrBursts::11 6445 # Per bank write bursts system.physmem.perBankWrBursts::12 6308 # Per bank write bursts -system.physmem.perBankWrBursts::13 6280 # Per bank write bursts -system.physmem.perBankWrBursts::14 5994 # Per bank write bursts -system.physmem.perBankWrBursts::15 6045 # Per bank write bursts +system.physmem.perBankWrBursts::13 6282 # Per bank write bursts +system.physmem.perBankWrBursts::14 5997 # Per bank write bursts +system.physmem.perBankWrBursts::15 6048 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 365347483000 # Total gap between requests +system.physmem.totGap 365317203500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144139 # Read request sizes (log2) +system.physmem.readPktSize::6 144157 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96547 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96561 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,37 +140,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -189,98 +189,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.344433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.101707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.291878 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24488 37.75% 37.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18300 28.21% 65.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6859 10.57% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7791 12.01% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2064 3.18% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1161 1.79% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 764 1.18% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 681 1.05% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2758 4.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5569 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.862992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.285392 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5565 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5569 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.333273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.210704 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.188900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5418 97.29% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 79 1.42% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 23 0.41% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 20 0.36% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 9 0.16% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 7 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 5 0.09% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5569 # Writes before turning the bus around for reads -system.physmem.totQLat 1570268250 # Total ticks spent queuing -system.physmem.totMemAccLat 4270868250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10902.22 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads +system.physmem.totQLat 1534207250 # Total ticks spent queuing +system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29652.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.86 # Average write queue length when enqueuing -system.physmem.readRowHits 110988 # Number of row buffer hits during reads -system.physmem.writeRowHits 64704 # Number of row buffer hits during writes +system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing +system.physmem.readRowHits 111019 # Number of row buffer hits during reads +system.physmem.writeRowHits 64498 # Number of row buffer hits during writes system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.02 # Row buffer hit rate for writes -system.physmem.avgGap 1517942.39 # Average gap between requests -system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 256543365500 # Time in different power states -system.physmem.memoryStateTime::REF 12199720000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 96603610750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 246584520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 243719280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134545125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132981750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 560422200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 562972800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 310625280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 314778960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 23862652320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 23862652320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 47112370740 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 46678345380 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 177881368500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 178262092500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 250108568685 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 250057542990 # Total energy per rank (pJ) -system.physmem.averagePower::0 684.578732 # Core power per rank (mW) -system.physmem.averagePower::1 684.439068 # Core power per rank (mW) -system.cpu.branchPred.lookups 132580026 # Number of BP lookups -system.cpu.branchPred.condPredicted 98506360 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6554090 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 69003825 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64853184 # Number of BTB hits +system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes +system.physmem.avgGap 1517614.82 # Average gap between requests +system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.594758 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.461067 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 132578917 # Number of BP lookups +system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.984912 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10016062 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17737 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -302,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -323,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -344,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -366,90 +411,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 730695022 # number of cpu cycles simulated +system.cpu.numCycles 730634466 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13461717 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.442402 # CPI: cycles per instruction -system.cpu.ipc 0.693288 # IPC: instructions per cycle -system.cpu.tickCycles 695775254 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34919768 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139848 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.076883 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171283127 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143944 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.730343 # Average number of references to valid blocks. +system.cpu.cpi 1.442282 # CPI: cycles per instruction +system.cpu.ipc 0.693346 # IPC: instructions per cycle +system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139812 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.076883 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.074819 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346820764 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346820764 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 114767369 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114767369 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538676 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538676 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 114766084 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 53538710 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 168306045 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168306045 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168306045 # number of overall hits -system.cpu.dcache.overall_hits::total 168306045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 854653 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854653 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 700630 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700630 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 1555283 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555283 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1555283 # number of overall misses -system.cpu.dcache.overall_misses::total 1555283 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13708895232 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13708895232 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20586763000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20586763000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 34295658232 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34295658232 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 34295658232 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34295658232 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 115622022 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115622022 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 168304794 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168304794 # number of overall hits +system.cpu.dcache.overall_hits::total 168304794 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 854755 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 700596 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 1555351 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1555351 # number of overall misses +system.cpu.dcache.overall_misses::total 1555351 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13707430482 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20521575250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 34229005732 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 34229005732 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 115620839 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 169861328 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169861328 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 169861328 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169861328 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007392 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 169860145 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 169860145 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007393 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.009156 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009156 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.009156 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009156 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16040.305518 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16040.305518 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29383.216534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29383.216534 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22051.072526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22051.072526 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.009157 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.009157 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16036.677740 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29291.596369 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,103 +503,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068569 # number of writebacks -system.cpu.dcache.writebacks::total 1068569 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66869 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66869 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787784 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787784 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356160 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356160 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1143944 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143944 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1143944 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143944 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11256226015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11256226015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10106063500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10106063500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21362289515 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111385 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27648.726753 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684688 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142574 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.816236 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 163201810500 # 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number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 100868 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100868 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 144174 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144174 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 144174 # number of overall misses +system.cpu.l2cache.overall_misses::total 144174 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3229271000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3229271000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7164307250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7164307250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10393578250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10393578250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10393578250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10393578250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 807073 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 807073 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1068525 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1068525 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356398 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356398 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1163471 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163471 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1163471 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163471 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053658 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.053658 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283021 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283021 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123917 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123917 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123917 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123917 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74568.674087 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74568.674087 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71026.561942 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71026.561942 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72090.517361 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72090.517361 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72090.517361 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72090.517361 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -667,60 +712,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # 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number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100869 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100869 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144139 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144139 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2682518500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2682518500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5916082000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5916082000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8598600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8598600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8598600500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8598600500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283012 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283012 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123888 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123888 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100868 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 144157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 144157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2680290500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5883442250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8563732750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8563732750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61916.202730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58328.134294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356413 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1248896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141600832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142849728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2232027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -729,41 +774,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2232027 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2232027 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184582500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29960995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744681985 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43270 # Transaction distribution -system.membus.trans_dist::ReadResp 43270 # Transaction distribution -system.membus.trans_dist::Writeback 96547 # Transaction distribution -system.membus.trans_dist::ReadExReq 100869 # Transaction distribution -system.membus.trans_dist::ReadExResp 100869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384825 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384825 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15403904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15403904 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43289 # Transaction distribution +system.membus.trans_dist::ReadResp 43289 # Transaction distribution +system.membus.trans_dist::Writeback 96561 # Transaction distribution +system.membus.trans_dist::ReadExReq 100868 # Transaction distribution +system.membus.trans_dist::ReadExResp 100868 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240686 # Request fanout histogram +system.membus.snoop_fanout::samples 240718 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240686 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240686 # Request fanout histogram -system.membus.reqLayer0.occupancy 1081853000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 240718 # Request fanout histogram +system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1366563500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e3aeba90b..e36a9b419 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.231519 # Number of seconds simulated -sim_ticks 231518815500 # Number of ticks simulated -final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.232212 # Number of seconds simulated +sim_ticks 232211555000 # Number of ticks simulated +final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137569 # Simulator instruction rate (inst/s) -host_op_rate 149036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63039200 # Simulator tick rate (ticks/s) -host_mem_usage 324016 # Number of bytes of host memory used -host_seconds 3672.62 # Real time elapsed on the host +host_inst_rate 135087 # Simulator instruction rate (inst/s) +host_op_rate 146347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62087234 # Simulator tick rate (ticks/s) +host_mem_usage 317808 # Number of bytes of host memory used +host_seconds 3740.09 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory -system.physmem.bytes_read::total 28711552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory -system.physmem.bytes_written::total 19446336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448618 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory -system.physmem.num_writes::total 303849 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448618 # Number of read requests accepted -system.physmem.writeReqs 303849 # Number of write requests accepted -system.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue -system.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory +system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory +system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory +system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412658 # Number of read requests accepted +system.physmem.writeReqs 292638 # Number of write requests accepted +system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue +system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28534 # Per bank write bursts -system.physmem.perBankRdBursts::1 27313 # Per bank write bursts -system.physmem.perBankRdBursts::2 27956 # Per bank write bursts -system.physmem.perBankRdBursts::3 26702 # Per bank write bursts -system.physmem.perBankRdBursts::4 30075 # Per bank write bursts -system.physmem.perBankRdBursts::5 29207 # Per bank write bursts -system.physmem.perBankRdBursts::6 27700 # Per bank write bursts -system.physmem.perBankRdBursts::7 26438 # Per bank write bursts -system.physmem.perBankRdBursts::8 28442 # Per bank write bursts -system.physmem.perBankRdBursts::9 26796 # Per bank write bursts -system.physmem.perBankRdBursts::10 28037 # Per bank write bursts -system.physmem.perBankRdBursts::11 28667 # Per bank write bursts -system.physmem.perBankRdBursts::12 28663 # Per bank write bursts -system.physmem.perBankRdBursts::13 27984 # Per bank write bursts -system.physmem.perBankRdBursts::14 26659 # Per bank write bursts -system.physmem.perBankRdBursts::15 27067 # Per bank write bursts -system.physmem.perBankWrBursts::0 19504 # Per bank write bursts -system.physmem.perBankWrBursts::1 19011 # Per bank write bursts -system.physmem.perBankWrBursts::2 18881 # Per bank write bursts -system.physmem.perBankWrBursts::3 18629 # Per bank write bursts -system.physmem.perBankWrBursts::4 19556 # Per bank write bursts -system.physmem.perBankWrBursts::5 19014 # Per bank write bursts -system.physmem.perBankWrBursts::6 18738 # Per bank write bursts -system.physmem.perBankWrBursts::7 18227 # Per bank write bursts -system.physmem.perBankWrBursts::8 18808 # Per bank write bursts -system.physmem.perBankWrBursts::9 18381 # Per bank write bursts -system.physmem.perBankWrBursts::10 19036 # Per bank write bursts -system.physmem.perBankWrBursts::11 19525 # Per bank write bursts -system.physmem.perBankWrBursts::12 19578 # Per bank write bursts -system.physmem.perBankWrBursts::13 19080 # Per bank write bursts -system.physmem.perBankWrBursts::14 18969 # Per bank write bursts -system.physmem.perBankWrBursts::15 18884 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26576 # Per bank write bursts +system.physmem.perBankRdBursts::1 25575 # Per bank write bursts +system.physmem.perBankRdBursts::2 25174 # Per bank write bursts +system.physmem.perBankRdBursts::3 24876 # Per bank write bursts +system.physmem.perBankRdBursts::4 27202 # Per bank write bursts +system.physmem.perBankRdBursts::5 26589 # Per bank write bursts +system.physmem.perBankRdBursts::6 25428 # Per bank write bursts +system.physmem.perBankRdBursts::7 24234 # Per bank write bursts +system.physmem.perBankRdBursts::8 25846 # Per bank write bursts +system.physmem.perBankRdBursts::9 24812 # Per bank write bursts +system.physmem.perBankRdBursts::10 25055 # Per bank write bursts +system.physmem.perBankRdBursts::11 26081 # Per bank write bursts +system.physmem.perBankRdBursts::12 26502 # Per bank write bursts +system.physmem.perBankRdBursts::13 25872 # Per bank write bursts +system.physmem.perBankRdBursts::14 25198 # Per bank write bursts +system.physmem.perBankRdBursts::15 25467 # Per bank write bursts +system.physmem.perBankWrBursts::0 18795 # Per bank write bursts +system.physmem.perBankWrBursts::1 18343 # Per bank write bursts +system.physmem.perBankWrBursts::2 17877 # Per bank write bursts +system.physmem.perBankWrBursts::3 18076 # Per bank write bursts +system.physmem.perBankWrBursts::4 18802 # Per bank write bursts +system.physmem.perBankWrBursts::5 18306 # Per bank write bursts +system.physmem.perBankWrBursts::6 18071 # Per bank write bursts +system.physmem.perBankWrBursts::7 17638 # Per bank write bursts +system.physmem.perBankWrBursts::8 18138 # Per bank write bursts +system.physmem.perBankWrBursts::9 17849 # Per bank write bursts +system.physmem.perBankWrBursts::10 18079 # Per bank write bursts +system.physmem.perBankWrBursts::11 18708 # Per bank write bursts +system.physmem.perBankWrBursts::12 18879 # Per bank write bursts +system.physmem.perBankWrBursts::13 18261 # Per bank write bursts +system.physmem.perBankWrBursts::14 18465 # Per bank write bursts +system.physmem.perBankWrBursts::15 18329 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 231518762500 # Total gap between requests +system.physmem.totGap 232211534500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 448618 # Read request sizes (log2) +system.physmem.readPktSize::6 412658 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 303849 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,125 +197,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads -system.physmem.totQLat 10651839911 # Total ticks spent queuing -system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads +system.physmem.totQLat 9526506707 # Total ticks spent queuing +system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.62 # Data bus utilization in percentage -system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing -system.physmem.readRowHits 331076 # Number of row buffer hits during reads -system.physmem.writeRowHits 99609 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes -system.physmem.avgGap 307679.62 # Average gap between requests -system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states -system.physmem.memoryStateTime::REF 7730840000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 1204270200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1209705840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 657091875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 660057750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1746123600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1733674800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 981894960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 986450400 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 15121523040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 15121523040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 75885673770 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 75815795475 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 72343590000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 72404886750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 167940167445 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 167932094055 # Total energy per rank (pJ) -system.physmem.averagePower::0 725.391418 # Core power per rank (mW) -system.physmem.averagePower::1 725.356546 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 445006 # Transaction distribution -system.membus.trans_dist::ReadResp 445005 # Transaction distribution -system.membus.trans_dist::Writeback 303849 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 3612 # Transaction distribution -system.membus.trans_dist::ReadExResp 3612 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 752471 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 752471 # Request fanout histogram -system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 175071152 # Number of BP lookups -system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits +system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing +system.physmem.readRowHits 299737 # Number of row buffer hits during reads +system.physmem.writeRowHits 95481 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes +system.physmem.avgGap 329239.83 # Average gap between requests +system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.427350 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states +system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.098525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states +system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 175052211 # Number of BP lookups +system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -358,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -379,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -401,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 463037632 # number of cpu cycles simulated +system.cpu.numCycles 464423111 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14941835 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -551,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued -system.cpu.iq.rate 1.317880 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued +system.cpu.iq.rate 1.313932 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1486621 # number of nop insts executed -system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed -system.cpu.iew.exec_branches 131372634 # Number of branches executed -system.cpu.iew.exec_stores 60949141 # Number of stores executed -system.cpu.iew.exec_rate 1.294450 # Inst execution rate -system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349881958 # num instructions producing a value -system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value +system.cpu.iew.exec_nop 1486524 # number of nop insts executed +system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed +system.cpu.iew.exec_branches 131371292 # Number of branches executed +system.cpu.iew.exec_stores 60952468 # Number of stores executed +system.cpu.iew.exec_rate 1.290583 # Inst execution rate +system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349870966 # num instructions producing a value +system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back +system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -674,513 +684,527 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1090469902 # The number of ROB reads -system.cpu.rob.rob_writes 1334452492 # The number of ROB writes -system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1091332417 # The number of ROB reads +system.cpu.rob.rob_writes 1334357175 # The number of ROB writes +system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611059162 # number of integer regfile reads -system.cpu.int_regfile_writes 328109228 # number of integer regfile writes +system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads +system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611063177 # number of integer regfile reads +system.cpu.int_regfile_writes 328106532 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads -system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes -system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads +system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes +system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 453214 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 73538 # number of replacements -system.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2823114 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits +system.cpu.dcache.overall_hits::total 166674811 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses +system.cpu.dcache.overall_misses::total 7050523 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173725334 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619626514 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8857939270 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27572196041 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.061207 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063782 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006925 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006925 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.046955 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.080000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.080000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053569 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173042 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73450.188805 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62120.549015 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62300.872022 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488556 # 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number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses -system.cpu.dcache.overall_misses::total 7049008 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks -system.cpu.dcache.writebacks::total 2348838 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 335729 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 408974 # Transaction distribution +system.membus.trans_dist::ReadResp 408974 # Transaction distribution +system.membus.trans_dist::Writeback 292638 # Transaction distribution +system.membus.trans_dist::UpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 3684 # Transaction distribution +system.membus.trans_dist::ReadExResp 3684 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 705299 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 705299 # Request fanout histogram +system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index aa1528255..29aebf258 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362297500 # Number of ticks simulated final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2087081 # Simulator instruction rate (inst/s) -host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1150953174 # Simulator tick rate (ticks/s) -host_mem_usage 299952 # Number of bytes of host memory used -host_seconds 242.72 # Real time elapsed on the host +host_inst_rate 1700410 # Simulator instruction rate (inst/s) +host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 937717572 # Simulator tick rate (ticks/s) +host_mem_usage 304668 # Number of bytes of host memory used +host_seconds 297.92 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 773431583 # Wr system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 630711790 # Transaction distribution -system.membus.trans_dist::ReadResp 632200331 # Transaction distribution -system.membus.trans_dist::WriteReq 54239306 # Transaction distribution -system.membus.trans_dist::WriteResp 54239306 # Transaction distribution -system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution -system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 687930749 # Request fanout histogram -system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 687930749 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction +system.membus.trans_dist::ReadReq 630711790 # Transaction distribution +system.membus.trans_dist::ReadResp 632200331 # Transaction distribution +system.membus.trans_dist::WriteReq 54239306 # Transaction distribution +system.membus.trans_dist::WriteResp 54239306 # Transaction distribution +system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution +system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 687930749 # Request fanout histogram +system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 687930749 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index a70fb0c6b..efad42105 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.707539 # Nu sim_ticks 707539023000 # Number of ticks simulated final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1199909 # Simulator instruction rate (inst/s) -host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1681197618 # Simulator tick rate (ticks/s) -host_mem_usage 309428 # Number of bytes of host memory used -host_seconds 420.85 # Real time elapsed on the host +host_inst_rate 1166033 # Simulator instruction rate (inst/s) +host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1633733414 # Simulator tick rate (ticks/s) +host_mem_usage 312880 # Number of bytes of host memory used +host_seconds 433.08 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 8679369 # To system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 41855 # Transaction distribution -system.membus.trans_dist::ReadResp 41855 # Transaction distribution -system.membus.trans_dist::Writeback 95953 # Transaction distribution -system.membus.trans_dist::ReadExReq 100794 # Transaction distribution -system.membus.trans_dist::ReadExResp 100794 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 238603 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 238603 # Request fanout histogram -system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,139 @@ system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction +system.cpu.dcache.tags.replacements 1134822 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits +system.cpu.dcache.overall_hits::total 167203374 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses +system.cpu.dcache.overall_misses::total 1138918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks +system.cpu.dcache.writebacks::total 1064905 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. @@ -439,139 +580,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits -system.cpu.dcache.overall_hits::total 167203374 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses -system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks -system.cpu.dcache.writebacks::total 1064905 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution @@ -605,5 +613,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 17281500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 41855 # Transaction distribution +system.membus.trans_dist::ReadResp 41855 # Transaction distribution +system.membus.trans_dist::Writeback 95953 # Transaction distribution +system.membus.trans_dist::ReadExReq 100794 # Transaction distribution +system.membus.trans_dist::ReadExResp 100794 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 238603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 238603 # Request fanout histogram +system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 666f127d9..be422e790 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451764 # Number of seconds simulated -sim_ticks 451764406000 # Number of ticks simulated -final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.451526 # Number of seconds simulated +sim_ticks 451526391500 # Number of ticks simulated +final_tick 451526391500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112231 # Simulator instruction rate (inst/s) -host_op_rate 207527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61317335 # Simulator tick rate (ticks/s) -host_mem_usage 367016 # Number of bytes of host memory used -host_seconds 7367.65 # Real time elapsed on the host +host_inst_rate 97078 # Simulator instruction rate (inst/s) +host_op_rate 179507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53010367 # Simulator tick rate (ticks/s) +host_mem_usage 427448 # Number of bytes of host memory used +host_seconds 8517.70 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24540544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24764608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18820736 # Number of bytes written to this memory -system.physmem.bytes_written::total 18820736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386947 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294074 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294074 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 495975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54321553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54817528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 495975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 495975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41660511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41660511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41660511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 495975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54321553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96478039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386948 # Number of read requests accepted -system.physmem.writeReqs 294074 # Number of write requests accepted -system.physmem.readBursts 386948 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294074 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24743168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21504 # Total number of bytes read from write queue -system.physmem.bytesWritten 18819072 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24764672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18820736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 336 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 224960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24535168 # Number of bytes read from this memory +system.physmem.bytes_read::total 24760128 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18817920 # Number of bytes written to this memory +system.physmem.bytes_written::total 18817920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383362 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386877 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294030 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294030 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 498221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54338281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54836502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 498221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41676235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41676235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41676235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 498221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54338281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 96512737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386877 # Number of read requests accepted +system.physmem.writeReqs 294030 # Number of write requests accepted +system.physmem.readBursts 386877 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294030 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24738496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue +system.physmem.bytesWritten 18816576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24760128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18817920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 179060 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24122 # Per bank write bursts -system.physmem.perBankRdBursts::1 26505 # Per bank write bursts -system.physmem.perBankRdBursts::2 24681 # Per bank write bursts -system.physmem.perBankRdBursts::3 24611 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 180174 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24137 # Per bank write bursts +system.physmem.perBankRdBursts::1 26529 # Per bank write bursts +system.physmem.perBankRdBursts::2 24699 # Per bank write bursts +system.physmem.perBankRdBursts::3 24593 # Per bank write bursts system.physmem.perBankRdBursts::4 23302 # Per bank write bursts -system.physmem.perBankRdBursts::5 23732 # Per bank write bursts -system.physmem.perBankRdBursts::6 24448 # Per bank write bursts -system.physmem.perBankRdBursts::7 24311 # Per bank write bursts -system.physmem.perBankRdBursts::8 23620 # Per bank write bursts -system.physmem.perBankRdBursts::9 23937 # Per bank write bursts -system.physmem.perBankRdBursts::10 24812 # Per bank write bursts -system.physmem.perBankRdBursts::11 24076 # Per bank write bursts -system.physmem.perBankRdBursts::12 23393 # Per bank write bursts -system.physmem.perBankRdBursts::13 22985 # Per bank write bursts -system.physmem.perBankRdBursts::14 24096 # Per bank write bursts -system.physmem.perBankRdBursts::15 23981 # Per bank write bursts +system.physmem.perBankRdBursts::5 23749 # Per bank write bursts +system.physmem.perBankRdBursts::6 24449 # Per bank write bursts +system.physmem.perBankRdBursts::7 24297 # Per bank write bursts +system.physmem.perBankRdBursts::8 23610 # Per bank write bursts +system.physmem.perBankRdBursts::9 23919 # Per bank write bursts +system.physmem.perBankRdBursts::10 24817 # Per bank write bursts +system.physmem.perBankRdBursts::11 24050 # Per bank write bursts +system.physmem.perBankRdBursts::12 23346 # Per bank write bursts +system.physmem.perBankRdBursts::13 22971 # Per bank write bursts +system.physmem.perBankRdBursts::14 24088 # Per bank write bursts +system.physmem.perBankRdBursts::15 23983 # Per bank write bursts system.physmem.perBankWrBursts::0 18558 # Per bank write bursts -system.physmem.perBankWrBursts::1 19850 # Per bank write bursts -system.physmem.perBankWrBursts::2 18948 # Per bank write bursts -system.physmem.perBankWrBursts::3 18946 # Per bank write bursts +system.physmem.perBankWrBursts::1 19844 # Per bank write bursts +system.physmem.perBankWrBursts::2 18955 # Per bank write bursts +system.physmem.perBankWrBursts::3 18948 # Per bank write bursts system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18437 # Per bank write bursts -system.physmem.perBankWrBursts::6 18993 # Per bank write bursts -system.physmem.perBankWrBursts::7 18991 # Per bank write bursts -system.physmem.perBankWrBursts::8 18543 # Per bank write bursts -system.physmem.perBankWrBursts::9 18160 # Per bank write bursts -system.physmem.perBankWrBursts::10 18841 # Per bank write bursts -system.physmem.perBankWrBursts::11 17736 # Per bank write bursts -system.physmem.perBankWrBursts::12 17380 # Per bank write bursts -system.physmem.perBankWrBursts::13 16967 # Per bank write bursts -system.physmem.perBankWrBursts::14 17832 # Per bank write bursts -system.physmem.perBankWrBursts::15 17826 # Per bank write bursts +system.physmem.perBankWrBursts::5 18446 # Per bank write bursts +system.physmem.perBankWrBursts::6 18985 # Per bank write bursts +system.physmem.perBankWrBursts::7 18975 # Per bank write bursts +system.physmem.perBankWrBursts::8 18547 # Per bank write bursts +system.physmem.perBankWrBursts::9 18155 # Per bank write bursts +system.physmem.perBankWrBursts::10 18842 # Per bank write bursts +system.physmem.perBankWrBursts::11 17721 # Per bank write bursts +system.physmem.perBankWrBursts::12 17374 # Per bank write bursts +system.physmem.perBankWrBursts::13 16974 # Per bank write bursts +system.physmem.perBankWrBursts::14 17821 # Per bank write bursts +system.physmem.perBankWrBursts::15 17824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 451764392500 # Total gap between requests +system.physmem.totGap 451526286000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386948 # Read request sizes (log2) +system.physmem.readPktSize::6 386877 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294074 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294030 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,418 +144,395 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17467 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17580 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.521852 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.115334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.715133 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54829 37.20% 37.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40372 27.39% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13383 9.08% 73.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7515 5.10% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5234 3.55% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3732 2.53% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3157 2.14% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2805 1.90% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16375 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147402 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17447 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.158537 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.201153 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17434 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.912829 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.000830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.915309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54902 37.17% 37.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40417 27.37% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13633 9.23% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7488 5.07% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5349 3.62% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3749 2.54% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3045 2.06% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2781 1.88% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16322 11.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147686 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17443 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.159892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.587687 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17430 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17447 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.853786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.774474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.995315 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17244 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 149 0.85% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17443 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17443 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.855415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.780849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.647023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17241 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 150 0.86% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17447 # Writes before turning the bus around for reads -system.physmem.totQLat 4338654000 # Total ticks spent queuing -system.physmem.totMemAccLat 11587629000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1933060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11222.24 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17443 # Writes before turning the bus around for reads +system.physmem.totQLat 4244351250 # Total ticks spent queuing +system.physmem.totMemAccLat 11491957500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932695000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10980.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29972.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29730.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.75 # Data bus utilization in percentage system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.93 # Average write queue length when enqueuing -system.physmem.readRowHits 317693 # Number of row buffer hits during reads -system.physmem.writeRowHits 215552 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes -system.physmem.avgGap 663362.41 # Average gap between requests -system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 312439483250 # Time in different power states -system.physmem.memoryStateTime::REF 15085200000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 567642600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 546300720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 309725625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 298080750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1526397600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1488559800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 976736880 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 928272960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 29506651200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 29506651200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 64826566830 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 62404533090 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 214189673250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 216314264250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 311903393985 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 311486662770 # Total energy per rank (pJ) -system.physmem.averagePower::0 690.420687 # Core power per rank (mW) -system.physmem.averagePower::1 689.498222 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 179971 # Transaction distribution -system.membus.trans_dist::ReadResp 179970 # Transaction distribution -system.membus.trans_dist::Writeback 294074 # Transaction distribution -system.membus.trans_dist::UpgradeReq 179060 # Transaction distribution -system.membus.trans_dist::UpgradeResp 179060 # Transaction distribution -system.membus.trans_dist::ReadExReq 206977 # Transaction distribution -system.membus.trans_dist::ReadExResp 206977 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 860082 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 860082 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 860082 # Request fanout histogram -system.membus.reqLayer0.occupancy 3467694500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3995364517 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 231811700 # Number of BP lookups -system.cpu.branchPred.condPredicted 231811700 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9749774 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132043202 # Number of BTB lookups -system.cpu.branchPred.BTBHits 129334985 # Number of BTB hits +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.42 # Average write queue length when enqueuing +system.physmem.readRowHits 317756 # Number of row buffer hits during reads +system.physmem.writeRowHits 215101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes +system.physmem.avgGap 663124.75 # Average gap between requests +system.physmem.pageHitRate 78.30 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 569336040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310649625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1526881200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 976788720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64757369970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 214110228000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 311742647955 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.421834 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 355630472000 # Time in different power states +system.physmem_0.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80817135000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 547049160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 298489125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1487951400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928182240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62071035210 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 216466682250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 311290783785 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.421031 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 359566067000 # Time in different power states +system.physmem_1.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 76881477500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 231910847 # Number of BP lookups +system.cpu.branchPred.condPredicted 231910847 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9746486 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132027793 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129309443 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.948992 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28034260 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1466603 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.941077 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28045741 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1465755 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903528833 # number of cpu cycles simulated +system.cpu.numCycles 903052797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 186193866 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1278658073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20239877 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1885 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 180561661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2733230 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 903347128 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.632355 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.341099 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186172753 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278263981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231910847 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157355184 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 705668368 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20227891 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1132 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 96729 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 811106 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1664 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180547715 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2736967 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 902865746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.633456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.342016 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492680103 54.54% 54.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 34123521 3.78% 58.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33275891 3.68% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33627770 3.72% 65.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27182272 3.01% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27855831 3.08% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37310737 4.13% 75.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33828820 3.74% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183462183 20.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 492504429 54.55% 54.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33980590 3.76% 58.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33251729 3.68% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33383912 3.70% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27248388 3.02% 68.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27817475 3.08% 71.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37350305 4.14% 75.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33792757 3.74% 79.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183536161 20.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 903347128 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.256563 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.415182 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127724228 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 442644539 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240143304 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82715119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10119938 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2233772257 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10119938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159908050 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 227395701 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285948747 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219943139 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183809979 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 169165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 140088736 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 23988102 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 45039827 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2289176453 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5526365527 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3514194402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 52054 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 902865746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.256808 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.415492 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127621918 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 442269855 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240334233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82525795 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10113945 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2233625829 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10113945 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159854620 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 227411371 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31769 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285878914 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219575127 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2183611721 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 177740 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 139597859 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24038652 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44983183 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2288587317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5525861457 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3514141602 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 52752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 675135599 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2312 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2290 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 426537147 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 530783294 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210410050 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 240827707 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72173678 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112785390 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25204 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1829110925 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 437516 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 579120624 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1007560279 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24652 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 903347128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.024815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.069613 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 674546463 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2421 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2405 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 426714045 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530721549 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210389629 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240824950 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72195473 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112352245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24995 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1828962616 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 418654 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 578669571 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1006826210 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24443 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 902865746 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.025730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070839 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 319005991 35.31% 35.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 130297139 14.42% 49.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 120325805 13.32% 63.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111338872 12.33% 75.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91295017 10.11% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61401299 6.80% 92.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43188488 4.78% 97.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19128067 2.12% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7366450 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 318904182 35.32% 35.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130514441 14.46% 49.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119555800 13.24% 63.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 110903587 12.28% 75.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91967934 10.19% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61336498 6.79% 92.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43115692 4.78% 97.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19163460 2.12% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7404152 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 903347128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 902865746 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11298417 42.44% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12271176 46.10% 88.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3050228 11.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11303507 42.48% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12206863 45.87% 88.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3099868 11.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719541 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212963557 66.31% 66.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 389902 0.02% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881002 0.21% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435438564 23.81% 90.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173718237 9.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2714574 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212750239 66.31% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 388692 0.02% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881011 0.21% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435509272 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173718712 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1829110925 # Type of FU issued -system.cpu.iq.rate 2.024408 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26619821 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014553 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4588595925 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2692200263 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1799476115 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 30390 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 66120 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6655 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1852997149 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185108157 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1828962616 # Type of FU issued +system.cpu.iq.rate 2.025311 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26610238 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014549 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4587788532 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2691313007 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799275575 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31338 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 67501 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6790 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852843768 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14512 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185242573 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 146685050 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 212835 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 388917 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61249864 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146624129 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213999 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 388901 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61229443 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18586 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 815 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19562 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 956 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10119938 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166724787 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10164048 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112810594 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401170 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 530787207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210410050 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7737 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4462758 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3568650 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 388917 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5751622 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4609702 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10361324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1807989007 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 429368726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21121918 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10113945 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 166739883 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10207354 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112377240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 401313 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530726286 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210389629 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7530 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4519493 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3556436 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 388901 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5749904 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4643271 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10393175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1807883955 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429428539 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21078661 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599512830 # number of memory reference insts executed -system.cpu.iew.exec_branches 171944433 # Number of branches executed -system.cpu.iew.exec_stores 170144104 # Number of stores executed -system.cpu.iew.exec_rate 2.001031 # Inst execution rate -system.cpu.iew.wb_sent 1804759601 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1799482770 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1369602342 # num instructions producing a value -system.cpu.iew.wb_consumers 2093301343 # num instructions consuming a value +system.cpu.iew.exec_refs 599547832 # number of memory reference insts executed +system.cpu.iew.exec_branches 171967250 # Number of branches executed +system.cpu.iew.exec_stores 170119293 # Number of stores executed +system.cpu.iew.exec_rate 2.001969 # Inst execution rate +system.cpu.iew.wb_sent 1804612346 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799282365 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369352269 # num instructions producing a value +system.cpu.iew.wb_consumers 2092896532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.991616 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654279 # average fanout of values written-back +system.cpu.iew.wb_rate 1.992444 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 583616621 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 824173638 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9832190 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823756093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.505218 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 355774644 43.17% 43.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174944190 21.23% 64.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57267566 6.95% 71.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27168668 3.30% 85.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27065091 3.28% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9878369 1.20% 89.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8803957 1.07% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76959576 9.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 355425849 43.15% 43.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174994405 21.24% 64.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57317339 6.96% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86207861 10.47% 81.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27016335 3.28% 85.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27048633 3.28% 88.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9853927 1.20% 89.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8829984 1.07% 90.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 77061760 9.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 824173638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823756093 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,256 +578,338 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76959576 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 77061760 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2860250696 # The number of ROB reads -system.cpu.rob.rob_writes 4305432556 # The number of ROB writes -system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2859299655 # The number of ROB reads +system.cpu.rob.rob_writes 4304507020 # The number of ROB writes +system.cpu.timesIdled 2587 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 187051 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.092700 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.092700 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.915164 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2763452214 # number of integer regfile reads -system.cpu.int_regfile_writes 1467518123 # number of integer regfile writes -system.cpu.fp_regfile_reads 6756 # number of floating regfile reads -system.cpu.fp_regfile_writes 202 # number of floating regfile writes -system.cpu.cc_regfile_reads 600952146 # number of cc regfile reads -system.cpu.cc_regfile_writes 409697644 # number of cc regfile writes -system.cpu.misc_regfile_reads 991728878 # number of misc regfile reads +system.cpu.cpi 1.092125 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.092125 # CPI: Total CPI of All Threads +system.cpu.ipc 0.915646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.915646 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763619398 # number of integer regfile reads +system.cpu.int_regfile_writes 1467382261 # number of integer regfile writes +system.cpu.fp_regfile_reads 6855 # number of floating regfile reads +system.cpu.fp_regfile_writes 205 # number of floating regfile writes +system.cpu.cc_regfile_reads 600921704 # number of cc regfile reads +system.cpu.cc_regfile_writes 409683570 # number of cc regfile writes +system.cpu.misc_regfile_reads 991700936 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 1956687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1956686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2333034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 180860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 180860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771518 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 198212 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7771975 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7970187 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311785216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312336768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 180976 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5242099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5242099 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5242099 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4970549506 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 284884490 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3981162622 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 7001 # number of replacements -system.cpu.icache.tags.tagsinuse 1081.953602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 180366705 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8614 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20938.786278 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2534340 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.717392 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 388713882 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538436 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.131252 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.717392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 872 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 786546356 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 786546356 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 240120715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 240120715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148188548 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148188548 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 388309263 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 388309263 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 388309263 # number of overall hits +system.cpu.dcache.overall_hits::total 388309263 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2723043 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2723043 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 971654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 971654 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3694697 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3694697 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3694697 # number of overall misses +system.cpu.dcache.overall_misses::total 3694697 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55426039088 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55426039088 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27751124058 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27751124058 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83177163146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83177163146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83177163146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83177163146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 392003960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 392003960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 392003960 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 392003960 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011213 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011213 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006514 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006514 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009425 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009425 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009425 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009425 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20354.448713 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20354.448713 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28560.705825 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28560.705825 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22512.580367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22512.580367 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9748 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1054 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.248577 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5.333333 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2333101 # number of writebacks +system.cpu.dcache.writebacks::total 2333101 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 955922 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 955922 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18334 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18334 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 974256 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 974256 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 974256 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 974256 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767121 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767121 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 953320 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 953320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2720441 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2720441 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2720441 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2720441 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30613583252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30613583252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25522867191 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25522867191 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56136450443 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56136450443 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56136450443 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56136450443 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007277 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007277 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006391 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006391 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006940 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006940 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17323.988143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17323.988143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26772.612754 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26772.612754 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 6998 # number of replacements +system.cpu.icache.tags.tagsinuse 1079.308636 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180351835 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20956.522775 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1081.953602 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.528298 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.528298 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1613 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1172 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.787598 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 361312916 # Number of tag accesses -system.cpu.icache.tags.data_accesses 361312916 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 180369624 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 180369624 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 180369624 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 180369624 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 180369624 # number of overall hits -system.cpu.icache.overall_hits::total 180369624 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.160740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59732.751033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59756.338591 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2534514 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.721227 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 388791403 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538610 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.151293 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.721227 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998223 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998223 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 861 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3187 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 786699916 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 786699916 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 240205034 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 240205034 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148189734 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148189734 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 388394768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 388394768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 388394768 # number of overall hits -system.cpu.dcache.overall_hits::total 388394768 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2715417 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2715417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 970468 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 970468 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3685885 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3685885 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3685885 # number of overall misses -system.cpu.dcache.overall_misses::total 3685885 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55284847940 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55284847940 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27786671624 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27786671624 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83071519564 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83071519564 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83071519564 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83071519564 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242920451 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242920451 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 392080653 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 392080653 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 392080653 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 392080653 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011178 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011178 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006506 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009401 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009401 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009401 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009401 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20359.616199 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20359.616199 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28632.238903 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28632.238903 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22537.740479 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22537.740479 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8578 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 914 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.385120 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.400000 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2333034 # number of writebacks -system.cpu.dcache.writebacks::total 2333034 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 948123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 948123 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 966414 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 966414 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 966414 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 966414 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767294 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767294 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 952177 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 952177 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2719471 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2719471 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2719471 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2719471 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30652377753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30652377753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25560484625 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25560484625 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56212862378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56212862378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56212862378 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56212862378 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006936 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006936 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 1957626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1957626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2333101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 182005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 182005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771533 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 199325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7773983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7973308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311778368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312328896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182121 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5244265 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5244265 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5244265 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4971600701 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 286576989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3981486557 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 179848 # Transaction distribution +system.membus.trans_dist::ReadResp 179848 # Transaction distribution +system.membus.trans_dist::Writeback 294030 # Transaction distribution +system.membus.trans_dist::UpgradeReq 180174 # Transaction distribution +system.membus.trans_dist::UpgradeResp 180174 # Transaction distribution +system.membus.trans_dist::ReadExReq 207029 # Transaction distribution +system.membus.trans_dist::ReadExResp 207029 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 861081 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 861081 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 861081 # Request fanout histogram +system.membus.reqLayer0.occupancy 3467092000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3996161130 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index ca5c08420..fd544a1a5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.226819 # Nu sim_ticks 226818771000 # Number of ticks simulated final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 285609 # Simulator instruction rate (inst/s) -host_op_rate 285609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162496290 # Simulator tick rate (ticks/s) -host_mem_usage 242892 # Number of bytes of host memory used -host_seconds 1395.84 # Real time elapsed on the host +host_inst_rate 333141 # Simulator instruction rate (inst/s) +host_op_rate 333141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189539219 # Simulator tick rate (ticks/s) +host_mem_usage 300760 # Number of bytes of host memory used +host_seconds 1196.69 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # By system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 50615750 # Total ticks spent queuing -system.physmem.totMemAccLat 198234500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 50610250 # Total ticks spent queuing +system.physmem.totMemAccLat 198229000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6429.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6428.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25179.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25178.33 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s @@ -218,36 +218,41 @@ system.physmem.readRowHitRate 80.54 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28809690.02 # Average gap between requests system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 217525128250 # Time in different power states -system.physmem.memoryStateTime::REF 7573800000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1714919250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6698160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4808160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3654750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2623500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 34164000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 26910000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5823022815 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5572463355 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 130980318750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 131200107750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 151662211275 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 151621265565 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.664178 # Core power per rank (mW) -system.physmem.averagePower::1 668.483652 # Core power per rank (mW) -system.cpu.branchPred.lookups 46273762 # Number of BP lookups +system.physmem_0.actEnergy 6698160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3654750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5823127980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130980226500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151662224190 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.664235 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217898379000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1344256000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4808160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2623500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5572496700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 131200078500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151621269660 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.483670 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 218263346500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 976701000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 46273761 # Number of BP lookups system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25595417 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25595416 # Number of BTB lookups system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.452221 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 83.452224 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -293,15 +298,15 @@ system.cpu.discardedOps 4467797 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.137893 # CPI: cycles per instruction system.cpu.ipc 0.878818 # IPC: instructions per cycle -system.cpu.tickCycles 450174331 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3463211 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 450174327 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3463215 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.955317 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3291.955330 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955317 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955330 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id @@ -329,14 +334,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7119 # n system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81052500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81052500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391543250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 391543250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 472595750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 472595750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 472595750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 472595750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81009750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391587500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 472597250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 472597250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) @@ -353,14 +358,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68630.397968 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68630.397968 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65938.573594 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65938.573594 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66385.131339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66385.131339 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68594.199831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65946.025598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,14 +392,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64327500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64327500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214316000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 214316000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278643500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278643500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278643500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278643500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64296000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214342750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278638750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278638750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -403,22 +408,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66317.010309 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66317.010309 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67078.560250 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67078.560250 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66901.200480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66901.200480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66901.200480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66901.200480 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66284.536082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67086.932707 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.781810 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1918.781818 # Cycle average of tags in use system.cpu.icache.tags.total_refs 98776054 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19090.849246 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781810 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781818 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.936905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.936905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id @@ -441,12 +446,12 @@ system.cpu.icache.demand_misses::cpu.inst 5174 # n system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses system.cpu.icache.overall_misses::total 5174 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293010500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293010500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293010500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293010500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293010500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293010500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293011250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293011250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293011250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293011250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293011250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293011250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 98781228 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 98781228 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 98781228 # number of demand (read+write) accesses @@ -459,12 +464,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.329726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56631.329726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.329726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56631.329726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.329726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56631.329726 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.474681 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56631.474681 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56631.474681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56631.474681 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,33 +484,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5174 system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281053500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281053500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281053500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281053750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281053750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281053750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.351759 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.351759 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.351759 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.351759 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.351759 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.351759 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.400077 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.400077 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.924710 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4426.924727 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.138333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786377 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786392 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123712 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy @@ -535,14 +540,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7873 # system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7873 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324986750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 324986750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210671750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 210671750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 535658500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 535658500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 535658500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 535658500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324955500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210698500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 535654000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 535654000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) @@ -561,14 +566,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843024 system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843024 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68620.513091 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68620.513091 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67157.076825 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67157.076825 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68037.406325 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68037.406325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68037.406325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68037.406325 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.914696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67165.604080 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,14 +590,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7873 system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7873 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265636250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265636250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 170998250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 170998250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436634500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 436634500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436634500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 436634500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 171025500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436627500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980926 # mshr miss rate for ReadExReq accesses @@ -601,14 +606,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843024 system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56088.735220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56088.735220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54510.121135 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54510.121135 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56081.503378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54518.807778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution @@ -635,9 +640,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8565750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6972750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4736 # Transaction distribution system.membus.trans_dist::ReadResp 4736 # Transaction distribution @@ -660,7 +665,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 7873 # Request fanout histogram system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73875500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 73877500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 52c9c0408..90aeffe97 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.069652 # Nu sim_ticks 69651704000 # Number of ticks simulated final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274902 # Simulator instruction rate (inst/s) -host_op_rate 274902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50981523 # Simulator tick rate (ticks/s) -host_mem_usage 244336 # Number of bytes of host memory used -host_seconds 1366.21 # Real time elapsed on the host +host_inst_rate 253977 # Simulator instruction rate (inst/s) +host_op_rate 253977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47101012 # Simulator tick rate (ticks/s) +host_mem_usage 302288 # Number of bytes of host memory used +host_seconds 1478.77 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 915 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see @@ -188,24 +188,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.823320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.868335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 424 31.34% 31.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 330 24.39% 55.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 151 11.16% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 84 6.21% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.99% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 42 3.10% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 39 2.88% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.904608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.764111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 423 31.26% 31.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 330 24.39% 55.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 152 11.23% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 83 6.13% 73.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 55 4.07% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 3.18% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 38 2.81% 83.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation -system.physmem.totQLat 66704750 # Total ticks spent queuing -system.physmem.totMemAccLat 206542250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 67034750 # Total ticks spent queuing +system.physmem.totMemAccLat 206872250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8944.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8988.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27694.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27738.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s @@ -222,82 +222,64 @@ system.physmem.readRowHitRate 81.74 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9339181.35 # Average gap between requests system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 66207575500 # Time in different power states -system.physmem.memoryStateTime::REF 2325700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 5843880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4362120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3188625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2380125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 32385600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 25373400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2090120175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1977791130 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 39955521000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 40054055250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 46636128480 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 46613031225 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.594966 # Core power per rank (mW) -system.physmem.averagePower::1 669.263339 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4328 # Transaction distribution -system.membus.trans_dist::ReadResp 4328 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7458 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7458 # Request fanout histogram -system.membus.reqLayer0.occupancy 9424000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69710500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 51167476 # Number of BP lookups +system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32385600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2090226195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 39955428000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46636141500 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.595153 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66468117000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 855864000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25373400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1978191270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40053704250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46613080365 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.264045 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66630949750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 691630250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 51167471 # Number of BP lookups system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25804997 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25804996 # Number of BTB lookups system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.459026 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9351095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.459030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9351091 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103696201 # DTB read hits +system.cpu.dtb.read_hits 103696202 # DTB read hits system.cpu.dtb.read_misses 91462 # DTB read misses system.cpu.dtb.read_acv 49407 # DTB read access violations -system.cpu.dtb.read_accesses 103787663 # DTB read accesses +system.cpu.dtb.read_accesses 103787664 # DTB read accesses system.cpu.dtb.write_hits 79414480 # DTB write hits system.cpu.dtb.write_misses 1579 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations system.cpu.dtb.write_accesses 79416059 # DTB write accesses -system.cpu.dtb.data_hits 183110681 # DTB hits +system.cpu.dtb.data_hits 183110682 # DTB hits system.cpu.dtb.data_misses 93041 # DTB misses system.cpu.dtb.data_acv 49409 # DTB access violations -system.cpu.dtb.data_accesses 183203722 # DTB accesses -system.cpu.itb.fetch_hits 51277823 # ITB hits +system.cpu.dtb.data_accesses 183203723 # DTB accesses +system.cpu.itb.fetch_hits 51277820 # ITB hits system.cpu.itb.fetch_misses 422 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51278245 # ITB accesses +system.cpu.itb.fetch_accesses 51278242 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -314,57 +296,57 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 139303411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52063861 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85692225 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 52063926 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 457094521 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51167471 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32952090 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85692281 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139036455 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287588 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 51277820 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 545278 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139036576 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58307210 41.94% 41.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58307337 41.94% 41.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4519216 3.25% 45.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11970287 8.61% 63.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11970286 8.61% 63.02% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5933035 4.27% 73.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5933032 4.27% 73.06% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35575530 25.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139036455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 139036576 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45112319 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16348091 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking +system.cpu.fetch.rate 3.281287 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45112383 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16348146 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71787003 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4526860 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode +system.cpu.decode.SquashedInsts 14196 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47010962 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5663544 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 518995 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10271556 # Number of cycles rename is unblocking +system.cpu.rename.IdleCycles 47011024 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5663526 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74309218 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10271511 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3600572 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 3600527 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups @@ -373,35 +355,35 @@ system.cpu.rename.CommittedMaps 259532329 # Nu system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 16173803 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 16173797 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 406915916 # Number of instructions issued +system.cpu.iq.iqInstsIssued 406915918 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 18208107 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139036455 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.926685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.221928 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 139036576 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.926683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891375 17.18% 17.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19616672 14.11% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22677489 16.31% 47.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891494 17.18% 17.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19616678 14.11% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22677483 16.31% 47.60% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14153870 10.18% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9626407 6.92% 92.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14153871 10.18% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9626410 6.92% 92.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6209797 4.47% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4351187 3.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139036455 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139036576 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available @@ -437,7 +419,7 @@ system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153207489 37.65% 37.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153207490 37.65% 37.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued @@ -466,21 +448,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105367867 25.89% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105367868 25.89% 80.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 406915916 # Type of FU issued +system.cpu.iq.FU_type_0::total 406915918 # Type of FU issued system.cpu.iq.rate 2.921076 # Inst issue rate system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 625896924 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 625897049 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 237228631 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246150912 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 246150914 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -491,35 +473,35 @@ system.cpu.iew.lsq.thread0.squashedStores 8146657 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 139208 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 131709 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 131691 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403157734 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103837101 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 403157736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103837102 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 24979489 # number of nop insts executed -system.cpu.iew.exec_refs 183253197 # number of memory reference insts executed -system.cpu.iew.exec_branches 46959988 # Number of branches executed +system.cpu.iew.exec_refs 183253198 # number of memory reference insts executed +system.cpu.iew.exec_branches 46959989 # Number of branches executed system.cpu.iew.exec_stores 79416096 # Number of stores executed system.cpu.iew.exec_rate 2.894098 # Inst execution rate -system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198000445 # num instructions producing a value -system.cpu.iew.wb_consumers 283955599 # num instructions consuming a value +system.cpu.iew.wb_sent 401401507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400567896 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198000452 # num instructions producing a value +system.cpu.iew.wb_consumers 283955606 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back @@ -527,23 +509,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133310602 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.990494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 133310723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.990491 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48555591 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18055922 13.54% 49.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9630864 7.22% 57.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48555712 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18055923 13.54% 49.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8737322 6.55% 63.75% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2616133 1.96% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29895302 22.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4404759 3.30% 71.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4988493 3.74% 75.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2616131 1.96% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133310602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133310723 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -589,60 +571,152 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29895302 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 542988978 # The number of ROB reads +system.cpu.rob.rob_reads 542989097 # The number of ROB reads system.cpu.rob.rob_writes 884890973 # The number of ROB writes -system.cpu.timesIdled 3472 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 266956 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 3476 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 266835 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403240144 # number of integer regfile reads -system.cpu.int_regfile_writes 171897287 # number of integer regfile writes +system.cpu.int_regfile_reads 403240146 # number of integer regfile reads +system.cpu.int_regfile_writes 171897288 # number of integer regfile writes system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6787000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6700000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 798 # number of replacements +system.cpu.dcache.tags.tagsinuse 3297.113166 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113166 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits +system.cpu.dcache.overall_hits::total 156873469 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses +system.cpu.dcache.overall_misses::total 21715 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114608500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114608500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125293584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1125293584 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239902084 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239902084 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239902084 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239902084 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62902.579583 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62902.579583 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56567.314332 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56567.314332 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57098.875616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57098.875616 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46396 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.044397 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 674 # number of writebacks +system.cpu.dcache.writebacks::total 674 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67693000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67693000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235962750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 235962750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303655750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 303655750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67828.657315 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67828.657315 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73669.294411 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73669.294411 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2164 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.364308 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1832.364532 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51272141 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12532.911513 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364308 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364532 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id @@ -651,44 +725,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 167 system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 102559737 # Number of tag accesses -system.cpu.icache.tags.data_accesses 102559737 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 51272145 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 51272145 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 51272145 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 51272145 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 51272145 # number of overall hits -system.cpu.icache.overall_hits::total 51272145 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5678 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5678 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5678 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses -system.cpu.icache.overall_misses::total 5678 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 340036249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 340036249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 340036249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 340036249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 340036249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 340036249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 51277823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 51277823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 51277823 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 102559731 # Number of tag accesses +system.cpu.icache.tags.data_accesses 102559731 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 51272141 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 51272141 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 51272141 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 51272141 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 51272141 # number of overall hits +system.cpu.icache.overall_hits::total 51272141 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5679 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5679 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5679 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5679 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5679 # number of overall misses +system.cpu.icache.overall_misses::total 5679 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 341090499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 341090499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 341090499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 341090499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 341090499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 341090499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 51277820 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 51277820 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 51277820 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 51277820 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 51277820 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 51277820 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000111 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000111 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59886.623635 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59886.623635 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59886.623635 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59886.623635 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60061.718436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60061.718436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60061.718436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60061.718436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -697,46 +771,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1587 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1587 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1587 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1587 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1587 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1587 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1588 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1588 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1588 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1588 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1588 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1588 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4091 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 250258250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250258250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 250258250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250258250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 250258250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61100.586654 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61100.586654 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61172.879492 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61172.879492 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4021.632026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4021.632512 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.133812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.662944 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835269 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.133834 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.663344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835334 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy @@ -773,17 +847,17 @@ system.cpu.l2cache.demand_misses::total 7458 # nu system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses system.cpu.l2cache.overall_misses::total 7458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239571000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65252750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 304823750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231908750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 231908750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239571000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 297161500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 536732500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 239571000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 297161500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 536732500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239866750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65282000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 305148750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231929750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 231929750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 239866750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 297211750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 537078500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 239866750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 297211750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 537078500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses) @@ -808,17 +882,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.899421 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69200.173310 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75349.595843 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70430.626155 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74092.252396 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74092.252396 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71967.350496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71967.350496 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69285.600809 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75383.371824 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70505.718577 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74098.961661 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74098.961661 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72013.743631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72013.743631 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,17 +912,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7458 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195687500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54580750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250268250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193330750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193330750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195687500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247911500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 443599000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195687500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247911500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 443599000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195982250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54610500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250592750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193350250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193350250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195982250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247960750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 443943000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195982250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247960750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 443943000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses @@ -860,138 +934,69 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56524.407857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63026.270208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57825.381238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61767.012780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61767.012780 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56609.546505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63060.623557 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.358133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61773.242812 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61773.242812 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 798 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.113011 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113011 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits -system.cpu.dcache.overall_hits::total 156873469 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses -system.cpu.dcache.overall_misses::total 21715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114579750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114579750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125182835 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1125182835 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239762585 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239762585 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239762585 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239762585 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62886.800220 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62886.800220 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56561.747097 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56561.747097 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57092.451531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57092.451531 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46428 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 947 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.026399 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 674 # number of writebacks -system.cpu.dcache.writebacks::total 674 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67663750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67663750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235941750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 235941750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303605500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 303605500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303605500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 303605500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67799.348697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67799.348697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73662.738058 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73662.738058 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6700250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4328 # Transaction distribution +system.membus.trans_dist::ReadResp 4328 # Transaction distribution +system.membus.trans_dist::ReadExReq 3130 # Transaction distribution +system.membus.trans_dist::ReadExResp 3130 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7458 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7458 # Request fanout histogram +system.membus.reqLayer0.occupancy 9422500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 69712000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index a544f3c3c..d0b9d8c3b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.216828 # Nu sim_ticks 216828260500 # Number of ticks simulated final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172164 # Simulator instruction rate (inst/s) -host_op_rate 206702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136721287 # Simulator tick rate (ticks/s) -host_mem_usage 262128 # Number of bytes of host memory used -host_seconds 1585.91 # Real time elapsed on the host +host_inst_rate 175239 # Simulator instruction rate (inst/s) +host_op_rate 210394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139163086 # Simulator tick rate (ticks/s) +host_mem_usage 320864 # Number of bytes of host memory used +host_seconds 1558.09 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -184,24 +184,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.317321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.826076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 548 36.41% 36.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 349 23.19% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 163 10.83% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.58% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 60 3.99% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.19% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 50683250 # Total ticks spent queuing -system.physmem.totMemAccLat 192902000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 50845500 # Total ticks spent queuing +system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6682.04 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25432.04 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 80.07 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28586424.65 # Average gap between requests system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 207228229000 # Time in different power states -system.physmem.memoryStateTime::REF 7240220000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 2356912000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 5012280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 6342840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2734875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3460875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 29905200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 29000400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5651949285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5745162240 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 125136528000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 125054762250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 144987999960 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 145000598925 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.689925 # Core power per rank (mW) -system.physmem.averagePower::1 668.748031 # Core power per rank (mW) +system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.690273 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.748242 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 33221230 # Number of BP lookups system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 87.059638 # BT system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -345,15 +382,15 @@ system.cpu.discardedOps 4064410 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.588265 # CPI: cycles per instruction system.cpu.ipc 0.629618 # IPC: instructions per cycle -system.cpu.tickCycles 430211091 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3445430 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.009332 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009488 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -385,14 +422,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7290 # n system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126122956 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 126122956 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360338500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 360338500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 486461456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486461456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 486461456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486461456 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126489706 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360451750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486941456 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486941456 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) @@ -413,14 +450,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66729.966529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66729.966529 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61313.478429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68959.584848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,14 +484,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 99847542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 99847542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197786250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197786250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297633792 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 297633792 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297633792 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 297633792 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100259792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197855250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298115042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses @@ -463,22 +500,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61096.765387 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68939.111498 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36927 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.993605 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73270396 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1885.302491 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993605 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -488,44 +525,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146657386 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146657386 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73270396 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73270396 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73270396 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73270396 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73270396 # number of overall hits -system.cpu.icache.overall_hits::total 73270396 # number of overall hits +system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits +system.cpu.icache.overall_hits::total 73270394 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses system.cpu.icache.overall_misses::total 38865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 703294747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 703294747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 703294747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 703294747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 703294747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 703294747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73309261 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73309261 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73309261 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73309261 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73309261 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73309261 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18095.838081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18095.838081 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,33 +577,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38865 system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624165253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 624165253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624165253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 624165253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624165253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 624165253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624088753 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 624088753 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624088753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 624088753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624088753 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 624088753 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4198.559652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4198.559801 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.760812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798840 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798959 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy @@ -597,14 +634,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7630 # system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7630 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326194750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 326194750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194720750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 194720750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 520915500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 520915500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 520915500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 520915500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326530500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194789750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 521320250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 521320250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) @@ -623,14 +660,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68369.032663 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68251.489138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,14 +690,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264387500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264387500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158755250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158755250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423142750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 423142750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423142750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 423142750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264479250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158825750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423305000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses @@ -669,14 +706,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55903.455929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55650.227751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution @@ -709,7 +746,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7500208 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4731 # Transaction distribution system.membus.trans_dist::ReadResp 4731 # Transaction distribution @@ -730,9 +767,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8963500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71030250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 784b1e77a..2e0077bb1 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112541 # Number of seconds simulated -sim_ticks 112540655000 # Number of ticks simulated -final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112624 # Number of seconds simulated +sim_ticks 112623767500 # Number of ticks simulated +final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132153 # Simulator instruction rate (inst/s) -host_op_rate 158665 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54470958 # Simulator tick rate (ticks/s) -host_mem_usage 270904 # Number of bytes of host memory used -host_seconds 2066.07 # Real time elapsed on the host +host_inst_rate 123996 # Simulator instruction rate (inst/s) +host_op_rate 148871 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51146556 # Simulator tick rate (ticks/s) +host_mem_usage 325020 # Number of bytes of host memory used +host_seconds 2201.98 # Real time elapsed on the host sim_insts 273037219 # Number of instructions simulated sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory -system.physmem.bytes_read::total 623680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 9745 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory +system.physmem.bytes_read::total 469120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7330 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side +system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 803 # Per bank write bursts -system.physmem.perBankRdBursts::1 999 # Per bank write bursts -system.physmem.perBankRdBursts::2 769 # Per bank write bursts -system.physmem.perBankRdBursts::3 645 # Per bank write bursts -system.physmem.perBankRdBursts::4 618 # Per bank write bursts -system.physmem.perBankRdBursts::5 484 # Per bank write bursts -system.physmem.perBankRdBursts::6 251 # Per bank write bursts -system.physmem.perBankRdBursts::7 363 # Per bank write bursts -system.physmem.perBankRdBursts::8 300 # Per bank write bursts -system.physmem.perBankRdBursts::9 432 # Per bank write bursts -system.physmem.perBankRdBursts::10 486 # Per bank write bursts -system.physmem.perBankRdBursts::11 534 # Per bank write bursts -system.physmem.perBankRdBursts::12 696 # Per bank write bursts -system.physmem.perBankRdBursts::13 850 # Per bank write bursts -system.physmem.perBankRdBursts::14 782 # Per bank write bursts -system.physmem.perBankRdBursts::15 733 # Per bank write bursts +system.physmem.perBankRdBursts::0 589 # Per bank write bursts +system.physmem.perBankRdBursts::1 789 # Per bank write bursts +system.physmem.perBankRdBursts::2 601 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::4 444 # Per bank write bursts +system.physmem.perBankRdBursts::5 346 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::8 219 # Per bank write bursts +system.physmem.perBankRdBursts::9 291 # Per bank write bursts +system.physmem.perBankRdBursts::10 316 # Per bank write bursts +system.physmem.perBankRdBursts::11 411 # Per bank write bursts +system.physmem.perBankRdBursts::12 547 # Per bank write bursts +system.physmem.perBankRdBursts::13 678 # Per bank write bursts +system.physmem.perBankRdBursts::14 615 # Per bank write bursts +system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112540488500 # Total gap between requests +system.physmem.totGap 112623613500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 9745 # Read request sizes (log2) +system.physmem.readPktSize::6 7330 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,100 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation -system.physmem.totQLat 248191131 # Total ticks spent queuing -system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation +system.physmem.totQLat 100359280 # Total ticks spent queuing +system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 8500 # Number of row buffer hits during reads +system.physmem.readRowHits 5950 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 11548536.53 # Average gap between requests -system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states -system.physmem.memoryStateTime::REF 3757780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 4460400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4845960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2433750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2644125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 38220000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 37221600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 7350217680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 7350217680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 3071428470 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3094710975 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 64826723250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 64806300000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 75293483550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 75295940340 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.067664 # Core power per rank (mW) -system.physmem.averagePower::1 669.089495 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 9170 # Transaction distribution -system.membus.trans_dist::ReadResp 9170 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 575 # Transaction distribution -system.membus.trans_dist::ReadExResp 575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9746 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9746 # Request fanout histogram -system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 37763717 # Number of BP lookups -system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits +system.physmem.avgGap 15364749.45 # Average gap between requests +system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.161673 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states +system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.228880 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states +system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 37762202 # Number of BP lookups +system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -305,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -326,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -347,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -369,96 +381,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225081311 # number of cpu cycles simulated +system.cpu.numCycles 225247536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3511517 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available @@ -477,22 +488,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued @@ -511,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued -system.cpu.iq.rate 1.538412 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued +system.cpu.iq.rate 1.537271 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 864 # number of nop insts executed -system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752179 # Number of branches executed -system.cpu.iew.exec_stores 84582729 # Number of stores executed -system.cpu.iew.exec_rate 1.520806 # Inst execution rate -system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153543382 # num instructions producing a value -system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value +system.cpu.iew.exec_nop 868 # number of nop insts executed +system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752029 # Number of branches executed +system.cpu.iew.exec_stores 84582492 # Number of stores executed +system.cpu.iew.exec_rate 1.519678 # Inst execution rate +system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153542130 # num instructions producing a value +system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle +system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037831 # Number of instructions committed system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -643,489 +654,155 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction -system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 561656707 # The number of ROB reads -system.cpu.rob.rob_writes 705358339 # The number of ROB writes -system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 561683936 # The number of ROB reads +system.cpu.rob.rob_writes 705354391 # The number of ROB writes +system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037219 # Number of Instructions Simulated system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads -system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331187240 # number of integer regfile reads -system.cpu.int_regfile_writes 136909181 # number of integer regfile writes -system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads -system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes -system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads -system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads +system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads +system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331186150 # number of integer regfile reads +system.cpu.int_regfile_writes 136908474 # number of integer regfile writes +system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads +system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes +system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads +system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 50213 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 715368 # number of replacements -system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits -system.cpu.icache.overall_hits::total 88391816 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses -system.cpu.icache.overall_misses::total 719790 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 44298 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 135685 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 8320.579960 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2794148 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 9718 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 287.522947 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2574.248018 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 441.129211 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 367.415546 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4937.787185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157120 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026924 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.022425 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.301379 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.507848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 5676 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4042 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 572 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4961 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3234 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.346436 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.246704 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51678510 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51678510 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 714431 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1313042 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2027473 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 966282 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 966282 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219797 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219797 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 714431 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1532839 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2247270 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 714431 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1532839 # number of overall hits -system.cpu.l2cache.overall_hits::total 2247270 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 546 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 730 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1276 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 689 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 689 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 546 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1419 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1965 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 546 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1419 # number of overall misses -system.cpu.l2cache.overall_misses::total 1965 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38998499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50021748 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 89020247 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41954499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41954499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 38998499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 91976247 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 130974746 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 38998499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 91976247 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 130974746 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 714977 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1313772 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2028749 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 966282 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 966282 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 220486 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 220486 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 714977 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1534258 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2249235 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 714977 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1534258 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2249235 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000764 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000556 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000629 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003125 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003125 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000764 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000874 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000764 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000874 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71425.822344 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68522.942466 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69765.083856 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60891.870827 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60891.870827 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66653.814758 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66653.814758 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 6173 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 209 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.535885 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 114 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 114 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 157 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 157 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 225 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 478 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 687 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1165 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 44298 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 44298 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 575 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 478 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1262 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 478 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1262 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 44298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 46038 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32592250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42691498 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75283748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 669707182 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34465750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34465750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32592250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77157248 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 109749498 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32592250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77157248 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 779456680 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.002608 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.002608 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000774 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.020468 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1533746 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533739 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits -system.cpu.dcache.overall_hits::total 163781573 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits +system.cpu.dcache.overall_hits::total 163782096 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses -system.cpu.dcache.overall_misses::total 3771680 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses +system.cpu.dcache.overall_misses::total 3771380 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks -system.cpu.dcache.writebacks::total 966282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks +system.cpu.dcache.writebacks::total 966281 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313753 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220489 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220489 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534242 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534253 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534253 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9313835285 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9313835285 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1599508327 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1599508327 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 613250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 613250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10913343612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10913343612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10913956862 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10913956862 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses @@ -1136,16 +813,372 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7089.487358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7089.487358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7254.367914 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7254.367914 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 55750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55750 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7113.182674 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7113.182674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7113.531381 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7113.531381 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 715275 # number of replacements +system.cpu.icache.tags.tagsinuse 511.840362 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88389408 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 715787 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.485629 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 315060000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.840362 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999688 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999688 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 68 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 178935006 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178935006 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88389408 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88389408 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88389408 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88389408 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88389408 # number of overall hits +system.cpu.icache.overall_hits::total 88389408 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 720201 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 720201 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 720201 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 720201 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 720201 # number of overall misses +system.cpu.icache.overall_misses::total 720201 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5943843584 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5943843584 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5943843584 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5943843584 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5943843584 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5943843584 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89109609 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89109609 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89109609 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89109609 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89109609 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89109609 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008082 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008082 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008082 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008082 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008082 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008082 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8253.034339 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8253.034339 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8253.034339 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8253.034339 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 33002 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 6603 # Transaction distribution +system.membus.trans_dist::ReadResp 6603 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 727 # Transaction distribution +system.membus.trans_dist::ReadExResp 727 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7331 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7331 # Request fanout histogram +system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 607680a6d..8e74d72ee 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717313500 # Number of ticks simulated final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1306299 # Simulator instruction rate (inst/s) -host_op_rate 1568357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 965080142 # Simulator tick rate (ticks/s) -host_mem_usage 305108 # Number of bytes of host memory used -host_seconds 209.02 # Real time elapsed on the host +host_inst_rate 1117455 # Simulator instruction rate (inst/s) +host_op_rate 1341629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 825564009 # Simulator tick rate (ticks/s) +host_mem_usage 308812 # Number of bytes of host memory used +host_seconds 244.34 # Real time elapsed on the host sim_insts 273037594 # Number of instructions simulated sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1983209850 # Wr system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 434895827 # Transaction distribution -system.membus.trans_dist::ReadResp 434906722 # Transaction distribution -system.membus.trans_dist::WriteReq 82052672 # Transaction distribution -system.membus.trans_dist::WriteResp 82052672 # Transaction distribution -system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution -system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution -system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution -system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 517024351 # Request fanout histogram -system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 517024351 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812144 # Class of executed instruction +system.membus.trans_dist::ReadReq 434895827 # Transaction distribution +system.membus.trans_dist::ReadResp 434906722 # Transaction distribution +system.membus.trans_dist::WriteReq 82052672 # Transaction distribution +system.membus.trans_dist::WriteResp 82052672 # Transaction distribution +system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution +system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 517024351 # Request fanout histogram +system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 517024351 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 09b69e575..c39fe9424 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517235 # Nu sim_ticks 517235411000 # Number of ticks simulated final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 795879 # Simulator instruction rate (inst/s) -host_op_rate 955482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1509341441 # Simulator tick rate (ticks/s) -host_mem_usage 314596 # Number of bytes of host memory used -host_seconds 342.69 # Real time elapsed on the host +host_inst_rate 761441 # Simulator instruction rate (inst/s) +host_op_rate 914138 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1444030997 # Simulator tick rate (ticks/s) +host_mem_usage 318052 # Number of bytes of host memory used +host_seconds 358.19 # Real time elapsed on the host sim_insts 272739285 # Number of instructions simulated sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 322824 # In system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3976 # Transaction distribution -system.membus.trans_dist::ReadResp 3976 # Transaction distribution -system.membus.trans_dist::ReadExReq 2856 # Transaction distribution -system.membus.trans_dist::ReadExResp 2856 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6833 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,145 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812213 # Class of executed instruction +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 998 # number of writebacks +system.cpu.dcache.writebacks::total 998 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. @@ -430,145 +578,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits -system.cpu.dcache.overall_hits::total 168337827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses -system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 998 # number of writebacks -system.cpu.dcache.writebacks::total 998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution @@ -602,5 +611,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3976 # Transaction distribution +system.membus.trans_dist::ReadResp 3976 # Transaction distribution +system.membus.trans_dist::ReadExReq 2856 # Transaction distribution +system.membus.trans_dist::ReadExResp 2856 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6833 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6833 # Request fanout histogram +system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 3373b2092..896e43907 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.559967 # Number of seconds simulated -sim_ticks 559966999500 # Number of ticks simulated -final_tick 559966999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.559962 # Number of seconds simulated +sim_ticks 559961514500 # Number of ticks simulated +final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 393705 # Simulator instruction rate (inst/s) -host_op_rate 393705 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237364888 # Simulator tick rate (ticks/s) -host_mem_usage 245892 # Number of bytes of host memory used -host_seconds 2359.10 # Real time elapsed on the host +host_inst_rate 343254 # Simulator instruction rate (inst/s) +host_op_rate 343254 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206945650 # Simulator tick rate (ticks/s) +host_mem_usage 305268 # Number of bytes of host memory used +host_seconds 2705.84 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,33 +23,33 @@ system.physmem.num_reads::cpu.inst 291519 # Nu system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33318421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33318421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7621363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7621363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7621363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33318421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40939784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33318747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17280 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 270 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 17935 # Per bank write bursts system.physmem.perBankRdBursts::1 18289 # Per bank write bursts system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18248 # Per bank write bursts -system.physmem.perBankRdBursts::4 18163 # Per bank write bursts -system.physmem.perBankRdBursts::5 18239 # Per bank write bursts +system.physmem.perBankRdBursts::3 18250 # Per bank write bursts +system.physmem.perBankRdBursts::4 18167 # Per bank write bursts +system.physmem.perBankRdBursts::5 18240 # Per bank write bursts system.physmem.perBankRdBursts::6 18320 # Per bank write bursts system.physmem.perBankRdBursts::7 18299 # Per bank write bursts system.physmem.perBankRdBursts::8 18230 # Per bank write bursts @@ -59,7 +59,7 @@ system.physmem.perBankRdBursts::11 18391 # Pe system.physmem.perBankRdBursts::12 18259 # Per bank write bursts system.physmem.perBankRdBursts::13 18042 # Per bank write bursts system.physmem.perBankRdBursts::14 17977 # Per bank write bursts -system.physmem.perBankRdBursts::15 18106 # Per bank write bursts +system.physmem.perBankRdBursts::15 18101 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 559966923500 # Total gap between requests +system.physmem.totGap 559961438500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.912664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.833166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 269.609760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39535 37.79% 37.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43904 41.96% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8672 8.29% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 695 0.66% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 728 0.70% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 763 0.73% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1332 1.27% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 808 0.77% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8193 7.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.196437 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.192949 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.958027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes @@ -221,12 +221,12 @@ system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Wr system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2990654250 # Total ticks spent queuing -system.physmem.totMemAccLat 8451573000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10268.38 # Average queueing delay per DRAM burst +system.physmem.totQLat 2985206750 # Total ticks spent queuing +system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29018.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s @@ -237,35 +237,40 @@ system.physmem.busUtilRead 0.26 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 202814 # Number of row buffer hits during reads -system.physmem.writeRowHits 50461 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 1563271.35 # Average gap between requests -system.physmem.pageHitRate 70.76 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275670988500 # Time in different power states -system.physmem.memoryStateTime::REF 18698420000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 265594606500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 393989400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 396952920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 214974375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 216591375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136974800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1134400800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215550720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 36574109520 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 36574109520 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 108415975050 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 108760602465 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 240876668250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 240574363500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 387829129875 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 387872571300 # Total energy per rank (pJ) -system.physmem.averagePower::0 692.596540 # Core power per rank (mW) -system.physmem.averagePower::1 692.674119 # Core power per rank (mW) +system.physmem.readRowHits 202789 # Number of row buffer hits during reads +system.physmem.writeRowHits 50437 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgGap 1563256.04 # Average gap between requests +system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.597962 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states +system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.677886 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 125749069 # Number of BP lookups system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect @@ -309,24 +314,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1119933999 # number of cpu cycles simulated +system.cpu.numCycles 1119923029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.205800 # CPI: cycles per instruction -system.cpu.ipc 0.829325 # IPC: instructions per cycle -system.cpu.tickCycles 1060170405 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59763594 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.205788 # CPI: cycles per instruction +system.cpu.ipc 0.829333 # IPC: instructions per cycle +system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.890193 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890165 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -354,14 +359,14 @@ system.cpu.dcache.demand_misses::cpu.inst 849082 # n system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 849082 # number of overall misses system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23415653250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23415653250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9042894000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9042894000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32458547250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32458547250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32458547250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32458547250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32445902750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) @@ -378,14 +383,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002618 system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32890.433245 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32890.433245 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65932.892463 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65932.892463 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38227.812214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38227.812214 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32892.515616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65829.890706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,14 +417,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21914188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21914188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4452805750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4452805750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26366993750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26366993750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26366993750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26366993750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26361393250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses @@ -428,22 +433,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002407 system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30794.919177 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30794.919177 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64523.130371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64523.130371 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10606 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.447542 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447542 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id @@ -467,12 +472,12 @@ system.cpu.icache.demand_misses::cpu.inst 12350 # n system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses system.cpu.icache.overall_misses::total 12350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333735500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333735500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333735500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333735500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 333735500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 333735500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 333924000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 333924000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 333924000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses @@ -485,12 +490,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27023.117409 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27023.117409 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27023.117409 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27023.117409 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27038.380567 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27038.380567 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27038.380567 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27038.380567 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,41 +510,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12350 system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 307779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 307779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307779500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 307779500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307968000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 307968000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307968000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 307968000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307968000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 307968000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24921.417004 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24921.417004 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24936.680162 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24936.680162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 258740 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32601.453126 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32601.451844 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 523849 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2865.906217 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.546909 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2865.934205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.517639 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2657 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses @@ -562,14 +567,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 291520 # system.cpu.l2cache.demand_misses::total 291520 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 291520 # number of overall misses system.cpu.l2cache.overall_misses::total 291520 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16507068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16507068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4360106750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4360106750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20867174750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20867174750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20867174750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20867174750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20861762750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20861762750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) @@ -588,14 +593,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367627 system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367627 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73405.527515 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73405.527515 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65422.863681 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65422.863681 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71580.593956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71580.593956 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,14 +619,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 291520 system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 291520 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13668599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13668599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3526847250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3526847250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17195446750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17195446750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17195446750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17195446750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17190059750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965716 # mshr miss rate for ReadExReq accesses @@ -630,14 +635,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367627 system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60783.099500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60783.099500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52919.907720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52919.907720 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution @@ -666,7 +671,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # La system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222199250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution @@ -688,9 +693,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 975509000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2745284750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index ce136ba27..8cb1b2d37 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.278139 # Number of seconds simulated -sim_ticks 278139424500 # Number of ticks simulated -final_tick 278139424500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.278180 # Number of seconds simulated +sim_ticks 278180234500 # Number of ticks simulated +final_tick 278180234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197644 # Simulator instruction rate (inst/s) -host_op_rate 197644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65258345 # Simulator tick rate (ticks/s) -host_mem_usage 248388 # Number of bytes of host memory used -host_seconds 4262.13 # Real time elapsed on the host +host_inst_rate 185742 # Simulator instruction rate (inst/s) +host_op_rate 185742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61337566 # Simulator tick rate (ticks/s) +host_mem_usage 305284 # Number of bytes of host memory used +host_seconds 4535.23 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 175680 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18477184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18653120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18652864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 175680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 175680 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2745 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 288706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291451 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 632546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66431374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67063920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 632546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 632546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15343787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15343787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15343787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 632546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66431374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82407706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291455 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 631533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66421628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67053161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15341536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15341536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15341536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66421628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82394697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291451 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291451 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18634176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18944 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18653120 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18633536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652864 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 296 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17915 # Per bank write bursts -system.physmem.perBankRdBursts::1 18264 # Per bank write bursts -system.physmem.perBankRdBursts::2 18305 # Per bank write bursts -system.physmem.perBankRdBursts::3 18245 # Per bank write bursts -system.physmem.perBankRdBursts::4 18154 # Per bank write bursts -system.physmem.perBankRdBursts::5 18231 # Per bank write bursts -system.physmem.perBankRdBursts::6 18323 # Per bank write bursts -system.physmem.perBankRdBursts::7 18314 # Per bank write bursts -system.physmem.perBankRdBursts::8 18231 # Per bank write bursts -system.physmem.perBankRdBursts::9 18221 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18383 # Per bank write bursts -system.physmem.perBankRdBursts::12 18244 # Per bank write bursts -system.physmem.perBankRdBursts::13 18043 # Per bank write bursts -system.physmem.perBankRdBursts::14 17967 # Per bank write bursts -system.physmem.perBankRdBursts::15 18104 # Per bank write bursts +system.physmem.perBankRdBursts::0 17916 # Per bank write bursts +system.physmem.perBankRdBursts::1 18271 # Per bank write bursts +system.physmem.perBankRdBursts::2 18306 # Per bank write bursts +system.physmem.perBankRdBursts::3 18248 # Per bank write bursts +system.physmem.perBankRdBursts::4 18157 # Per bank write bursts +system.physmem.perBankRdBursts::5 18220 # Per bank write bursts +system.physmem.perBankRdBursts::6 18319 # Per bank write bursts +system.physmem.perBankRdBursts::7 18312 # Per bank write bursts +system.physmem.perBankRdBursts::8 18226 # Per bank write bursts +system.physmem.perBankRdBursts::9 18223 # Per bank write bursts +system.physmem.perBankRdBursts::10 18210 # Per bank write bursts +system.physmem.perBankRdBursts::11 18385 # Per bank write bursts +system.physmem.perBankRdBursts::12 18240 # Per bank write bursts +system.physmem.perBankRdBursts::13 18040 # Per bank write bursts +system.physmem.perBankRdBursts::14 17965 # Per bank write bursts +system.physmem.perBankRdBursts::15 18111 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::9 4187 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 278139341500 # Total gap between requests +system.physmem.totGap 278180151500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291455 # Read request sizes (log2) +system.physmem.readPktSize::6 291451 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 211494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 211637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,137 +193,118 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.952415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.081554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 279.010577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36030 35.87% 35.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42282 42.09% 77.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10217 10.17% 88.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 414 0.41% 88.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 384 0.38% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 317 0.32% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 757 0.75% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1270 1.26% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8780 8.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 100542 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.760100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.180809 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.034024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36066 35.87% 35.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42234 42.01% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10234 10.18% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 483 0.48% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 471 0.47% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 384 0.38% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 767 0.76% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1163 1.16% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8740 8.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100542 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.301854 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.144651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 769.722850 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.840049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.159268 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 778.757650 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.458498 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.856350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3077 76.07% 76.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 963 23.81% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.480346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.459004 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.856073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3075 76.02% 76.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 23.86% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 3340616250 # Total ticks spent queuing -system.physmem.totMemAccLat 8799847500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11473.51 # Average queueing delay per DRAM burst +system.physmem.totQLat 3369536750 # Total ticks spent queuing +system.physmem.totMemAccLat 8828580500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11573.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30223.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 67.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30323.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing -system.physmem.readRowHits 206977 # Number of row buffer hits during reads -system.physmem.writeRowHits 50379 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.55 # Row buffer hit rate for writes -system.physmem.avgGap 776626.17 # Average gap between requests -system.physmem.pageHitRate 71.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 74109656250 # Time in different power states -system.physmem.memoryStateTime::REF 9287460000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 194735825750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 377969760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 381175200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 206233500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 207982500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136124600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1133831400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215524800 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 18166271760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 18166271760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 79684218180 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79920417060 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 96981320250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 96774128250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 196768576530 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 196799330970 # Total energy per rank (pJ) -system.physmem.averagePower::0 707.462354 # Core power per rank (mW) -system.physmem.averagePower::1 707.572929 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 224829 # Transaction distribution -system.membus.trans_dist::ReadResp 224829 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66626 # Transaction distribution -system.membus.trans_dist::ReadExResp 66626 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649593 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649593 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22920832 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358138 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358138 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358138 # Request fanout histogram -system.membus.reqLayer0.occupancy 956225500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2708510750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 192497192 # Number of BP lookups -system.cpu.branchPred.condPredicted 125506208 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11891081 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 155386216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126898467 # Number of BTB hits +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 206912 # Number of row buffer hits during reads +system.physmem.writeRowHits 50353 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.51 # Row buffer hit rate for writes +system.physmem.avgGap 776748.79 # Average gap between requests +system.physmem.pageHitRate 71.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 378604800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 206580000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136756400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79832621385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96879153000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 196819477185 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.526603 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 160651755000 # Time in different power states +system.physmem_0.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108238852500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 381470040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 208143375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134088800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79968075615 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 96760333500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 196836972210 # Total energy per rank (pJ) +system.physmem_1.averagePower 707.589494 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 160452636750 # Time in different power states +system.physmem_1.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108437970750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 192516083 # Number of BP lookups +system.cpu.branchPred.condPredicted 125602202 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11889251 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 155393318 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126938973 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.666489 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 29014222 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.688823 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28938957 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244546246 # DTB read hits -system.cpu.dtb.read_misses 309763 # DTB read misses +system.cpu.dtb.read_hits 244535558 # DTB read hits +system.cpu.dtb.read_misses 309848 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244856009 # DTB read accesses -system.cpu.dtb.write_hits 135693142 # DTB write hits -system.cpu.dtb.write_misses 31331 # DTB write misses +system.cpu.dtb.read_accesses 244845406 # DTB read accesses +system.cpu.dtb.write_hits 135688740 # DTB write hits +system.cpu.dtb.write_misses 31438 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135724473 # DTB write accesses -system.cpu.dtb.data_hits 380239388 # DTB hits -system.cpu.dtb.data_misses 341094 # DTB misses +system.cpu.dtb.write_accesses 135720178 # DTB write accesses +system.cpu.dtb.data_hits 380224298 # DTB hits +system.cpu.dtb.data_misses 341286 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380580482 # DTB accesses -system.cpu.itb.fetch_hits 197059053 # ITB hits -system.cpu.itb.fetch_misses 278 # ITB misses +system.cpu.dtb.data_accesses 380565584 # DTB accesses +system.cpu.itb.fetch_hits 196974389 # ITB hits +system.cpu.itb.fetch_misses 282 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 197059331 # ITB accesses +system.cpu.itb.fetch_accesses 196974671 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -337,99 +318,99 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 556278850 # number of cpu cycles simulated +system.cpu.numCycles 556360470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202390061 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648021471 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192497192 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155912689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341534414 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24250324 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 202471372 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648161036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192516083 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155877930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341537101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24247434 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6722 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 6713 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 197059053 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6903560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 556056617 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 196974389 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6735628 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 556139161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176192 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236849124 42.59% 42.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30318987 5.45% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22124224 3.98% 52.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36449383 6.55% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67846603 12.20% 70.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21659642 3.90% 74.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19297725 3.47% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3452517 0.62% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118058412 21.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236974879 42.61% 42.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30241040 5.44% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22122460 3.98% 52.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36446378 6.55% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67887841 12.21% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21615986 3.89% 74.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19300231 3.47% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3499506 0.63% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118050840 21.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 556056617 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346044 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.962582 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168903349 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 88724490 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273566111 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12744273 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12118394 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15366279 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1583865955 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 556139161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346028 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.962398 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168673381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 88906441 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273702922 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12739464 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12116953 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15366288 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7026 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1584564231 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12118394 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176795678 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61743317 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13930 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278397423 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26987875 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1537838720 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7334 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2373790 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17873362 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6849052 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1027019192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1768562187 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1728780266 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39781920 # Number of floating rename lookups +system.cpu.rename.SquashCycles 12116953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176662049 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61884123 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13864 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278433046 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27029126 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538057639 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6904 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2373775 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17934465 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6832008 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1026949046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1768413823 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1728631636 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39782186 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 388052034 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1374 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9574141 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372265088 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175432833 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40642740 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11166161 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304456084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 387981888 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1375 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 99 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9559876 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372392006 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175420299 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40717360 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11158065 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304772774 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015678873 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8790246 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462050270 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427374200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1015651643 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8789932 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462366805 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427709940 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 556056617 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.826575 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.903970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 556139161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.826254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.901646 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197073815 35.44% 35.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93100278 16.74% 52.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91275539 16.41% 68.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59807751 10.76% 79.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56767795 10.21% 89.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29817356 5.36% 94.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17038926 3.06% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7188508 1.29% 99.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3986649 0.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 196811929 35.39% 35.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93156725 16.75% 52.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91633615 16.48% 68.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59891442 10.77% 79.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56837976 10.22% 89.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29662833 5.33% 94.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17038989 3.06% 98.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7191857 1.29% 99.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3913795 0.70% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 556056617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 556139161 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2463855 10.47% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2464081 10.47% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available @@ -458,118 +439,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15566694 66.15% 76.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5500530 23.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15568992 66.16% 76.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5500305 23.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579447507 57.05% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579437623 57.05% 57.05% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7930 0.00% 57.05% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13181923 1.30% 58.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13181925 1.30% 58.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276926005 27.27% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138947884 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276912765 27.26% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138943776 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015678873 # Type of FU issued -system.cpu.iq.rate 1.825845 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23531079 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2548927232 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1725239923 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 940039301 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70808456 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41311588 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34425282 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002846638 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36362038 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50462240 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015651643 # Type of FU issued +system.cpu.iq.rate 1.825528 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23533378 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023171 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2548957351 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1725871307 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 940019268 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70808406 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41313833 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34425264 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002821720 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36362025 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50456367 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 134754491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1146539 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45582 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77131633 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 134881409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1145791 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45978 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77119099 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2126 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4422 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2647 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4470 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12118394 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60795579 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 183960 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1478937167 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16099 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372265088 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175432833 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 12116953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60932529 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 189663 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479247252 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16168 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372392006 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175420299 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 26971 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 168750 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45582 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11885427 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16182 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11901609 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976191371 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244856188 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39487502 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 26629 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 174749 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45978 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11882583 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16645 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11899228 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976172370 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244845576 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39479273 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174481002 # number of nop insts executed -system.cpu.iew.exec_refs 380581036 # number of memory reference insts executed -system.cpu.iew.exec_branches 129104728 # Number of branches executed -system.cpu.iew.exec_stores 135724848 # Number of stores executed -system.cpu.iew.exec_rate 1.754860 # Inst execution rate -system.cpu.iew.wb_sent 974983742 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974464583 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556223277 # num instructions producing a value -system.cpu.iew.wb_consumers 832224680 # num instructions consuming a value +system.cpu.iew.exec_nop 174474397 # number of nop insts executed +system.cpu.iew.exec_refs 380566182 # number of memory reference insts executed +system.cpu.iew.exec_branches 129102826 # Number of branches executed +system.cpu.iew.exec_stores 135720606 # Number of stores executed +system.cpu.iew.exec_rate 1.754568 # Inst execution rate +system.cpu.iew.wb_sent 974964146 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974444532 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556292557 # num instructions producing a value +system.cpu.iew.wb_consumers 832443785 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.751756 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668357 # average fanout of values written-back +system.cpu.iew.wb_rate 1.751463 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668264 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543106202 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543416365 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11884314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 483349873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.921150 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.600543 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11882488 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 483294798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.921369 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.600805 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 205286712 42.47% 42.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102225167 21.15% 63.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51816081 10.72% 74.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25666887 5.31% 79.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21541208 4.46% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9141976 1.89% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10432211 2.16% 88.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6655388 1.38% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50584243 10.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 205311965 42.48% 42.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102147195 21.14% 63.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51748026 10.71% 74.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25735966 5.33% 79.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21537447 4.46% 84.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9139527 1.89% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10425967 2.16% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6656382 1.38% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50592323 10.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 483349873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 483294798 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -615,238 +596,330 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50584243 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 50592323 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1901838322 # The number of ROB reads -system.cpu.rob.rob_writes 3016095658 # The number of ROB writes -system.cpu.timesIdled 3295 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 222233 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1902085330 # The number of ROB reads +system.cpu.rob.rob_writes 3016853590 # The number of ROB writes +system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 221309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.660364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.660364 # CPI: Total CPI of All Threads -system.cpu.ipc 1.514316 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.514316 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237260763 # number of integer regfile reads -system.cpu.int_regfile_writes 705832198 # number of integer regfile writes -system.cpu.fp_regfile_reads 36691509 # number of floating regfile reads -system.cpu.fp_regfile_writes 24411335 # number of floating regfile writes +system.cpu.cpi 0.660461 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.660461 # CPI: Total CPI of All Threads +system.cpu.ipc 1.514094 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.514094 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237238749 # number of integer regfile reads +system.cpu.int_regfile_writes 705818584 # number of integer regfile writes +system.cpu.fp_regfile_reads 36691517 # number of floating regfile reads +system.cpu.fp_regfile_writes 24411333 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 718899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68835 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1666955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 408320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56270144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 879222 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 879222 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 879222 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 531099000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10065500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1207435500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4667 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.176031 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 197050731 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6380 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30885.694514 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 777239 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.040110 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289873961 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781335 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 370.998305 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354310000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.040110 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 585528663 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585528663 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192492893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192492893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97381046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97381046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289873939 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289873939 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289873939 # number of overall hits +system.cpu.dcache.overall_hits::total 289873939 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1579549 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1579549 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 920154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 920154 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2499703 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2499703 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2499703 # number of overall misses +system.cpu.dcache.overall_misses::total 2499703 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79817656500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79817656500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57409075211 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57409075211 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137226731711 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137226731711 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137226731711 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137226731711 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194072442 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194072442 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292373642 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292373642 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292373642 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292373642 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008139 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008139 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009361 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009361 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008550 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008550 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008550 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008550 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50531.928101 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50531.928101 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62390.725043 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62390.725043 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54897.214473 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54897.214473 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21908 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 55699 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 467 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.912206 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 107.943798 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks +system.cpu.dcache.writebacks::total 91488 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867045 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 867045 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851323 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 851323 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1718368 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1718368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1718368 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1718368 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712504 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712504 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68831 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68831 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781335 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781335 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781335 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781335 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21874292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21874292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5221022246 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5221022246 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27095314246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27095314246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27095314246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27095314246 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30700.588348 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30700.588348 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75852.773402 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75852.773402 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 4662 # number of replacements +system.cpu.icache.tags.tagsinuse 1655.102487 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 196966072 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6374 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30901.486037 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1655.176031 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.808191 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.808191 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1655.102487 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.808156 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.808156 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1712 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1559 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 394124484 # Number of tag accesses -system.cpu.icache.tags.data_accesses 394124484 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 197050731 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 197050731 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 197050731 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 197050731 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 197050731 # number of overall hits -system.cpu.icache.overall_hits::total 197050731 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8321 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8321 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8321 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8321 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8321 # number of overall misses -system.cpu.icache.overall_misses::total 8321 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333298749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333298749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333298749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333298749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 333298749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 333298749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 197059052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 197059052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 197059052 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 197059052 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 197059052 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 197059052 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.835938 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 393955150 # Number of tag accesses +system.cpu.icache.tags.data_accesses 393955150 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 196966072 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 196966072 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 196966072 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 196966072 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 196966072 # number of overall hits +system.cpu.icache.overall_hits::total 196966072 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8316 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8316 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8316 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8316 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8316 # number of overall misses +system.cpu.icache.overall_misses::total 8316 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 334444749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 334444749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 334444749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 334444749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 334444749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 334444749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 196974388 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 196974388 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 196974388 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 196974388 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 196974388 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 196974388 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40055.131475 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40055.131475 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40055.131475 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40055.131475 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40055.131475 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40055.131475 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 711 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40217.021284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40217.021284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40217.021284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40217.021284 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.636364 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 64.545455 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1940 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1940 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1940 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1940 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1940 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1940 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6381 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6381 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6381 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6381 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6381 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6381 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242585749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242585749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242585749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242585749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242585749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242585749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1941 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1941 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1941 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1941 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1941 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1941 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6375 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6375 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6375 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6375 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6375 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6375 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242697999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 242697999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242697999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242697999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242697999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242697999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38016.885911 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38016.885911 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38016.885911 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 38016.885911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38016.885911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38016.885911 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38070.274353 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38070.274353 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38070.274353 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38070.274353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38070.274353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38070.274353 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258677 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32635.114541 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 518852 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291414 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.780464 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258673 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32635.253710 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 518833 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291412 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.780411 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2797.134842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.663964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29769.315735 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.085362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002095 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.908487 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995945 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32737 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26521 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999054 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7394025 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7394025 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 490438 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26528 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999115 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7393827 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7393827 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 3629 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 490422 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 494051 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91488 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91488 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2209 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2209 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 492647 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 496278 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 492647 # number of overall hits -system.cpu.l2cache.overall_hits::total 496278 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2750 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 222080 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224830 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66626 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66626 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2750 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 2207 # 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miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72680.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73113.913905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73108.607615 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76941.539339 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76941.539339 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72680.090909 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73997.232479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73984.804739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72680.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73997.232479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73984.804739 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.967936 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.967936 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430745 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369503 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.369999 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430745 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369503 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.369999 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72836.671522 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73203.544186 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73199.063284 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76997.819855 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76997.819855 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72836.671522 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74079.140198 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74067.433917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72836.671522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74079.140198 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74067.433917 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17802574250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17967942250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312748 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.369999 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.369999 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60221.412964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60736.572527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60730.280481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64752.562890 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64752.562890 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60221.412964 # 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Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354263250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.039658 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2500 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 242 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585539447 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585539447 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192500682 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192500682 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97383359 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97383359 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 21 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 21 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289884041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289884041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289884041 # number of overall hits -system.cpu.dcache.overall_hits::total 289884041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1577144 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1577144 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 917841 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 917841 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2494985 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2494985 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2494985 # number of overall misses -system.cpu.dcache.overall_misses::total 2494985 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79985151750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79985151750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57294656713 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57294656713 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137279808463 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137279808463 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137279808463 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137279808463 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194077826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194077826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292379026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292379026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292379026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292379026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008126 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008126 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009337 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009337 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008533 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008533 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008533 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008533 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50715.186280 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50715.186280 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62423.291957 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62423.291957 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55022.298115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55022.298115 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21941 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 56666 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 465 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.184946 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 109.605416 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks -system.cpu.dcache.writebacks::total 91488 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 864626 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 849006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 849006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1713632 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1713632 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1713632 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1713632 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712518 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712518 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68835 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68835 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781353 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781353 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781353 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781353 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21854414000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21854414000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5217448748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5217448748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27071862748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27071862748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27071862748 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27071862748 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30672.086881 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30672.086881 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75796.451631 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75796.451631 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 718879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68831 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1666907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 407936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55860672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56268608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 879198 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 879198 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 879198 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 531087000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 10054750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1207495250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224827 # Transaction distribution +system.membus.trans_dist::ReadResp 224827 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66624 # Transaction distribution +system.membus.trans_dist::ReadExResp 66624 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649585 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649585 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358134 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358134 # Request fanout histogram +system.membus.reqLayer0.occupancy 959207000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2708819750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 531c5ebad..11060cf95 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541781 # Number of seconds simulated -sim_ticks 541781076000 # Number of ticks simulated -final_tick 541781076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541786 # Number of seconds simulated +sim_ticks 541786101000 # Number of ticks simulated +final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140173 # Simulator instruction rate (inst/s) -host_op_rate 172571 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118539448 # Simulator tick rate (ticks/s) -host_mem_usage 261676 # Number of bytes of host memory used -host_seconds 4570.47 # Real time elapsed on the host +host_inst_rate 183531 # Simulator instruction rate (inst/s) +host_op_rate 225950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155207340 # Simulator tick rate (ticks/s) +host_mem_usage 320704 # Number of bytes of host memory used +host_seconds 3490.72 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,43 +23,43 @@ system.physmem.num_reads::cpu.inst 290529 # Nu system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34319870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34319870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7808084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7808084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7808084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34319870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42127954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34319552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18573248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18288 # Per bank write bursts -system.physmem.perBankRdBursts::1 18139 # Per bank write bursts -system.physmem.perBankRdBursts::2 18224 # Per bank write bursts -system.physmem.perBankRdBursts::3 18182 # Per bank write bursts -system.physmem.perBankRdBursts::4 18264 # Per bank write bursts -system.physmem.perBankRdBursts::5 18315 # Per bank write bursts -system.physmem.perBankRdBursts::6 18098 # Per bank write bursts +system.physmem.perBankRdBursts::0 18289 # Per bank write bursts +system.physmem.perBankRdBursts::1 18137 # Per bank write bursts +system.physmem.perBankRdBursts::2 18222 # Per bank write bursts +system.physmem.perBankRdBursts::3 18184 # Per bank write bursts +system.physmem.perBankRdBursts::4 18266 # Per bank write bursts +system.physmem.perBankRdBursts::5 18308 # Per bank write bursts +system.physmem.perBankRdBursts::6 18094 # Per bank write bursts system.physmem.perBankRdBursts::7 17914 # Per bank write bursts -system.physmem.perBankRdBursts::8 17936 # Per bank write bursts -system.physmem.perBankRdBursts::9 17963 # Per bank write bursts -system.physmem.perBankRdBursts::10 18015 # Per bank write bursts +system.physmem.perBankRdBursts::8 17939 # Per bank write bursts +system.physmem.perBankRdBursts::9 17962 # Per bank write bursts +system.physmem.perBankRdBursts::10 18018 # Per bank write bursts system.physmem.perBankRdBursts::11 18110 # Per bank write bursts -system.physmem.perBankRdBursts::12 18146 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts -system.physmem.perBankRdBursts::14 18075 # Per bank write bursts -system.physmem.perBankRdBursts::15 18267 # Per bank write bursts +system.physmem.perBankRdBursts::12 18143 # Per bank write bursts +system.physmem.perBankRdBursts::13 18270 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18266 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4101 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541780987500 # Total gap between requests +system.physmem.totGap 541786012500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,9 +93,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,42 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.445337 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.546078 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.289579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46919 42.07% 42.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43694 39.18% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8696 7.80% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 722 0.65% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1258 1.13% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1255 1.13% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 576 0.52% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 502 0.45% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7898 7.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111520 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.543798 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.072613 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.664819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.488645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.467122 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3028 75.57% 75.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 2702187250 # Total ticks spent queuing -system.physmem.totMemAccLat 8143568500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9311.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads +system.physmem.totQLat 2707676000 # Total ticks spent queuing +system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28061.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s @@ -235,35 +237,40 @@ system.physmem.busUtilRead 0.27 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing -system.physmem.readRowHits 194639 # Number of row buffer hits during reads -system.physmem.writeRowHits 50105 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.80 # Row buffer hit rate for writes -system.physmem.avgGap 1519181.07 # Average gap between requests -system.physmem.pageHitRate 68.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 263887343000 # Time in different power states -system.physmem.memoryStateTime::REF 18091060000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 259796939500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 421530480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 421462440 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 230001750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 229964625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1134174600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1128987600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 215628480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 212505120 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 35386113360 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 35386113360 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 105979651695 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 105556941405 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 232100586000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 232471384500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 375467686365 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 375407359050 # Total energy per rank (pJ) -system.physmem.averagePower::0 693.032096 # Core power per rank (mW) -system.physmem.averagePower::1 692.920745 # Core power per rank (mW) +system.physmem.readRowHits 194608 # Number of row buffer hits during reads +system.physmem.writeRowHits 50098 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes +system.physmem.avgGap 1519195.16 # Average gap between requests +system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.117148 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.890615 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 156937341 # Number of BP lookups system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect @@ -274,6 +281,14 @@ system.cpu.branchPred.BTBHitPct 83.942615 # BT system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -295,6 +310,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -316,6 +339,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +368,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -359,24 +398,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1083562152 # number of cpu cycles simulated +system.cpu.numCycles 1083572202 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655084 # Number of instructions committed system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.691335 # CPI: cycles per instruction -system.cpu.ipc 0.591249 # IPC: instructions per cycle -system.cpu.tickCycles 1029140125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54422027 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.691350 # CPI: cycles per instruction +system.cpu.ipc 0.591244 # IPC: instructions per cycle +system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778221 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.644165 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 752182250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.644165 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.645412 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -408,14 +447,14 @@ system.cpu.dcache.demand_misses::cpu.inst 851460 # n system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23050728217 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23050728217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9196889000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9196889000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32247617217 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32247617217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32247617217 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32247617217 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32255064217 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) @@ -436,14 +475,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32295.376677 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32295.376677 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66783.012497 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66783.012497 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37873.320199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37873.320199 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32302.557092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66799.873650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,14 +509,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21540338778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21540338778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529678750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529678750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26070017528 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26070017528 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26070017528 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26070017528 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21545578028 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses @@ -486,22 +525,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30211.065685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30211.065685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65342.586048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65342.586048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23590 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.180354 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289921724 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11440.816227 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180354 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -509,44 +548,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 57 system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579919473 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579919473 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289921724 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289921724 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289921724 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289921724 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289921724 # number of overall hits -system.cpu.icache.overall_hits::total 289921724 # number of overall hits +system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits +system.cpu.icache.overall_hits::total 289921723 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses system.cpu.icache.overall_misses::total 25342 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 481750746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 481750746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 481750746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 481750746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 481750746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 481750746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289947066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289947066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289947066 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289947066 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289947066 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289947066 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 480693746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 480693746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 480693746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 480693746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 480693746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 480693746 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289947065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289947065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289947065 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289947065 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289947065 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19009.973404 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19009.973404 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19009.973404 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19009.973404 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,36 +600,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25342 system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429966254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 429966254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429966254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 429966254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429966254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 429966254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16966.547786 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16966.547786 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32583.074549 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2860.585859 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.488690 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087298 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907058 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994357 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.446536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907057 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id @@ -618,14 +657,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 290562 # system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses system.cpu.l2cache.overall_misses::total 290562 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16093224000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16093224000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4428044750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4428044750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20521268750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20521268750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20521268750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20521268750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16097406250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4429448000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20526854250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20526854250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) @@ -644,14 +683,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71694.000561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71694.000561 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66999.209423 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66999.209423 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70626.127126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70626.127126 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71712.632144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67020.441512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,14 +715,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 290530 system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 290530 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13281416250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13281416250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3575940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3575940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16857356500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16857356500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16857356500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16857356500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13285316750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3577310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16862626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16862626750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses @@ -692,14 +731,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59176.062315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59176.062315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54106.311752 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54106.311752 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59193.441202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54127.036964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution @@ -732,7 +771,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # La system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224341972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224438 # Transaction distribution system.membus.trans_dist::ReadResp 224438 # Transaction distribution @@ -754,9 +793,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 356627 # Request fanout histogram -system.membus.reqLayer0.occupancy 983533000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2738969000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 57de3b3e6..5cb40d175 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.407884 # Number of seconds simulated -sim_ticks 407883784500 # Number of ticks simulated -final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.408037 # Number of seconds simulated +sim_ticks 408037199500 # Number of ticks simulated +final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91246 # Simulator instruction rate (inst/s) -host_op_rate 112336 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58093586 # Simulator tick rate (ticks/s) -host_mem_usage 2566152 # Number of bytes of host memory used -host_seconds 7021.15 # Real time elapsed on the host +host_inst_rate 90640 # Simulator instruction rate (inst/s) +host_op_rate 111590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57729920 # Simulator tick rate (ticks/s) +host_mem_usage 318440 # Number of bytes of host memory used +host_seconds 7068.04 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 63360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6867584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 13490752 # Number of bytes read from this memory -system.physmem.bytes_read::total 20421696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4243968 # Number of bytes written to this memory -system.physmem.bytes_written::total 4243968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 107306 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 210793 # Number of read requests responded to by this memory -system.physmem.num_reads::total 319089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66312 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66312 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 155338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16837110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 33074990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50067438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10404846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10404846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10404846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16837110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 33074990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60472284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 319089 # Number of read requests accepted -system.physmem.writeReqs 66312 # Number of write requests accepted -system.physmem.readBursts 319089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66312 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20403200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20421696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4243968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 20089 # Per bank write bursts -system.physmem.perBankRdBursts::1 19545 # Per bank write bursts -system.physmem.perBankRdBursts::2 20086 # Per bank write bursts -system.physmem.perBankRdBursts::3 20646 # Per bank write bursts -system.physmem.perBankRdBursts::4 19933 # Per bank write bursts -system.physmem.perBankRdBursts::5 20704 # Per bank write bursts -system.physmem.perBankRdBursts::6 19571 # Per bank write bursts -system.physmem.perBankRdBursts::7 19471 # Per bank write bursts -system.physmem.perBankRdBursts::8 19556 # Per bank write bursts -system.physmem.perBankRdBursts::9 19505 # Per bank write bursts -system.physmem.perBankRdBursts::10 19502 # Per bank write bursts -system.physmem.perBankRdBursts::11 20173 # Per bank write bursts -system.physmem.perBankRdBursts::12 19634 # Per bank write bursts -system.physmem.perBankRdBursts::13 20280 # Per bank write bursts -system.physmem.perBankRdBursts::14 19577 # Per bank write bursts -system.physmem.perBankRdBursts::15 20528 # Per bank write bursts -system.physmem.perBankWrBursts::0 4247 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory +system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315254 # Number of read requests accepted +system.physmem.writeReqs 66324 # Number of write requests accepted +system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19893 # Per bank write bursts +system.physmem.perBankRdBursts::1 19507 # Per bank write bursts +system.physmem.perBankRdBursts::2 19696 # Per bank write bursts +system.physmem.perBankRdBursts::3 19811 # Per bank write bursts +system.physmem.perBankRdBursts::4 19755 # Per bank write bursts +system.physmem.perBankRdBursts::5 20266 # Per bank write bursts +system.physmem.perBankRdBursts::6 19606 # Per bank write bursts +system.physmem.perBankRdBursts::7 19431 # Per bank write bursts +system.physmem.perBankRdBursts::8 19468 # Per bank write bursts +system.physmem.perBankRdBursts::9 19384 # Per bank write bursts +system.physmem.perBankRdBursts::10 19414 # Per bank write bursts +system.physmem.perBankRdBursts::11 19672 # Per bank write bursts +system.physmem.perBankRdBursts::12 19624 # Per bank write bursts +system.physmem.perBankRdBursts::13 19992 # Per bank write bursts +system.physmem.perBankRdBursts::14 19481 # Per bank write bursts +system.physmem.perBankRdBursts::15 19957 # Per bank write bursts +system.physmem.perBankWrBursts::0 4278 # Per bank write bursts system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4151 # Per bank write bursts -system.physmem.perBankWrBursts::4 4245 # Per bank write bursts +system.physmem.perBankWrBursts::2 4141 # Per bank write bursts +system.physmem.perBankWrBursts::3 4152 # Per bank write bursts +system.physmem.perBankWrBursts::4 4250 # Per bank write bursts system.physmem.perBankWrBursts::5 4232 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4153 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 407883730500 # Total gap between requests +system.physmem.totGap 408037145000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 319089 # Read request sizes (log2) +system.physmem.readPktSize::6 315254 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66312 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 124916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 644 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66324 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,189 +148,171 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 595 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 138324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.138053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.082938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 199.804046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 55124 39.85% 39.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 58239 42.10% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14671 10.61% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 966 0.70% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1420 1.03% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1368 0.99% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1462 1.06% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1224 0.88% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3850 2.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 138324 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 67.829475 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.454654 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 482.917109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3981 99.10% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 5 0.12% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 3 0.07% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 2 0.05% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 2 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.484690 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.435555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.421529 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3367 83.82% 83.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.22% 84.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 437 10.88% 94.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 79 1.97% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 37 0.92% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.45% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.37% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.55% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.32% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.07% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.15% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.07% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 9958454882 # Total ticks spent queuing -system.physmem.totMemAccLat 15935954882 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1594000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31237.31 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads +system.physmem.totQLat 9384520258 # Total ticks spent queuing +system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49987.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 50.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.07 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.47 # Data bus utilization in percentage system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing -system.physmem.readRowHits 219908 # Number of row buffer hits during reads -system.physmem.writeRowHits 26785 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.43 # Row buffer hit rate for writes -system.physmem.avgGap 1058335.94 # Average gap between requests -system.physmem.pageHitRate 64.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 155274651966 # Time in different power states -system.physmem.memoryStateTime::REF 13620100000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 238988228034 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 524928600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 520778160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 286419375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 284154750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1248351000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1238000400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216380160 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 212718960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 26640915600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 26640915600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 97043660235 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 97028348895 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 159603762000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 159617193000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 285564416970 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 285542109765 # Total energy per rank (pJ) -system.physmem.averagePower::0 700.113612 # Core power per rank (mW) -system.physmem.averagePower::1 700.058922 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 317731 # Transaction distribution -system.membus.trans_dist::ReadResp 317731 # Transaction distribution -system.membus.trans_dist::Writeback 66312 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19 # Transaction distribution -system.membus.trans_dist::UpgradeResp 19 # Transaction distribution -system.membus.trans_dist::ReadExReq 1358 # Transaction distribution -system.membus.trans_dist::ReadExResp 1358 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 704528 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 704528 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24665664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24665664 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 385420 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 385420 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 385420 # Request fanout histogram -system.membus.reqLayer0.occupancy 968060850 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2930140600 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 233961455 # Number of BP lookups -system.cpu.branchPred.condPredicted 161822903 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15515021 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121571694 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108258179 # Number of BTB hits +system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 218395 # Number of row buffer hits during reads +system.physmem.writeRowHits 26455 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes +system.physmem.avgGap 1069341.38 # Average gap between requests +system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.765171 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states +system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.696391 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states +system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 233958621 # Number of BP lookups +system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.048836 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25034450 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300530 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -352,6 +334,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -373,6 +363,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,6 +392,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -416,95 +422,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 815767570 # number of cpu cycles simulated +system.cpu.numCycles 816074400 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064711 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370072724 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652087 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 815611997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.839157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134572174 16.50% 16.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 222502254 27.28% 43.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98076609 12.02% 55.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360460960 44.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 815611997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286799 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.471100 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119967047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 156830594 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662032 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38633655 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518669 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25180757 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13832 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248142745 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39968083 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518669 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176978211 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77349013 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 209115 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464956606 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80600383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190653187 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25546667 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24946830 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267986 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40254462 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1692453 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225396135 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812466885 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358185264 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876472 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350617905 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7272 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 7264 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108149104 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366119032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236098756 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1753479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5371728 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168565166 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017100859 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18396242 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379746204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032205063 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 815611997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.247040 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 257903097 31.62% 31.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 228438073 28.01% 59.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 215325690 26.40% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97769150 11.99% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16175979 1.98% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 815611997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64512923 19.13% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18147 0.01% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available @@ -532,13 +538,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155504488 46.10% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116641749 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456383765 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195693 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -560,90 +566,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550151 0.25% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478998 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322094029 31.67% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215573019 21.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017100859 # Type of FU issued -system.cpu.iq.rate 1.246802 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337314196 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331643 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3143647062 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504776491 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934274751 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877091 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565761 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152451 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320604680 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810375 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960281 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued +system.cpu.iq.rate 1.246337 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113878094 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1252 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107118260 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23979 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518669 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35328826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 675397 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168583078 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366119032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236098756 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 121 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 678981 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437712 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784771 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19222483 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974757504 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303300667 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42343355 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5552 # number of nop insts executed -system.cpu.iew.exec_refs 497757295 # number of memory reference insts executed -system.cpu.iew.exec_branches 150614518 # Number of branches executed -system.cpu.iew.exec_stores 194456628 # Number of stores executed -system.cpu.iew.exec_rate 1.194896 # Inst execution rate -system.cpu.iew.wb_sent 963726633 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960427202 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536683301 # num instructions producing a value -system.cpu.iew.wb_consumers 893293358 # num instructions consuming a value +system.cpu.iew.exec_nop 5556 # number of nop insts executed +system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed +system.cpu.iew.exec_branches 150614661 # Number of branches executed +system.cpu.iew.exec_stores 194464042 # Number of stores executed +system.cpu.iew.exec_rate 1.194456 # Inst execution rate +system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536684839 # num instructions producing a value +system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.177329 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600792 # average fanout of values written-back +system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357423726 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15501335 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 764789514 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.031303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.790973 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 428726988 56.06% 56.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 171833427 22.47% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566428 9.62% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31619643 4.13% 92.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 7902471 1.03% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14889027 1.95% 95.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7271717 0.95% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6618968 0.87% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360845 2.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 764789514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654410 # Number of instructions committed system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -689,507 +695,529 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1888573713 # The number of ROB reads -system.cpu.rob.rob_writes 2343133826 # The number of ROB writes -system.cpu.timesIdled 646395 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1888745890 # The number of ROB reads +system.cpu.rob.rob_writes 2343137518 # The number of ROB writes +system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649298 # Number of Instructions Simulated system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.273345 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.273345 # CPI: Total CPI of All Threads -system.cpu.ipc 0.785333 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.785333 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995802642 # number of integer regfile reads -system.cpu.int_regfile_writes 567917186 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889847 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959506 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794452598 # number of cc regfile reads -system.cpu.cc_regfile_writes 384905504 # number of cc regfile writes -system.cpu.misc_regfile_reads 715806131 # number of misc regfile reads +system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads +system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995816176 # number of integer regfile reads +system.cpu.int_regfile_writes 567918829 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads +system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes +system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 7205652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7205652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 9840757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339627 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248397 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16588024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330867456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223467584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554335040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 9840776 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18503299 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.531838 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.498985 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 8662542 46.82% 46.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 9840757 53.18% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18503299 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5066671498 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7754858551 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4142472532 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 5169293 # number of replacements -system.cpu.icache.tags.tagsinuse 510.870067 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 364901080 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.583169 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 199337500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.870067 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 325 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745315243 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745315243 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364901109 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364901109 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364901109 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364901109 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364901109 # number of overall hits -system.cpu.icache.overall_hits::total 364901109 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5171601 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5171601 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5171601 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5171601 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5171601 # number of overall misses -system.cpu.icache.overall_misses::total 5171601 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41478755019 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41478755019 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41478755019 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41478755019 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41478755019 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41478755019 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370072710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370072710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370072710 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370072710 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370072710 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370072710 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8020.486310 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8020.486310 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8020.486310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8020.486310 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17792 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1782 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9.984287 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1778 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1778 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1778 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1778 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1778 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1778 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169823 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5169823 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5169823 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5169823 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5169823 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5169823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33703861415 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33703861415 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33703861415 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33703861415 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33703861415 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33703861415 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6519.345327 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6519.345327 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6519.345327 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6519.345327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6519.345327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6519.345327 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 42714534 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 332916 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 32636070 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 18709 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3827 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 9723012 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4810754 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 302773 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16364.911497 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7827990 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 319143 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.528158 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 12938833000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 727.090986 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.045333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8487.644412 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 7101.130766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.044378 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.518045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.433419 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998835 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 7180 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9190 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1499 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 5110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2000 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6801 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.438232 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.560913 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 139624071 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 139624071 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5168280 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1928699 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7096979 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 735005 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 735005 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718110 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718110 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5168280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2646809 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7815089 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5168280 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2646809 # number of overall hits -system.cpu.l2cache.overall_hits::total 7815089 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 107130 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 108654 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2737 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2737 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 109867 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 111391 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1524 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 109867 # number of overall misses -system.cpu.l2cache.overall_misses::total 111391 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107432161 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7354763933 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 7462196094 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 174400348 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 174400348 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107432161 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7529164281 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7636596442 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107432161 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7529164281 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7636596442 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169804 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 2035829 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7205633 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 735005 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 735005 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5169804 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756676 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7926480 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5169804 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756676 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7926480 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.052622 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015079 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.950000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.950000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003797 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003797 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000295 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.039855 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014053 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000295 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.039855 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014053 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70493.543963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68652.701699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68678.521674 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63719.527950 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63719.527950 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70493.543963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68529.806775 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68556.673717 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70493.543963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68529.806775 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68556.673717 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 126545 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2364 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53.530034 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66312 # number of writebacks -system.cpu.l2cache.writebacks::total 66312 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 534 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1182 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1716 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1379 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1379 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 534 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2561 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3095 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 534 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2561 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3095 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 990 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 105948 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 106938 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 9723012 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 9723012 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1358 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1358 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 107306 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 108296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 107306 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 9723012 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 9831308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71873499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6404181248 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6476054747 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19431970184 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 143518 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 143518 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92793756 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92793756 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71873499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6496975004 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6568848503 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71873499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6496975004 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26000818687 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.052042 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.014841 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.950000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.950000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.013663 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.240312 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72599.493939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60446.457205 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60558.966382 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 1998.554582 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 7553.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 7553.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68331.189985 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68331.189985 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.427781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 2644.695771 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2756164 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.948880 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414248795 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756676 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.271122 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 207459500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.948880 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999900 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999900 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756166 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347154 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347154 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286297439 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286297439 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127936631 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127936631 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414234070 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414234070 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414237227 # number of overall hits -system.cpu.dcache.overall_hits::total 414237227 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031039 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031039 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1014846 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1014846 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 648 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 648 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits +system.cpu.dcache.overall_hits::total 414238542 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4045885 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4045885 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4046533 # number of overall misses -system.cpu.dcache.overall_misses::total 4046533 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33719933619 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33719933619 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9704111685 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9704111685 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 169500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 169500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43424045304 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43424045304 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43424045304 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43424045304 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses +system.cpu.dcache.overall_misses::total 4045534 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3805 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3805 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279955 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279955 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283760 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283760 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010476 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007870 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.007870 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170302 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.170302 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009673 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009673 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009674 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009674 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11124.876196 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11124.876196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9562.151977 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9562.151977 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10732.891643 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10732.891643 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10731.172909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10731.172909 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 339239 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5513 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.534373 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735005 # number of writebacks -system.cpu.dcache.writebacks::total 735005 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995853 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 995853 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293979 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 293979 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks +system.cpu.dcache.writebacks::total 735128 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1289832 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1289832 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1289832 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1289832 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720867 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720867 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 643 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 643 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756053 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756053 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756696 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756696 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2092 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7253 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.398804 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.599976 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139620886 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139620886 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5166160 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1926359 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7092519 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68338.017414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68338.017414 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks +system.cpu.l2cache.writebacks::total 66324 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1474 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2816 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2816 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2827 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3550 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108130 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 111680 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202272 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202272 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1377 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3550 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109507 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113057 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3550 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 109507 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202272 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 315329 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205967021 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6469574626 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6675541647 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18462254833 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 84014 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 84014 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126131000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126131000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205967021 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6595705626 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6801672647 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205967021 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6595705626 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25263927480 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053113 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015499 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823529 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823529 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91274.397015 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91598.402324 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91598.402324 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60161.446412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 317003 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 313877 # Transaction distribution +system.membus.trans_dist::ReadResp 313877 # Transaction distribution +system.membus.trans_dist::Writeback 66324 # Transaction distribution +system.membus.trans_dist::UpgradeReq 14 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 381592 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 381592 # Request fanout histogram +system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index b5ba9b69f..4817ec8a9 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778000 # Number of ticks simulated final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1695212 # Simulator instruction rate (inst/s) -host_op_rate 2087030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1047118075 # Simulator tick rate (ticks/s) -host_mem_usage 304696 # Number of bytes of host memory used -host_seconds 377.92 # Real time elapsed on the host +host_inst_rate 1395078 # Simulator instruction rate (inst/s) +host_op_rate 1717525 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 861727739 # Simulator tick rate (ticks/s) +host_mem_usage 309420 # Number of bytes of host memory used +host_seconds 459.22 # Real time elapsed on the host sim_insts 640654410 # Number of instructions simulated sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1322421029 # Wr system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 893703777 # Transaction distribution -system.membus.trans_dist::ReadResp 893709516 # Transaction distribution -system.membus.trans_dist::WriteReq 128951477 # Transaction distribution -system.membus.trans_dist::WriteResp 128951477 # Transaction distribution -system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution -system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram -system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 1022670352 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction +system.membus.trans_dist::ReadReq 893703777 # Transaction distribution +system.membus.trans_dist::ReadResp 893709516 # Transaction distribution +system.membus.trans_dist::WriteReq 128951477 # Transaction distribution +system.membus.trans_dist::WriteResp 128951477 # Transaction distribution +system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution +system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram +system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 1022670352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index b1098c721..c5e3a18fc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.043695 # Nu sim_ticks 1043695084000 # Number of ticks simulated final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 974812 # Simulator instruction rate (inst/s) -host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1591272225 # Simulator tick rate (ticks/s) -host_mem_usage 314196 # Number of bytes of host memory used -host_seconds 655.89 # Real time elapsed on the host +host_inst_rate 894518 # Simulator instruction rate (inst/s) +host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1460200235 # Simulator tick rate (ticks/s) +host_mem_usage 317628 # Number of bytes of host memory used +host_seconds 714.76 # Real time elapsed on the host sim_insts 639366786 # Number of instructions simulated sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 4053168 # To system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 223619 # Transaction distribution -system.membus.trans_dist::ReadResp 223619 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::ReadExReq 66093 # Transaction distribution -system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 355811 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 355811 # Request fanout histogram -system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,145 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction +system.cpu.dcache.tags.replacements 778046 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits +system.cpu.dcache.overall_hits::total 378498833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses +system.cpu.dcache.overall_misses::total 782143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks +system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. @@ -438,145 +585,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits -system.cpu.dcache.overall_hits::total 378498833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses -system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks -system.cpu.dcache.writebacks::total 91561 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution @@ -610,5 +618,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 15312000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::ReadExReq 66093 # Transaction distribution +system.membus.trans_dist::ReadExResp 66093 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 355811 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 355811 # Request fanout histogram +system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index a69375a69..1993a40dc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058648 # Number of seconds simulated -sim_ticks 58648243500 # Number of ticks simulated -final_tick 58648243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058585 # Number of seconds simulated +sim_ticks 58584661500 # Number of ticks simulated +final_tick 58584661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 296946 # Simulator instruction rate (inst/s) -host_op_rate 296946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 196921777 # Simulator tick rate (ticks/s) -host_mem_usage 246040 # Number of bytes of host memory used -host_seconds 297.83 # Real time elapsed on the host +host_inst_rate 346754 # Simulator instruction rate (inst/s) +host_op_rate 346754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 229702503 # Simulator tick rate (ticks/s) +host_mem_usage 303900 # Number of bytes of host memory used +host_seconds 255.05 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 10664704 # Number of bytes read from this memory -system.physmem.bytes_read::total 10664704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 516672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 516672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 166636 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114049 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114049 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 181841831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 181841831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8809676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8809676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 124456174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 124456174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 124456174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 181841831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 306298005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166636 # Number of read requests accepted -system.physmem.writeReqs 114049 # Number of write requests accepted -system.physmem.readBursts 166636 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114049 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10664320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10664704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 10664384 # Number of bytes read from this memory +system.physmem.bytes_read::total 10664384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 516608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 516608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 166631 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166631 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 182033722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 182033722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8818144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8818144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 124590154 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 124590154 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 124590154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 182033722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 306623876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166631 # Number of read requests accepted +system.physmem.writeReqs 114048 # Number of write requests accepted +system.physmem.readBursts 166631 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10663872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10664384 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10467 # Per bank write bursts -system.physmem.perBankRdBursts::1 10513 # Per bank write bursts +system.physmem.perBankRdBursts::0 10466 # Per bank write bursts +system.physmem.perBankRdBursts::1 10512 # Per bank write bursts system.physmem.perBankRdBursts::2 10315 # Per bank write bursts -system.physmem.perBankRdBursts::3 10094 # Per bank write bursts +system.physmem.perBankRdBursts::3 10093 # Per bank write bursts system.physmem.perBankRdBursts::4 10429 # Per bank write bursts system.physmem.perBankRdBursts::5 10431 # Per bank write bursts system.physmem.perBankRdBursts::6 9849 # Per bank write bursts -system.physmem.perBankRdBursts::7 10303 # Per bank write bursts +system.physmem.perBankRdBursts::7 10302 # Per bank write bursts system.physmem.perBankRdBursts::8 10595 # Per bank write bursts system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10600 # Per bank write bursts +system.physmem.perBankRdBursts::10 10598 # Per bank write bursts system.physmem.perBankRdBursts::11 10258 # Per bank write bursts system.physmem.perBankRdBursts::12 10302 # Per bank write bursts system.physmem.perBankRdBursts::13 10653 # Per bank write bursts -system.physmem.perBankRdBursts::14 10529 # Per bank write bursts +system.physmem.perBankRdBursts::14 10528 # Per bank write bursts system.physmem.perBankRdBursts::15 10648 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6999 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::5 7176 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7094 # Per bank write bursts -system.physmem.perBankWrBursts::8 7220 # Per bank write bursts +system.physmem.perBankWrBursts::7 7084 # Per bank write bursts +system.physmem.perBankWrBursts::8 7223 # Per bank write bursts system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7094 # Per bank write bursts +system.physmem.perBankWrBursts::10 7096 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6965 # Per bank write bursts +system.physmem.perBankWrBursts::12 6966 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts -system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58648216500 # Total gap between requests +system.physmem.totGap 58584634500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166636 # Read request sizes (log2) +system.physmem.readPktSize::6 166631 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114049 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1583 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114048 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165000 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1595 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7043 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -189,115 +189,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.476881 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.680943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.305827 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19373 35.65% 35.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11674 21.48% 57.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5602 10.31% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3597 6.62% 74.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2712 4.99% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2058 3.79% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1657 3.05% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1528 2.81% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6148 11.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 54549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.259345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.795576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.998077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19535 35.81% 35.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11763 21.56% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5616 10.30% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3566 6.54% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2684 4.92% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2055 3.77% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1672 3.07% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1540 2.82% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6118 11.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54549 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 7016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.748575 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.190330 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7015 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.746152 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.264922 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7014 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 7016 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 7016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.251995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.236052 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.756108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6236 88.88% 88.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.21% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 602 8.58% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 126 1.80% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 27 0.38% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.250998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.234711 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.764594 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6252 89.11% 89.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 8 0.11% 89.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 591 8.42% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 125 1.78% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 23 0.33% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8 0.11% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 5 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 7016 # Writes before turning the bus around for reads -system.physmem.totQLat 2009240500 # Total ticks spent queuing -system.physmem.totMemAccLat 5133553000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12058.10 # Average queueing delay per DRAM burst +system.physmem.totQLat 1948128750 # Total ticks spent queuing +system.physmem.totMemAccLat 5072310000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11691.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30808.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 181.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 124.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 181.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 124.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30441.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 182.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 124.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 182.03 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 124.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.39 # Data bus utilization in percentage +system.physmem.busUtil 2.40 # Data bus utilization in percentage system.physmem.busUtilRead 1.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.97 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing -system.physmem.readRowHits 144828 # Number of row buffer hits during reads -system.physmem.writeRowHits 81470 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.92 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.43 # Row buffer hit rate for writes -system.physmem.avgGap 208946.74 # Average gap between requests -system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 32158270750 # Time in different power states -system.physmem.memoryStateTime::REF 1958320000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24529718750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 198298800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 212481360 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 108198750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 115937250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 642673200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 656838000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 367811280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 370960560 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3830473920 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3830473920 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 12291718545 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 12736700730 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 24405568500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 24015233250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41844742995 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41938625070 # Total energy per rank (pJ) -system.physmem.averagePower::0 713.510412 # Core power per rank (mW) -system.physmem.averagePower::1 715.111230 # Core power per rank (mW) -system.cpu.branchPred.lookups 14678284 # Number of BP lookups -system.cpu.branchPred.condPredicted 9497966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 389718 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9980180 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6390464 # Number of BTB hits +system.physmem.avgWrQLen 24.07 # Average write queue length when enqueuing +system.physmem.readRowHits 144841 # Number of row buffer hits during reads +system.physmem.writeRowHits 81248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.24 # Row buffer hit rate for writes +system.physmem.avgGap 208724.68 # Average gap between requests +system.physmem.pageHitRate 80.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199077480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108623625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 642681000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367791840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12184332255 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24462392250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41791303890 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.356895 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40549753500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16078529000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 213282720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116374500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 656908200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371038320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12703202685 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24007242750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41894454615 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.117627 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 39789307500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16838471250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 14678313 # Number of BP lookups +system.cpu.branchPred.condPredicted 9498021 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 389703 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9975544 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6390264 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.031551 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1709614 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85893 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.059303 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1709596 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85905 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20567325 # DTB read hits -system.cpu.dtb.read_misses 96876 # DTB read misses +system.cpu.dtb.read_hits 20567455 # DTB read hits +system.cpu.dtb.read_misses 96888 # DTB read misses system.cpu.dtb.read_acv 11 # DTB read access violations -system.cpu.dtb.read_accesses 20664201 # DTB read accesses -system.cpu.dtb.write_hits 14665780 # DTB write hits -system.cpu.dtb.write_misses 9406 # DTB write misses +system.cpu.dtb.read_accesses 20664343 # DTB read accesses +system.cpu.dtb.write_hits 14665775 # DTB write hits +system.cpu.dtb.write_misses 9411 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 14675186 # DTB write accesses -system.cpu.dtb.data_hits 35233105 # DTB hits -system.cpu.dtb.data_misses 106282 # DTB misses +system.cpu.dtb.data_hits 35233230 # DTB hits +system.cpu.dtb.data_misses 106299 # DTB misses system.cpu.dtb.data_acv 11 # DTB access violations -system.cpu.dtb.data_accesses 35339387 # DTB accesses -system.cpu.itb.fetch_hits 25627874 # ITB hits -system.cpu.itb.fetch_misses 5262 # ITB misses +system.cpu.dtb.data_accesses 35339529 # DTB accesses +system.cpu.itb.fetch_hits 25627333 # ITB hits +system.cpu.itb.fetch_misses 5261 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25633136 # ITB accesses +system.cpu.itb.fetch_accesses 25632594 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,81 +318,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 117296487 # number of cpu cycles simulated +system.cpu.numCycles 117169323 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1098513 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1098705 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.326312 # CPI: cycles per instruction -system.cpu.ipc 0.753970 # IPC: instructions per cycle -system.cpu.tickCycles 91572461 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25724026 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200783 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.549742 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616444 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204879 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.960430 # Average number of references to valid blocks. +system.cpu.cpi 1.324874 # CPI: cycles per instruction +system.cpu.ipc 0.754789 # IPC: instructions per cycle +system.cpu.tickCycles 91571156 # Number of cycles that the object actually ticked +system.cpu.idleCycles 25598167 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200776 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.523211 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616515 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204872 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.966550 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.549742 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994031 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994031 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.523211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.994024 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994024 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 740 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 745 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3298 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176773 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176773 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20283132 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20283132 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 14333312 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333312 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 34616444 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616444 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 34616444 # number of overall hits -system.cpu.dcache.overall_hits::total 34616444 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 89438 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89438 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 280065 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280065 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 369503 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369503 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 369503 # number of overall misses -system.cpu.dcache.overall_misses::total 369503 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4420798500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4420798500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20106086500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20106086500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 24526885000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24526885000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 24526885000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24526885000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20372570 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70176892 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176892 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20283193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20283193 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 14333322 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333322 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 34616515 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616515 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 34616515 # number of overall hits +system.cpu.dcache.overall_hits::total 34616515 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 89440 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89440 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 280055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280055 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 369495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 369495 # number of overall misses +system.cpu.dcache.overall_misses::total 369495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4407640500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4407640500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 19996177500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19996177500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 24403818000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24403818000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 24403818000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24403818000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 20372633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372633 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 34985947 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985947 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 34985947 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985947 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 34986010 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34986010 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 34986010 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34986010 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004390 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019165 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019165 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019164 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.inst 0.010561 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.010561 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.010561 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49428.637716 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49428.637716 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71790.786068 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71790.786068 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66378.040232 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66378.040232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66378.040232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66378.040232 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49280.417039 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49280.417039 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71400.894467 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71400.894467 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66046.409288 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66046.409288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66046.409288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66046.409288 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,30 +403,30 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168546 # number of writebacks system.cpu.dcache.writebacks::total 168546 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136505 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 164624 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164624 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 164624 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164624 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61319 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61319 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143560 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 204879 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204879 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 204879 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204879 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2428683000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2428683000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9985116500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9985116500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12413799500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12413799500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12413799500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12413799500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28125 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28125 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136498 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136498 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 164623 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164623 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 164623 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164623 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61315 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61315 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143557 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143557 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1050 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 791 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1053 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51411598 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51411598 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25472023 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16227.496076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16227.496076 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16222.023236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16222.023236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16222.023236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16222.023236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16222.023236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16222.023236 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # 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Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164780 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.339076 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26240.805315 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4237.620786 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.800806 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129322 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.930128 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32077 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1016 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11992 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18835 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 26240.320965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4237.109970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.800791 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129306 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.930097 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1021 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11978 # 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number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 168546 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143561 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143561 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 360730 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360730 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 360730 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360730 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.164641 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.164641 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911682 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911682 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.461944 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.461944 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73027.352818 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73027.352818 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74225.097798 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74225.097798 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73968.099822 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73968.099822 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73968.099822 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73968.099822 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143558 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143558 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 360707 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 360707 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 360707 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 360707 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.164634 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.164634 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911701 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911701 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461959 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.461959 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461959 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.461959 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72831.601399 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72831.601399 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73812.147583 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73812.147583 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73601.776670 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73601.776670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73601.776670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73601.776670 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,93 +610,93 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114049 # number of writebacks -system.cpu.l2cache.writebacks::total 114049 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35755 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35755 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 114048 # number of writebacks +system.cpu.l2cache.writebacks::total 114048 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35750 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35750 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130882 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 166637 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166637 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 166637 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166637 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2156394000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156394000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 8029638750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8029638750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10186032750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10186032750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10186032750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10186032750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.164641 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.164641 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911682 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911682 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461944 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.461944 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461944 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.461944 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60310.278283 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60310.278283 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61350.214315 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61350.214315 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61127.077120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61127.077120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61127.077120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61127.077120 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 166632 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166632 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 166632 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166632 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2149088750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2149088750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7975554000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975554000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10124642750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10124642750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10124642750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10124642750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.164634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.164634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461959 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.461959 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461959 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.461959 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60114.370629 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60114.370629 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60936.981403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60936.981403 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 217169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 217168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 217149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 217148 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143561 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 890005 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9974400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33873600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578290 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 889959 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9973376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33872128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 529276 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 529253 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 529276 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 529253 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 529276 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 433184000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 529253 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 433172500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 235328991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 235311991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343212750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35754 # Transaction distribution -system.membus.trans_dist::ReadResp 35754 # Transaction distribution -system.membus.trans_dist::Writeback 114049 # Transaction distribution +system.membus.trans_dist::ReadReq 35749 # Transaction distribution +system.membus.trans_dist::ReadResp 35749 # Transaction distribution +system.membus.trans_dist::Writeback 114048 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447321 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447321 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17963840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447310 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17963456 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280685 # Request fanout histogram +system.membus.snoop_fanout::samples 280679 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280685 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280679 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280685 # Request fanout histogram -system.membus.reqLayer0.occupancy 1304586000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 280679 # Request fanout histogram +system.membus.reqLayer0.occupancy 1304618000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602413250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1602414250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f3059ec0c..6d3efb0ae 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022330 # Number of seconds simulated -sim_ticks 22329989500 # Number of ticks simulated -final_tick 22329989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022282 # Number of seconds simulated +sim_ticks 22281815500 # Number of ticks simulated +final_tick 22281815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240121 # Simulator instruction rate (inst/s) -host_op_rate 240121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67367468 # Simulator tick rate (ticks/s) -host_mem_usage 247512 # Number of bytes of host memory used -host_seconds 331.47 # Real time elapsed on the host +host_inst_rate 227860 # Simulator instruction rate (inst/s) +host_op_rate 227860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63789654 # Simulator tick rate (ticks/s) +host_mem_usage 305428 # Number of bytes of host memory used +host_seconds 349.30 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10151616 # Number of bytes read from this memory -system.physmem.bytes_read::total 10639040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296896 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158619 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166235 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114014 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21828223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 454618037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 476446261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21828223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21828223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 326775613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 326775613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 326775613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21828223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 454618037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 803221873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166235 # Number of read requests accepted -system.physmem.writeReqs 114014 # Number of write requests accepted -system.physmem.readBursts 166235 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114014 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10638592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10639040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7296896 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 487168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10151488 # Number of bytes read from this memory +system.physmem.bytes_read::total 10638656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 487168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 487168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296384 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158617 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166229 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114006 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114006 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21863928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455595192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 477459119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21863928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21863928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 327459134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 327459134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 327459134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21863928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455595192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 804918253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166229 # Number of read requests accepted +system.physmem.writeReqs 114006 # Number of write requests accepted +system.physmem.readBursts 166229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114006 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294656 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10638656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7296384 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10441 # Per bank write bursts -system.physmem.perBankRdBursts::1 10459 # Per bank write bursts +system.physmem.perBankRdBursts::0 10438 # Per bank write bursts +system.physmem.perBankRdBursts::1 10454 # Per bank write bursts system.physmem.perBankRdBursts::2 10317 # Per bank write bursts system.physmem.perBankRdBursts::3 10059 # Per bank write bursts -system.physmem.perBankRdBursts::4 10419 # Per bank write bursts -system.physmem.perBankRdBursts::5 10394 # Per bank write bursts -system.physmem.perBankRdBursts::6 9840 # Per bank write bursts -system.physmem.perBankRdBursts::7 10309 # Per bank write bursts -system.physmem.perBankRdBursts::8 10592 # Per bank write bursts -system.physmem.perBankRdBursts::9 10641 # Per bank write bursts -system.physmem.perBankRdBursts::10 10546 # Per bank write bursts -system.physmem.perBankRdBursts::11 10221 # Per bank write bursts -system.physmem.perBankRdBursts::12 10273 # Per bank write bursts -system.physmem.perBankRdBursts::13 10617 # Per bank write bursts -system.physmem.perBankRdBursts::14 10480 # Per bank write bursts -system.physmem.perBankRdBursts::15 10620 # Per bank write bursts -system.physmem.perBankWrBursts::0 7082 # Per bank write bursts -system.physmem.perBankWrBursts::1 7259 # Per bank write bursts -system.physmem.perBankWrBursts::2 7256 # Per bank write bursts +system.physmem.perBankRdBursts::4 10417 # Per bank write bursts +system.physmem.perBankRdBursts::5 10393 # Per bank write bursts +system.physmem.perBankRdBursts::6 9837 # Per bank write bursts +system.physmem.perBankRdBursts::7 10310 # Per bank write bursts +system.physmem.perBankRdBursts::8 10606 # Per bank write bursts +system.physmem.perBankRdBursts::9 10643 # Per bank write bursts +system.physmem.perBankRdBursts::10 10543 # Per bank write bursts +system.physmem.perBankRdBursts::11 10224 # Per bank write bursts +system.physmem.perBankRdBursts::12 10268 # Per bank write bursts +system.physmem.perBankRdBursts::13 10616 # Per bank write bursts +system.physmem.perBankRdBursts::14 10478 # Per bank write bursts +system.physmem.perBankRdBursts::15 10618 # Per bank write bursts +system.physmem.perBankWrBursts::0 7083 # Per bank write bursts +system.physmem.perBankWrBursts::1 7253 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7168 # Per bank write bursts -system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7079 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts -system.physmem.perBankWrBursts::9 6942 # Per bank write bursts -system.physmem.perBankWrBursts::10 7083 # Per bank write bursts -system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::5 7169 # Per bank write bursts +system.physmem.perBankWrBursts::6 6770 # Per bank write bursts +system.physmem.perBankWrBursts::7 7085 # Per bank write bursts +system.physmem.perBankWrBursts::8 7220 # Per bank write bursts +system.physmem.perBankWrBursts::9 6943 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6988 # Per bank write bursts +system.physmem.perBankWrBursts::12 6964 # Per bank write bursts system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts +system.physmem.perBankWrBursts::14 7283 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22329955500 # Total gap between requests +system.physmem.totGap 22281781500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166235 # Read request sizes (log2) +system.physmem.readPktSize::6 166229 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114014 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 53757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114006 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,142 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 51907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.459688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.593638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 345.239241 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18141 34.95% 34.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10684 20.58% 55.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5599 10.79% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2999 5.78% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2733 5.27% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1724 3.32% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1780 3.43% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1211 2.33% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7036 13.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 51907 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6971 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.843208 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.237754 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6969 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.580755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.430431 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.457165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18353 35.17% 35.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10742 20.58% 55.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5641 10.81% 66.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3092 5.92% 72.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2629 5.04% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1694 3.25% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1790 3.43% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1288 2.47% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6960 13.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52189 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6966 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.861757 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.246517 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6964 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6971 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6971 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.350882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.321302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.052955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6113 87.69% 87.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 29 0.42% 88.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 435 6.24% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 209 3.00% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 90 1.29% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 57 0.82% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 19 0.27% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 5 0.07% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 4 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6971 # Writes before turning the bus around for reads -system.physmem.totQLat 5659900500 # Total ticks spent queuing -system.physmem.totMemAccLat 8776675500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34049.02 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6966 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.363676 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.332802 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.079402 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6068 87.12% 87.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.43% 87.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 495 7.11% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 185 2.66% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 91 1.31% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.66% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.30% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.14% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6965 # Writes before turning the bus around for reads +system.physmem.totQLat 5436579750 # Total ticks spent queuing +system.physmem.totMemAccLat 8553223500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32706.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52799.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 476.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 326.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 476.45 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 326.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51456.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 477.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 327.38 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 477.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 327.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.72 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.55 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing -system.physmem.readRowHits 146045 # Number of row buffer hits during reads -system.physmem.writeRowHits 82245 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.14 # Row buffer hit rate for writes -system.physmem.avgGap 79678.98 # Average gap between requests -system.physmem.pageHitRate 81.46 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 9562649000 # Time in different power states -system.physmem.memoryStateTime::REF 745420000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 12015383500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 189642600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 202358520 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 103475625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 110413875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 641035200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 654732000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 367578000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 370610640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1458041520 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1458041520 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 6640293375 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 6800916240 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 7569244500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 7428347250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 16969310820 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 17025420045 # Total energy per rank (pJ) -system.physmem.averagePower::0 760.156668 # Core power per rank (mW) -system.physmem.averagePower::1 762.670135 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 35446 # Transaction distribution -system.membus.trans_dist::ReadResp 35446 # Transaction distribution -system.membus.trans_dist::Writeback 114014 # Transaction distribution -system.membus.trans_dist::ReadExReq 130789 # Transaction distribution -system.membus.trans_dist::ReadExResp 130789 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446484 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17935936 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280249 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280249 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280249 # Request fanout histogram -system.membus.reqLayer0.occupancy 1235861000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1525180500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16618969 # Number of BP lookups -system.cpu.branchPred.condPredicted 10749423 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 361100 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10742405 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7368684 # Number of BTB hits +system.physmem.busUtil 6.29 # Data bus utilization in percentage +system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 146012 # Number of row buffer hits during reads +system.physmem.writeRowHits 81986 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes +system.physmem.avgGap 79511.06 # Average gap between requests +system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190496880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103941750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 641043000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367539120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6553751985 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7617131250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16928894145 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.936312 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12590169250 # Time in different power states +system.physmem_0.memoryStateTime::REF 743860000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8942711000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 203779800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111189375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370694880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6762785805 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7433764500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 16992123720 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.774895 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12284853000 # Time in different power states +system.physmem_1.memoryStateTime::REF 743860000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9248437000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 16624924 # Number of BP lookups +system.cpu.branchPred.condPredicted 10755300 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 362268 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10924107 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7374828 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.594360 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1994688 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3025 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 67.509665 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1991560 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2903 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22640578 # DTB read hits -system.cpu.dtb.read_misses 225727 # DTB read misses -system.cpu.dtb.read_acv 15 # DTB read access violations -system.cpu.dtb.read_accesses 22866305 # DTB read accesses -system.cpu.dtb.write_hits 15860065 # DTB write hits -system.cpu.dtb.write_misses 44717 # DTB write misses -system.cpu.dtb.write_acv 7 # DTB write access violations -system.cpu.dtb.write_accesses 15904782 # DTB write accesses -system.cpu.dtb.data_hits 38500643 # DTB hits -system.cpu.dtb.data_misses 270444 # DTB misses -system.cpu.dtb.data_acv 22 # DTB access violations -system.cpu.dtb.data_accesses 38771087 # DTB accesses -system.cpu.itb.fetch_hits 13913295 # ITB hits -system.cpu.itb.fetch_misses 31383 # ITB misses +system.cpu.dtb.read_hits 22639897 # DTB read hits +system.cpu.dtb.read_misses 226363 # DTB read misses +system.cpu.dtb.read_acv 23 # DTB read access violations +system.cpu.dtb.read_accesses 22866260 # DTB read accesses +system.cpu.dtb.write_hits 15870343 # DTB write hits +system.cpu.dtb.write_misses 44837 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15915180 # DTB write accesses +system.cpu.dtb.data_hits 38510240 # DTB hits +system.cpu.dtb.data_misses 271200 # DTB misses +system.cpu.dtb.data_acv 24 # DTB access violations +system.cpu.dtb.data_accesses 38781440 # DTB accesses +system.cpu.itb.fetch_hits 13919462 # ITB hits +system.cpu.itb.fetch_misses 31654 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13944678 # ITB accesses +system.cpu.itb.fetch_accesses 13951116 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -342,141 +324,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44659983 # number of cpu cycles simulated +system.cpu.numCycles 44563634 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15776454 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106093576 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16618969 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9363372 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27339445 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 961528 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 166 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5126 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 335016 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13913295 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 207298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15791560 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106158478 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16624924 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9366388 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27217966 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 963396 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 137 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337279 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13919462 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206375 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43937055 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.414672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.131710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43833697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.421846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.133787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24208191 55.10% 55.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538198 3.50% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1405905 3.20% 61.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1524697 3.47% 65.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4231594 9.63% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1847884 4.21% 79.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 684699 1.56% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1071609 2.44% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7424278 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24095007 54.97% 54.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1538131 3.51% 58.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1406372 3.21% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1524721 3.48% 65.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4235690 9.66% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846144 4.21% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685371 1.56% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070354 2.44% 83.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7431907 16.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43937055 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372122 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.375585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15090542 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9411892 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18462094 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 590748 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 381779 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3738870 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100752 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103984898 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 316746 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 381779 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15474298 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6446400 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97317 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18646914 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2890347 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102848317 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4603 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 150963 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 325598 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2361182 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61896036 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124089387 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123759844 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 329542 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43833697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.373060 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.382177 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15105656 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9282610 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18470395 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 592044 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 382992 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3741910 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100605 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104048931 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 315835 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 382992 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15490766 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6387964 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 95966 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18655378 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2820631 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102900646 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4493 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 152365 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 320462 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2296242 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61929819 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124171537 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123841536 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 330000 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9349155 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5813 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5869 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2465054 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23265818 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16448253 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1251433 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 545590 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91286622 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5695 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89090659 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79052 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11213817 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4716109 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1112 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43937055 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.027688 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.246728 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9382938 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5791 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5849 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2464589 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23265416 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16459353 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1262626 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 544604 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91320451 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5681 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89124415 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 80151 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11242959 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4725710 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1098 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43833697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.033240 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.247678 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17318675 39.42% 39.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5798510 13.20% 52.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5098508 11.60% 64.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4414835 10.05% 74.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4342383 9.88% 84.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2650303 6.03% 90.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1951252 4.44% 94.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1378643 3.14% 97.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 983946 2.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17209661 39.26% 39.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5800175 13.23% 52.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5098270 11.63% 64.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4410681 10.06% 74.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4347575 9.92% 84.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649961 6.05% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1950790 4.45% 94.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1381860 3.15% 97.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 984724 2.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43937055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43833697 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243742 9.63% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1177038 46.48% 56.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1111319 43.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 244354 9.65% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1175209 46.41% 56.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1112799 43.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49642313 55.72% 55.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44169 0.05% 55.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49663354 55.72% 55.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44187 0.05% 55.77% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122147 0.14% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121699 0.14% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39048 0.04% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 122171 0.14% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121874 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39065 0.04% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued @@ -498,84 +480,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23057514 25.88% 81.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16063627 18.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23057459 25.87% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16076160 18.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89090659 # Type of FU issued -system.cpu.iq.rate 1.994865 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2532099 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224114042 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102090455 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87155295 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 615482 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 436927 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 301089 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91314862 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307896 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1660010 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89124415 # Type of FU issued +system.cpu.iq.rate 1.999936 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2532362 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028414 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224079080 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102152200 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87178162 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615960 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 437940 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 301333 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91348643 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 308134 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1658507 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2989180 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6359 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21743 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1834876 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2988778 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6943 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21591 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1845976 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2985 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 325715 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3051 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 325532 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 381779 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1212086 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4898049 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100815278 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 146031 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23265818 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16448253 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5611 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3372 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4875472 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21743 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 149411 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 157245 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 306656 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88317091 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22866843 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 773568 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 382992 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1216204 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4841557 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100851766 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 147146 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23265416 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16459353 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5598 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3356 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4819285 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21591 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 151679 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 156559 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 308238 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88344034 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22866899 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 780381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9522961 # number of nop insts executed -system.cpu.iew.exec_refs 38771937 # number of memory reference insts executed -system.cpu.iew.exec_branches 15172750 # Number of branches executed -system.cpu.iew.exec_stores 15905094 # Number of stores executed -system.cpu.iew.exec_rate 1.977544 # Inst execution rate -system.cpu.iew.wb_sent 87870804 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87456384 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33898733 # num instructions producing a value -system.cpu.iew.wb_consumers 44340261 # num instructions consuming a value +system.cpu.iew.exec_nop 9525634 # number of nop insts executed +system.cpu.iew.exec_refs 38782381 # number of memory reference insts executed +system.cpu.iew.exec_branches 15172546 # Number of branches executed +system.cpu.iew.exec_stores 15915482 # Number of stores executed +system.cpu.iew.exec_rate 1.982424 # Inst execution rate +system.cpu.iew.wb_sent 87895909 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87479495 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33899568 # num instructions producing a value +system.cpu.iew.wb_consumers 44349597 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.958272 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764514 # average fanout of values written-back +system.cpu.iew.wb_rate 1.963024 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764372 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9275726 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9308985 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 262115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42571128 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.075131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.882631 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 263562 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42463328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.080399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.884681 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21025343 49.39% 49.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6328820 14.87% 64.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2946361 6.92% 71.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1760662 4.14% 75.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1654958 3.89% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1139679 2.68% 81.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1203795 2.83% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795933 1.87% 86.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5715577 13.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20917493 49.26% 49.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6333939 14.92% 64.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2944595 6.93% 71.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1757333 4.14% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1653620 3.89% 79.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1138333 2.68% 81.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1205391 2.84% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 793939 1.87% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5718685 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42571128 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42463328 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -621,238 +603,344 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5715577 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5718685 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133154607 # The number of ROB reads -system.cpu.rob.rob_writes 196602232 # The number of ROB writes -system.cpu.timesIdled 47762 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 722928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133076958 # The number of ROB reads +system.cpu.rob.rob_writes 196673244 # The number of ROB writes +system.cpu.timesIdled 48172 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 729937 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.561113 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561113 # CPI: Total CPI of All Threads -system.cpu.ipc 1.782172 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.782172 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116877675 # number of integer regfile reads -system.cpu.int_regfile_writes 57921110 # number of integer regfile writes -system.cpu.fp_regfile_reads 255696 # number of floating regfile reads -system.cpu.fp_regfile_writes 241715 # number of floating regfile writes -system.cpu.misc_regfile_reads 38130 # number of misc regfile reads +system.cpu.cpi 0.559903 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.559903 # CPI: Total CPI of All Threads +system.cpu.ipc 1.786025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.786025 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116925772 # number of integer regfile reads +system.cpu.int_regfile_writes 57936362 # number of integer regfile writes +system.cpu.fp_regfile_reads 255891 # number of floating regfile reads +system.cpu.fp_regfile_writes 241873 # number of floating regfile writes +system.cpu.misc_regfile_reads 38152 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 157630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157629 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143405 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143405 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191099 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579901 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 771000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6115136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23962624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30077760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 469974 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 469974 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 469974 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 403921992 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 144682208 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 321839246 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 93501 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.858110 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13804656 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 95549 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 144.477242 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18832337250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.858110 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936942 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936942 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201381 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.852002 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34090259 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205477 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.907907 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4071.852002 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994104 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994104 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2773 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 71020605 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71020605 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20525911 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20525911 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13564288 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13564288 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34090199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34090199 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34090199 # number of overall hits +system.cpu.dcache.overall_hits::total 34090199 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 268215 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 268215 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1049089 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1049089 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1317304 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1317304 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1317304 # number of overall misses +system.cpu.dcache.overall_misses::total 1317304 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16911598996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16911598996 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85714857886 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85714857886 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102626456882 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102626456882 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102626456882 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102626456882 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20794126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20794126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35407503 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35407503 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35407503 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35407503 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012899 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012899 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071790 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071790 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037204 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63052.398248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63052.398248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81704.086008 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81704.086008 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77906.433809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77906.433809 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6293239 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 146230 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.036579 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168920 # number of writebacks +system.cpu.dcache.writebacks::total 168920 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206147 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 206147 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905681 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 905681 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1111828 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1111828 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1111828 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1111828 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62068 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62068 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143408 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143408 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205476 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205476 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205476 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205476 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3016288253 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3016288253 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13368781676 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13368781676 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16385069929 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16385069929 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16385069929 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16385069929 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002985 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002985 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.016393 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.016393 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005803 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005803 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48596.511133 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48596.511133 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93222.007670 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93222.007670 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 93674 # number of replacements +system.cpu.icache.tags.tagsinuse 1918.313943 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13810732 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 95722 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 144.279601 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18796346250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.313943 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936677 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936677 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1480 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 377 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1489 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 370 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27922137 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27922137 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13804656 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13804656 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13804656 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13804656 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13804656 # number of overall hits -system.cpu.icache.overall_hits::total 13804656 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 108638 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 108638 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 108638 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 108638 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 108638 # number of overall misses -system.cpu.icache.overall_misses::total 108638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2007932205 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2007932205 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2007932205 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2007932205 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2007932205 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2007932205 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13913294 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13913294 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13913294 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13913294 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13913294 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13913294 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007808 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007808 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007808 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007808 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007808 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007808 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18482.779552 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18482.779552 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18482.779552 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18482.779552 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18482.779552 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18482.779552 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27934642 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27934642 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13810732 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13810732 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13810732 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13810732 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13810732 # number of overall hits +system.cpu.icache.overall_hits::total 13810732 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 108728 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 108728 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 108728 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 108728 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 108728 # number of overall misses +system.cpu.icache.overall_misses::total 108728 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2006428959 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2006428959 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2006428959 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2006428959 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2006428959 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2006428959 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13919460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13919460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13919460 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13919460 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13919460 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13919460 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007811 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007811 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007811 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007811 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007811 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007811 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18453.654615 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18453.654615 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18453.654615 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18453.654615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18453.654615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18453.654615 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1061 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 66.312500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13088 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 13088 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 13088 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 13088 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 13088 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 13088 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95550 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 95550 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 95550 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 95550 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 95550 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 95550 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1542742292 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1542742292 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1542742292 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1542742292 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1542742292 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1542742292 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006868 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006868 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006868 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006868 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006868 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006868 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16145.916190 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16145.916190 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16145.916190 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16145.916190 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16145.916190 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16145.916190 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13005 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 13005 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 13005 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 13005 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 13005 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 13005 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95723 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 95723 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 95723 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 95723 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 95723 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 95723 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1546277535 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1546277535 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1546277535 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1546277535 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1546277535 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1546277535 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006877 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006877 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006877 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16153.667718 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16153.667718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16153.667718 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16153.667718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16153.667718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16153.667718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132334 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30651.520219 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 161905 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164393 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.984866 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132323 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30650.354019 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 162059 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164389 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.985826 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26718.655997 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2108.933972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1823.930250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.815389 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064360 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.055662 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.935410 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32059 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3021 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28588 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 26718.517593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2110.418463 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1821.417963 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.815384 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064405 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.055585 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.935375 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32066 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3005 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28611 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978363 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4067526 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4067526 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 87933 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34250 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 122183 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168931 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168931 # 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Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 88110 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34237 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 122347 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168920 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168920 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12623 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12623 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 88110 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46860 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 134970 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 88110 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46860 # number of overall hits +system.cpu.l2cache.overall_hits::total 134970 # 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number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34089405 # number of overall hits -system.cpu.dcache.overall_hits::total 34089405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268059 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1049159 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1049159 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1317218 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1317218 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1317218 # number of overall misses -system.cpu.dcache.overall_misses::total 1317218 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17086669746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17086669746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 86915323054 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 86915323054 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104001992800 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104001992800 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104001992800 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104001992800 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20793246 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20793246 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35406623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35406623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35406623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35406623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012892 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071794 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071794 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017241 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017241 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037203 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037203 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63742.197598 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63742.197598 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82842.851326 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82842.851326 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78955.793802 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78955.793802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78955.793802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78955.793802 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6406656 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146327 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.783143 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168931 # number of writebacks -system.cpu.dcache.writebacks::total 168931 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205979 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205979 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905755 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 905755 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1111734 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1111734 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1111734 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1111734 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62080 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62080 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143404 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143404 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205484 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205484 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205484 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205484 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3049561754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3049561754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13566762195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13566762195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16616323949 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16616323949 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16616323949 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16616323949 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002986 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002986 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017241 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017241 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005804 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005804 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49123.095264 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49123.095264 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94605.186710 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94605.186710 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 157790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157789 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191445 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579874 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 771319 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6126208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23961408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30087616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 470120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 470120 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 470120 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403980000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 144944965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 321950247 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 35442 # Transaction distribution +system.membus.trans_dist::ReadResp 35442 # Transaction distribution +system.membus.trans_dist::Writeback 114006 # Transaction distribution +system.membus.trans_dist::ReadExReq 130787 # Transaction distribution +system.membus.trans_dist::ReadExResp 130787 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17935040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 280235 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 280235 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 280235 # Request fanout histogram +system.membus.reqLayer0.occupancy 1235714000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1525262750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c949b9a6e..e5a2f02e5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057847 # Number of seconds simulated -sim_ticks 57847312000 # Number of ticks simulated -final_tick 57847312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057816 # Number of seconds simulated +sim_ticks 57815555000 # Number of ticks simulated +final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186854 # Simulator instruction rate (inst/s) -host_op_rate 238959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152421830 # Simulator tick rate (ticks/s) -host_mem_usage 261476 # Number of bytes of host memory used -host_seconds 379.52 # Real time elapsed on the host +host_inst_rate 199176 # Simulator instruction rate (inst/s) +host_op_rate 254717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162383906 # Simulator tick rate (ticks/s) +host_mem_usage 320240 # Number of bytes of host memory used +host_seconds 356.04 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8247680 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 8247808 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 128870 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 142576720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142576720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92880098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92880098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92880098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 142576720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235456818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128870 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 142657249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 142657249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128872 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128870 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247680 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::0 8159 # Per bank write bursts system.physmem.perBankRdBursts::1 8375 # Per bank write bursts system.physmem.perBankRdBursts::2 8229 # Per bank write bursts system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8319 # Per bank write bursts +system.physmem.perBankRdBursts::4 8320 # Per bank write bursts system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8089 # Per bank write bursts +system.physmem.perBankRdBursts::6 8088 # Per bank write bursts system.physmem.perBankRdBursts::7 7970 # Per bank write bursts system.physmem.perBankRdBursts::8 8071 # Per bank write bursts -system.physmem.perBankRdBursts::9 7641 # Per bank write bursts -system.physmem.perBankRdBursts::10 7819 # Per bank write bursts +system.physmem.perBankRdBursts::9 7640 # Per bank write bursts +system.physmem.perBankRdBursts::10 7820 # Per bank write bursts system.physmem.perBankRdBursts::11 7830 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts system.physmem.perBankRdBursts::14 7977 # Per bank write bursts system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5181 # Per bank write bursts +system.physmem.perBankWrBursts::0 5183 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5198 # Per bank write bursts -system.physmem.perBankWrBursts::7 5047 # Per bank write bursts +system.physmem.perBankWrBursts::6 5194 # Per bank write bursts +system.physmem.perBankWrBursts::7 5048 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::9 5086 # Per bank write bursts +system.physmem.perBankWrBursts::10 5252 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts @@ -78,14 +78,14 @@ system.physmem.perBankWrBursts::14 5451 # Pe system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57847280000 # Total gap between requests +system.physmem.totGap 57815523000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128870 # Read request sizes (log2) +system.physmem.readPktSize::6 128872 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,7 +95,7 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 83951 # Write request sizes (log2) system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -189,97 +189,110 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.780687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.561409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.824723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12139 31.63% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8088 21.07% 52.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4086 10.65% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2872 7.48% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2530 6.59% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1664 4.34% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1273 3.32% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1227 3.20% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4500 11.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38379 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.981187 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 361.178240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.276377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.259366 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.777117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4528 87.82% 87.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 480 9.31% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 121 2.35% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 14 0.27% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads -system.physmem.totQLat 1539171500 # Total ticks spent queuing -system.physmem.totMemAccLat 3955390250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11944.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 1505377000 # Total ticks spent queuing +system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30694.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.88 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.84 # Data bus utilization in percentage system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing -system.physmem.readRowHits 112176 # Number of row buffer hits during reads -system.physmem.writeRowHits 62224 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes -system.physmem.avgGap 271811.90 # Average gap between requests -system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 32236826000 # Time in different power states -system.physmem.memoryStateTime::REF 1931540000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23675959000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 151237800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 138899880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 82520625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 75788625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 512678400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 492078600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 272322000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 271486080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3778092240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3778092240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 11712850200 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 11277598770 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 24432156750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 24813956250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 40941858015 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 40847900445 # Total energy per rank (pJ) -system.physmem.averagePower::0 707.794027 # Core power per rank (mW) -system.physmem.averagePower::1 706.169709 # Core power per rank (mW) -system.cpu.branchPred.lookups 14825675 # Number of BP lookups -system.cpu.branchPred.condPredicted 9917897 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 395023 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9456669 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6745546 # Number of BTB hits +system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing +system.physmem.readRowHits 112203 # Number of row buffer hits during reads +system.physmem.writeRowHits 62134 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes +system.physmem.avgGap 271660.13 # Average gap between requests +system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.837327 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.292941 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 14822198 # Number of BP lookups +system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.331100 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719567 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -301,6 +314,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -322,6 +343,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -343,6 +372,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -365,89 +402,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115694624 # number of cpu cycles simulated +system.cpu.numCycles 115631110 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1146301 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.631452 # CPI: cycles per instruction -system.cpu.ipc 0.612951 # IPC: instructions per cycle -system.cpu.tickCycles 96938261 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18756363 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156422 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.596798 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42665450 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160518 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.798540 # Average number of references to valid blocks. +system.cpu.cpi 1.630556 # CPI: cycles per instruction +system.cpu.ipc 0.613288 # IPC: instructions per cycle +system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156428 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.596798 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993310 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993310 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.581764 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 750 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86015580 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86015580 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 22989734 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22989734 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19643878 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643878 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 22989229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 19643835 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 42633612 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42633612 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 42633612 # number of overall hits -system.cpu.dcache.overall_hits::total 42633612 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 56058 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56058 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 206023 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206023 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 262081 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262081 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 262081 # number of overall misses -system.cpu.dcache.overall_misses::total 262081 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2156088187 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2156088187 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15241867750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15241867750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17397955937 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17397955937 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17397955937 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17397955937 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 23045792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23045792 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 42633064 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 42633064 # number of overall hits +system.cpu.dcache.overall_hits::total 42633064 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 56065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 206066 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 262131 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 262131 # number of overall misses +system.cpu.dcache.overall_misses::total 262131 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2147242437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15196521000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 17343763437 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 17343763437 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42895693 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42895693 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42895693 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42895693 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002432 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002432 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010379 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010379 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38461.739395 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38461.739395 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73981.389214 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73981.389214 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66383.888710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66383.888710 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 42895195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42895195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002433 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.006111 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.006111 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38299.160564 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73745.892093 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,32 +493,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128433 # number of writebacks -system.cpu.dcache.writebacks::total 128433 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2574 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2574 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 98989 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 98989 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 101563 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101563 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 101563 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101563 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53484 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53484 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107034 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 160518 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160518 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 160518 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160518 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1995361313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1995361313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7633992250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7633992250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9629353563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9629353563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9629353563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9629353563 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks +system.cpu.dcache.writebacks::total 128441 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2577 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99030 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 101607 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 101607 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53488 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107036 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 160524 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 160524 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1987609313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7609976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9597585313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9597585313 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses @@ -490,68 +527,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37307.630562 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37307.630562 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71323.058561 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71323.058561 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37159.910877 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71097.350424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59789.098907 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59789.098907 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42703 # number of replacements -system.cpu.icache.tags.tagsinuse 1858.978148 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25082437 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44745 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 560.564018 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42682 # number of replacements +system.cpu.icache.tags.tagsinuse 1858.929385 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25083355 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44724 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 560.847755 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1858.978148 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.907704 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.907704 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1858.929385 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.907680 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.907680 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 804 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 803 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1117 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50299111 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50299111 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25082437 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25082437 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25082437 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25082437 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25082437 # number of overall hits -system.cpu.icache.overall_hits::total 25082437 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44746 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44746 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44746 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44746 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44746 # number of overall misses -system.cpu.icache.overall_misses::total 44746 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 897678738 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 897678738 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 897678738 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 897678738 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 897678738 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 897678738 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25127183 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25127183 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25127183 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25127183 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25127183 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20061.653287 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50300884 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50300884 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25083355 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25083355 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25083355 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25083355 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25083355 # number of overall hits +system.cpu.icache.overall_hits::total 25083355 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44725 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44725 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44725 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44725 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44725 # number of overall misses +system.cpu.icache.overall_misses::total 44725 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 895927489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 895927489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 895927489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 895927489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 895927489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 895927489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25128080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25128080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25128080 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25128080 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25128080 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25128080 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20031.917026 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20031.917026 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20031.917026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20031.917026 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -560,103 +597,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44746 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44746 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44746 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44746 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44746 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44746 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 806263262 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 806263262 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 806263262 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 806263262 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 806263262 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 806263262 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001781 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001781 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18018.666741 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18018.666741 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44725 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44725 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44725 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44725 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44725 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44725 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804564511 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 804564511 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804564511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 804564511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804564511 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 804564511 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17989.145020 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95732 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29937.969910 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99708 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126850 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.786031 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95733 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29936.958460 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99697 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126852 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26706.762922 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3231.206988 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.815026 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098609 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.913634 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9726 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19542 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3229.441462 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098555 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9778 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19493 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2903460 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2903460 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 71567 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71567 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128433 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128433 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4753 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4753 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 76320 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 76320 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 76320 # number of overall hits -system.cpu.l2cache.overall_hits::total 76320 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 26663 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26663 # number of ReadReq misses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949677 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2903408 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2903408 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 71548 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71548 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128441 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128441 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 4755 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4755 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 76303 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 76303 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 76303 # number of overall hits +system.cpu.l2cache.overall_hits::total 76303 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 26665 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26665 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.inst 102281 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 128944 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128944 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 128944 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128433 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128433 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 205264 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 205264 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 205264 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 205264 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271434 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.271434 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955594 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955594 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628186 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.628186 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628186 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.628186 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74534.017177 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74534.017177 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73125.934924 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73125.934924 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73417.097732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73417.097732 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 128946 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128946 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 128946 # number of overall misses +system.cpu.l2cache.overall_misses::total 128946 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978063750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1978063750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7455355000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7455355000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9433418750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9433418750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9433418750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9433418750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 98213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 98213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128441 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128441 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107036 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107036 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 205249 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205249 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 205249 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205249 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271502 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.271502 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955576 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955576 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628242 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.628242 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628242 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.628242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74182.027002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74182.027002 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72890.908380 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,52 +710,52 @@ system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26590 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26590 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26592 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 128871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 128871 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128871 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1644904750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1644904750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6188348750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6188348750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7833253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7833253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7833253500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7833253500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270691 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270691 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627831 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627831 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 128873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 128873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128873 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1635105500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1635105500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6164329000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6164329000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7799434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7799434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7799434500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7799434500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955576 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955576 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627886 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627886 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61488.624398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61488.624398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60268.564054 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60268.564054 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449469 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 538960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2863680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21356544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128441 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107036 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107036 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89449 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449489 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 538938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2862336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18493760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21356096 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333697 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333690 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -727,41 +764,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 333697 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333697 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295281500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68080238 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268447937 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26589 # Transaction distribution -system.membus.trans_dist::ReadResp 26589 # Transaction distribution +system.membus.trans_dist::ReadReq 26591 # Transaction distribution +system.membus.trans_dist::ReadResp 26591 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution system.membus.trans_dist::ReadExReq 102281 # Transaction distribution system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212821 # Request fanout histogram +system.membus.snoop_fanout::samples 212823 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212821 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212821 # Request fanout histogram -system.membus.reqLayer0.occupancy 929388500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 212823 # Request fanout histogram +system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1213397000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index d04d5cf1b..6394c9beb 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.032615 # Number of seconds simulated -sim_ticks 32615215000 # Number of ticks simulated -final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033020 # Number of seconds simulated +sim_ticks 33019504000 # Number of ticks simulated +final_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125661 # Simulator instruction rate (inst/s) -host_op_rate 160706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57800178 # Simulator tick rate (ticks/s) -host_mem_usage 335740 # Number of bytes of host memory used -host_seconds 564.28 # Real time elapsed on the host +host_inst_rate 123822 # Simulator instruction rate (inst/s) +host_op_rate 158353 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57659893 # Simulator tick rate (ticks/s) +host_mem_usage 322352 # Number of bytes of host memory used +host_seconds 572.66 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory -system.physmem.bytes_read::total 9977536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory -system.physmem.bytes_written::total 6303424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory -system.physmem.num_reads::total 155899 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 98491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 155899 # Number of read requests accepted -system.physmem.writeReqs 98491 # Number of write requests accepted -system.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory +system.physmem.bytes_read::total 9307712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory +system.physmem.bytes_written::total 6262016 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145433 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97844 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145433 # Number of read requests accepted +system.physmem.writeReqs 97844 # Number of write requests accepted +system.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10106 # Per bank write bursts -system.physmem.perBankRdBursts::1 10077 # Per bank write bursts -system.physmem.perBankRdBursts::2 9750 # Per bank write bursts -system.physmem.perBankRdBursts::3 10345 # Per bank write bursts -system.physmem.perBankRdBursts::4 10619 # Per bank write bursts -system.physmem.perBankRdBursts::5 10733 # Per bank write bursts -system.physmem.perBankRdBursts::6 9548 # Per bank write bursts -system.physmem.perBankRdBursts::7 9567 # Per bank write bursts -system.physmem.perBankRdBursts::8 9971 # Per bank write bursts -system.physmem.perBankRdBursts::9 9445 # Per bank write bursts -system.physmem.perBankRdBursts::10 9639 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 8930 # Per bank write bursts -system.physmem.perBankRdBursts::13 9084 # Per bank write bursts -system.physmem.perBankRdBursts::14 9062 # Per bank write bursts -system.physmem.perBankRdBursts::15 9408 # Per bank write bursts -system.physmem.perBankWrBursts::0 6017 # Per bank write bursts -system.physmem.perBankWrBursts::1 6275 # Per bank write bursts -system.physmem.perBankWrBursts::2 6171 # Per bank write bursts -system.physmem.perBankWrBursts::3 6231 # Per bank write bursts -system.physmem.perBankWrBursts::4 6142 # Per bank write bursts -system.physmem.perBankWrBursts::5 6389 # Per bank write bursts -system.physmem.perBankWrBursts::6 6054 # Per bank write bursts -system.physmem.perBankWrBursts::7 6025 # Per bank write bursts -system.physmem.perBankWrBursts::8 6057 # Per bank write bursts -system.physmem.perBankWrBursts::9 6227 # Per bank write bursts -system.physmem.perBankWrBursts::10 6350 # Per bank write bursts -system.physmem.perBankWrBursts::11 5949 # Per bank write bursts -system.physmem.perBankWrBursts::12 6129 # Per bank write bursts -system.physmem.perBankWrBursts::13 6148 # Per bank write bursts -system.physmem.perBankWrBursts::14 6212 # Per bank write bursts -system.physmem.perBankWrBursts::15 6088 # Per bank write bursts +system.physmem.perBankRdBursts::0 9146 # Per bank write bursts +system.physmem.perBankRdBursts::1 9381 # Per bank write bursts +system.physmem.perBankRdBursts::2 9349 # Per bank write bursts +system.physmem.perBankRdBursts::3 9489 # Per bank write bursts +system.physmem.perBankRdBursts::4 9691 # Per bank write bursts +system.physmem.perBankRdBursts::5 9742 # Per bank write bursts +system.physmem.perBankRdBursts::6 9065 # Per bank write bursts +system.physmem.perBankRdBursts::7 9033 # Per bank write bursts +system.physmem.perBankRdBursts::8 9160 # Per bank write bursts +system.physmem.perBankRdBursts::9 8585 # Per bank write bursts +system.physmem.perBankRdBursts::10 8818 # Per bank write bursts +system.physmem.perBankRdBursts::11 8754 # Per bank write bursts +system.physmem.perBankRdBursts::12 8666 # Per bank write bursts +system.physmem.perBankRdBursts::13 8713 # Per bank write bursts +system.physmem.perBankRdBursts::14 8726 # Per bank write bursts +system.physmem.perBankRdBursts::15 9002 # Per bank write bursts +system.physmem.perBankWrBursts::0 5993 # Per bank write bursts +system.physmem.perBankWrBursts::1 6194 # Per bank write bursts +system.physmem.perBankWrBursts::2 6159 # Per bank write bursts +system.physmem.perBankWrBursts::3 6198 # Per bank write bursts +system.physmem.perBankWrBursts::4 6133 # Per bank write bursts +system.physmem.perBankWrBursts::5 6325 # Per bank write bursts +system.physmem.perBankWrBursts::6 6074 # Per bank write bursts +system.physmem.perBankWrBursts::7 6046 # Per bank write bursts +system.physmem.perBankWrBursts::8 6012 # Per bank write bursts +system.physmem.perBankWrBursts::9 6139 # Per bank write bursts +system.physmem.perBankWrBursts::10 6243 # Per bank write bursts +system.physmem.perBankWrBursts::11 5934 # Per bank write bursts +system.physmem.perBankWrBursts::12 6049 # Per bank write bursts +system.physmem.perBankWrBursts::13 6103 # Per bank write bursts +system.physmem.perBankWrBursts::14 6164 # Per bank write bursts +system.physmem.perBankWrBursts::15 6052 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32615126500 # Total gap between requests +system.physmem.totGap 33019298500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155899 # Read request sizes (log2) +system.physmem.readPktSize::6 145433 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 98491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97844 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -197,125 +197,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads -system.physmem.totQLat 7435933847 # Total ticks spent queuing -system.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 778800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads +system.physmem.totQLat 7598607995 # Total ticks spent queuing +system.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 726600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.90 # Data bus utilization in percentage -system.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing -system.physmem.readRowHits 126861 # Number of row buffer hits during reads -system.physmem.writeRowHits 35985 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes -system.physmem.avgGap 128209.15 # Average gap between requests -system.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states -system.physmem.memoryStateTime::REF 1088880000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 352167480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 337674960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 192154875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 184247250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 628633200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 584321400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 319101120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 318206880 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 2129849280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 2129849280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 12060126405 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 11622718665 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 8986386750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 9370077750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 24668419110 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 24547096185 # Total energy per rank (pJ) -system.physmem.averagePower::0 756.489386 # Core power per rank (mW) -system.physmem.averagePower::1 752.768859 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 149976 # Transaction distribution -system.membus.trans_dist::ReadResp 149976 # Transaction distribution -system.membus.trans_dist::Writeback 98491 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 5923 # Transaction distribution -system.membus.trans_dist::ReadExResp 5923 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 254396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254396 # Request fanout histogram -system.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.4 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 17209876 # Number of BP lookups -system.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675638 # Number of BTB hits +system.physmem.busUtil 3.68 # Data bus utilization in percentage +system.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 118226 # Number of row buffer hits during reads +system.physmem.writeRowHits 36119 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes +system.physmem.avgGap 135727.17 # Average gap between requests +system.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.509165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states +system.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ) +system.physmem_1.averagePower 748.955517 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states +system.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 17204705 # Number of BP lookups +system.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7673903 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -358,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -379,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -401,131 +411,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 65230431 # number of cpu cycles simulated +system.cpu.numCycles 66039009 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322461 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31532227 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32193664 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31530881 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32193949 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18671 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18665 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued @@ -551,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94860274 # Type of FU issued -system.cpu.iq.rate 1.454233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 94858951 # Type of FU issued +system.cpu.iq.rate 1.436408 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9866 # number of nop insts executed -system.cpu.iew.exec_refs 44709300 # number of memory reference insts executed -system.cpu.iew.exec_branches 14252629 # Number of branches executed -system.cpu.iew.exec_stores 20981511 # Number of stores executed -system.cpu.iew.exec_rate 1.440176 # Inst execution rate -system.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93464426 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44933898 # num instructions producing a value -system.cpu.iew.wb_consumers 76510027 # num instructions consuming a value +system.cpu.iew.exec_nop 9863 # number of nop insts executed +system.cpu.iew.exec_refs 44710370 # number of memory reference insts executed +system.cpu.iew.exec_branches 14251746 # Number of branches executed +system.cpu.iew.exec_stores 20982459 # Number of stores executed +system.cpu.iew.exec_rate 1.422528 # Inst execution rate +system.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93463063 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44927637 # num instructions producing a value +system.cpu.iew.wb_consumers 76497349 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.432835 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back +system.cpu.iew.wb_rate 1.415271 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 706597 1.10% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 586126 0.91% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3803876 5.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64238392 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -674,506 +684,528 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction -system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3803876 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 157213253 # The number of ROB reads -system.cpu.rob.rob_writes 195483388 # The number of ROB writes -system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 157616533 # The number of ROB reads +system.cpu.rob.rob_writes 195472136 # The number of ROB writes +system.cpu.timesIdled 23660 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 744970 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.919935 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads -system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102236524 # number of integer regfile reads -system.cpu.int_regfile_writes 56794814 # number of integer regfile writes +system.cpu.cpi 0.931339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.931339 # CPI: Total CPI of All Threads +system.cpu.ipc 1.073723 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.073723 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102238235 # number of integer regfile reads +system.cpu.int_regfile_writes 56792997 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346002142 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804540 # number of cc regfile writes -system.cpu.misc_regfile_reads 44207937 # number of misc regfile reads +system.cpu.cc_regfile_reads 345997909 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804494 # number of cc regfile writes +system.cpu.misc_regfile_reads 44208348 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 261186 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 323466 # number of replacements -system.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323978 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.239069 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1054590000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.438944 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996951 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996951 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485280 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.769602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40441610 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485792 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.248818 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 148406000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.769602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 84635072 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84635072 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21513403 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21513403 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18834640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18834640 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 62245 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 62245 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40348043 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40348043 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40410288 # number of overall hits +system.cpu.dcache.overall_hits::total 40410288 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 550665 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 550665 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1015261 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1015261 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 66581 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 66581 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1565926 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1565926 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1632507 # number of overall misses +system.cpu.dcache.overall_misses::total 1632507 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8659099753 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8659099753 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14372727937 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14372727937 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4891750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4891750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23031827690 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23031827690 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23031827690 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23031827690 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 41913969 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41913969 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42042795 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42042795 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024958 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.024958 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051147 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051147 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037360 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037360 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038830 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038830 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15724.805014 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15724.805014 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14156.682801 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14156.682801 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8942.870201 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8942.870201 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14708.120109 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14708.120109 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14108.256620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14108.256620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2883834 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 127457 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.625937 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 264417 # number of writebacks +system.cpu.dcache.writebacks::total 264417 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 250985 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 250985 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866735 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 866735 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1117720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1117720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1117720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1117720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148526 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148526 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 448206 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 448206 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485803 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485803 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2833367604 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2833367604 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2154211948 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2154211948 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1934780357 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1934780357 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4987579552 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4987579552 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6922359909 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6922359909 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013582 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013582 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291843 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291843 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010693 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010693 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9454.643633 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9454.643633 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14503.938354 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14503.938354 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51461.030322 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51461.030322 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11127.873237 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11127.873237 # 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Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 267 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 351 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45851126 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45851126 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22431935 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22431935 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22431935 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22431935 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22431935 # number of overall hits -system.cpu.icache.overall_hits::total 22431935 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 331634 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 331634 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 331634 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 331634 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 331634 # number of overall misses -system.cpu.icache.overall_misses::total 331634 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2861760504 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2861760504 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2861760504 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2861760504 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2861760504 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2861760504 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22763569 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22763569 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22763569 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22763569 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22763569 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22763569 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014569 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014569 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014569 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8629.273549 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8629.273549 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8629.273549 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8629.273549 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 97738 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12080 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8.090894 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 45841045 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45841045 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22426703 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22426703 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22426703 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22426703 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22426703 # number of overall hits +system.cpu.icache.overall_hits::total 22426703 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 332124 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 332124 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 332124 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 332124 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 332124 # number of overall misses +system.cpu.icache.overall_misses::total 332124 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3299467842 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3299467842 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3299467842 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3299467842 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3299467842 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3299467842 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22758827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22758827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22758827 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22758827 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22758827 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22758827 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014593 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014593 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014593 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014593 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014593 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014593 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9934.445695 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 9934.445695 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 9934.445695 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 9934.445695 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 226617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 46 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14091 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.082393 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7645 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7645 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7645 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7645 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7645 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7645 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323989 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323989 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323989 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323989 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323989 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323989 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325660123 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2325660123 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325660123 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2325660123 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325660123 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2325660123 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014233 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014233 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014233 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7178.207047 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7178.207047 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8733 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8733 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8733 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8733 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8733 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8733 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323391 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323391 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323391 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323391 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323391 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323391 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2699093031 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2699093031 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2699093031 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2699093031 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2699093031 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2699093031 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014209 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014209 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8346.221852 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8346.221852 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 3266027 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 304781 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2719229 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 25673 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 17215 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 199121 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 314405 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 140078 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16107.104250 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 874451 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 156393 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.591369 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.num_hwpf_issued 812320 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826786 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 12696 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2632.995635 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.700814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018430 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.103150 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.160705 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.983100 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 869 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15446 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 244 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2641163503 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2800231003 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159067500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2641163503 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15016026778 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.090752 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.049420 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8240 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8240 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9199 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 39322 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 48521 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9199 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 39322 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 161120 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 569300762 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2303617903 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872918665 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 11396158527 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39006 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39006 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 539005297 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 539005297 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 569300762 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2842623200 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3411923962 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 569300762 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2842623200 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14808082489 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092170 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060976 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.039835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.039835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.047662 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059964 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.293549 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 76807.098020 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73361.555900 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73579.913798 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61348.605998 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66866.002028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66866.002028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72550.483276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63167.394888 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199118 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61887.244483 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74114.210894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71321.930066 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 101210.121999 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65413.264199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65413.264199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70318.500484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 485318 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.841997 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40443714 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485830 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.246638 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 139928000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.841997 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997738 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997738 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84640426 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84640426 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21515343 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21515343 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834765 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834765 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 62288 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 62288 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15377 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15377 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40350108 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40350108 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40412396 # number of overall hits -system.cpu.dcache.overall_hits::total 40412396 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 551365 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 551365 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1015136 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1015136 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 66556 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 66556 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 549 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 549 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1566501 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1566501 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1633057 # number of overall misses -system.cpu.dcache.overall_misses::total 1633057 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8548612161 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8548612161 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13150540915 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13150540915 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5021750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5021750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21699153076 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21699153076 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21699153076 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21699153076 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22066708 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22066708 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41916609 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41916609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42045453 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42045453 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024986 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024986 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051141 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051141 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516563 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.516563 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034472 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034472 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037372 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037372 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038840 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038840 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15504.451971 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15504.451971 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12954.462176 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12954.462176 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9147.085610 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9147.085610 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13851.988014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13851.988014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13287.443779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13287.443779 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2567726 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 127351 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.214286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20.162590 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 256573 # number of writebacks -system.cpu.dcache.writebacks::total 256573 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 251643 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 251643 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866615 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866615 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 549 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 549 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118258 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118258 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118258 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 169293 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 137181 # Transaction distribution +system.membus.trans_dist::ReadResp 137181 # Transaction distribution +system.membus.trans_dist::Writeback 97844 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 8252 # Transaction distribution +system.membus.trans_dist::ReadExResp 8252 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 243283 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 243283 # Request fanout histogram +system.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index b1db16392..23c0d1c87 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011000 # Number of ticks simulated final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264072 # Simulator instruction rate (inst/s) -host_op_rate 337712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182321320 # Simulator tick rate (ticks/s) -host_mem_usage 304496 # Number of bytes of host memory used -host_seconds 268.54 # Real time elapsed on the host +host_inst_rate 1376675 # Simulator instruction rate (inst/s) +host_op_rate 1760576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 950486092 # Simulator tick rate (ticks/s) +host_mem_usage 308184 # Number of bytes of host memory used +host_seconds 51.51 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1606621596 # Wr system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 100925135 # Transaction distribution -system.membus.trans_dist::ReadResp 100941054 # Transaction distribution -system.membus.trans_dist::WriteReq 19849901 # Transaction distribution -system.membus.trans_dist::WriteResp 19849901 # Transaction distribution -system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution -system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930618 # Request fanout histogram -system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 120930618 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction +system.membus.trans_dist::ReadReq 100925135 # Transaction distribution +system.membus.trans_dist::ReadResp 100941054 # Transaction distribution +system.membus.trans_dist::WriteReq 19849901 # Transaction distribution +system.membus.trans_dist::WriteResp 19849901 # Transaction distribution +system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution +system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 120930618 # Request fanout histogram +system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 120930618 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index baa7e0631..938385651 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.127294 # Nu sim_ticks 127293983000 # Number of ticks simulated final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 949441 # Simulator instruction rate (inst/s) -host_op_rate 1212170 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1717378261 # Simulator tick rate (ticks/s) -host_mem_usage 313972 # Number of bytes of host memory used -host_seconds 74.12 # Real time elapsed on the host +host_inst_rate 894668 # Simulator instruction rate (inst/s) +host_op_rate 1142240 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618302823 # Simulator tick rate (ticks/s) +host_mem_usage 317432 # Number of bytes of host memory used +host_seconds 78.66 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 42187194 # To system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 25532 # Transaction distribution -system.membus.trans_dist::ReadResp 25532 # Transaction distribution -system.membus.trans_dist::Writeback 83909 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214631 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214631 # Request fanout histogram -system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,143 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits +system.cpu.dcache.overall_hits::total 42576328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses +system.cpu.dcache.overall_misses::total 177384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks +system.cpu.dcache.writebacks::total 128239 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. @@ -439,143 +584,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits -system.cpu.dcache.overall_hits::total 42576328 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses -system.cpu.dcache.overall_misses::total 177384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks -system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution @@ -609,5 +617,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 28362000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 25532 # Transaction distribution +system.membus.trans_dist::ReadResp 25532 # Transaction distribution +system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214631 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214631 # Request fanout histogram +system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 38d19f012..e7cd333d6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.200149 # Number of seconds simulated -sim_ticks 1200148658000 # Number of ticks simulated -final_tick 1200148658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.199774 # Number of seconds simulated +sim_ticks 1199774280000 # Number of ticks simulated +final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 401299 # Simulator instruction rate (inst/s) -host_op_rate 401299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263701147 # Simulator tick rate (ticks/s) -host_mem_usage 236908 # Number of bytes of host memory used -host_seconds 4551.17 # Real time elapsed on the host +host_inst_rate 344306 # Simulator instruction rate (inst/s) +host_op_rate 344306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226179780 # Simulator tick rate (ticks/s) +host_mem_usage 294788 # Number of bytes of host memory used +host_seconds 5304.52 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125506304 # Number of bytes read from this memory -system.physmem.bytes_read::total 125506304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 125505984 # Number of bytes read from this memory +system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961036 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1961031 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 104575632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 104575632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54299513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54299513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54299513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 104575632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 158875145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961036 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 104607997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961031 # Number of read requests accepted system.physmem.writeReqs 1018242 # Number of write requests accepted -system.physmem.readBursts 1961036 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1961031 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125423936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82368 # Total number of bytes read from write queue -system.physmem.bytesWritten 65165888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125506304 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 125423808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82176 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166208 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125505984 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1287 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1284 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118759 # Per bank write bursts -system.physmem.perBankRdBursts::1 114099 # Per bank write bursts -system.physmem.perBankRdBursts::2 116224 # Per bank write bursts -system.physmem.perBankRdBursts::3 117761 # Per bank write bursts -system.physmem.perBankRdBursts::4 117826 # Per bank write bursts -system.physmem.perBankRdBursts::5 117519 # Per bank write bursts -system.physmem.perBankRdBursts::6 119878 # Per bank write bursts -system.physmem.perBankRdBursts::7 124524 # Per bank write bursts -system.physmem.perBankRdBursts::8 126972 # Per bank write bursts -system.physmem.perBankRdBursts::9 130092 # Per bank write bursts -system.physmem.perBankRdBursts::10 128660 # Per bank write bursts -system.physmem.perBankRdBursts::11 130342 # Per bank write bursts +system.physmem.perBankRdBursts::0 118757 # Per bank write bursts +system.physmem.perBankRdBursts::1 114096 # Per bank write bursts +system.physmem.perBankRdBursts::2 116226 # Per bank write bursts +system.physmem.perBankRdBursts::3 117770 # Per bank write bursts +system.physmem.perBankRdBursts::4 117824 # Per bank write bursts +system.physmem.perBankRdBursts::5 117523 # Per bank write bursts +system.physmem.perBankRdBursts::6 119882 # Per bank write bursts +system.physmem.perBankRdBursts::7 124516 # Per bank write bursts +system.physmem.perBankRdBursts::8 126973 # Per bank write bursts +system.physmem.perBankRdBursts::9 130090 # Per bank write bursts +system.physmem.perBankRdBursts::10 128654 # Per bank write bursts +system.physmem.perBankRdBursts::11 130347 # Per bank write bursts system.physmem.perBankRdBursts::12 126055 # Per bank write bursts -system.physmem.perBankRdBursts::13 125250 # Per bank write bursts -system.physmem.perBankRdBursts::14 122599 # Per bank write bursts -system.physmem.perBankRdBursts::15 123189 # Per bank write bursts +system.physmem.perBankRdBursts::13 125249 # Per bank write bursts +system.physmem.perBankRdBursts::14 122591 # Per bank write bursts +system.physmem.perBankRdBursts::15 123194 # Per bank write bursts system.physmem.perBankWrBursts::0 61222 # Per bank write bursts -system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60565 # Per bank write bursts +system.physmem.perBankWrBursts::1 61485 # Per bank write bursts +system.physmem.perBankWrBursts::2 60564 # Per bank write bursts system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61662 # Per bank write bursts -system.physmem.perBankWrBursts::5 63103 # Per bank write bursts +system.physmem.perBankWrBursts::4 61658 # Per bank write bursts +system.physmem.perBankWrBursts::5 63101 # Per bank write bursts system.physmem.perBankWrBursts::6 64148 # Per bank write bursts -system.physmem.perBankWrBursts::7 65614 # Per bank write bursts -system.physmem.perBankWrBursts::8 65330 # Per bank write bursts -system.physmem.perBankWrBursts::9 65779 # Per bank write bursts -system.physmem.perBankWrBursts::10 65300 # Per bank write bursts -system.physmem.perBankWrBursts::11 65644 # Per bank write bursts -system.physmem.perBankWrBursts::12 64162 # Per bank write bursts -system.physmem.perBankWrBursts::13 64212 # Per bank write bursts -system.physmem.perBankWrBursts::14 64570 # Per bank write bursts -system.physmem.perBankWrBursts::15 64181 # Per bank write bursts +system.physmem.perBankWrBursts::7 65617 # Per bank write bursts +system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::9 65778 # Per bank write bursts +system.physmem.perBankWrBursts::10 65295 # Per bank write bursts +system.physmem.perBankWrBursts::11 65646 # Per bank write bursts +system.physmem.perBankWrBursts::12 64171 # Per bank write bursts +system.physmem.perBankWrBursts::13 64211 # Per bank write bursts +system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1200148547500 # Total gap between requests +system.physmem.totGap 1199774169500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961036 # Read request sizes (log2) +system.physmem.readPktSize::6 1961031 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1834284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125445 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,35 +140,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -189,128 +189,129 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1837714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.708116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.073776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.879385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1458610 79.37% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 262385 14.28% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49383 2.69% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20628 1.12% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12966 0.71% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7221 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5354 0.29% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4357 0.24% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16810 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1837714 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59460 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.957232 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.327917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59419 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1838370 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.671596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.054008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.842659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1459678 79.40% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 262161 14.26% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49287 2.68% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20645 1.12% 97.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12893 0.70% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7143 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5357 0.29% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4451 0.24% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16755 0.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1838370 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59429 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.975652 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.968947 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59388 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59460 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59460 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.124403 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.088362 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.116973 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27861 46.86% 46.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1344 2.26% 49.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 25901 43.56% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3838 6.45% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 438 0.74% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 56 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59460 # Writes before turning the bus around for reads -system.physmem.totQLat 37078229500 # Total ticks spent queuing -system.physmem.totMemAccLat 73823523250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18919.89 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59429 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.133420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.097680 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.110939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27565 46.38% 46.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1269 2.14% 48.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26249 44.17% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3908 6.58% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 362 0.61% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 56 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59429 # Writes before turning the bus around for reads +system.physmem.totQLat 36751953000 # Total ticks spent queuing +system.physmem.totMemAccLat 73497209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798735000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18753.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37669.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 104.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 104.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37503.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 104.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 104.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.24 # Data bus utilization in percentage system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 726316 # Number of row buffer hits during reads -system.physmem.writeRowHits 413927 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.65 # Row buffer hit rate for writes -system.physmem.avgGap 402832.01 # Average gap between requests -system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 393584177750 # Time in different power states -system.physmem.memoryStateTime::REF 40075360000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 766482185250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6742219680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7150867920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3678790500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3901763250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7383355200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7901907000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3233772720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3364273440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 78387404160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 78387404160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 410122352430 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 423496116225 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 360328576500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 348597204750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 869876471190 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 872799536745 # Total energy per rank (pJ) -system.physmem.averagePower::0 724.811465 # Core power per rank (mW) -system.physmem.averagePower::1 727.247065 # Core power per rank (mW) -system.cpu.branchPred.lookups 246247636 # Number of BP lookups -system.cpu.branchPred.condPredicted 186450048 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15699340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168260719 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165258168 # Number of BTB hits +system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing +system.physmem.readRowHits 726418 # Number of row buffer hits during reads +system.physmem.writeRowHits 413172 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.58 # Row buffer hit rate for writes +system.physmem.avgGap 402707.03 # Average gap between requests +system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6745500720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3680580750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383386400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409753789290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 360427621500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 869587605780 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.796496 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 596865139750 # Time in different power states +system.physmem_0.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 562842538250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7152516000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3902662500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7901961600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364241040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 422708761260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 349063611000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 872456746680 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.187909 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 577877428500 # Time in different power states +system.physmem_1.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 581827655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 246222594 # Number of BP lookups +system.cpu.branchPred.condPredicted 186441188 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15682162 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167748253 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165224895 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.215537 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18428845 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104881 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.495747 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18427327 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104678 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452532318 # DTB read hits -system.cpu.dtb.read_misses 4979776 # DTB read misses +system.cpu.dtb.read_hits 452533853 # DTB read hits +system.cpu.dtb.read_misses 4979561 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457512094 # DTB read accesses -system.cpu.dtb.write_hits 161379130 # DTB write hits -system.cpu.dtb.write_misses 1710165 # DTB write misses +system.cpu.dtb.read_accesses 457513414 # DTB read accesses +system.cpu.dtb.write_hits 161377742 # DTB write hits +system.cpu.dtb.write_misses 1710117 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163089295 # DTB write accesses -system.cpu.dtb.data_hits 613911448 # DTB hits -system.cpu.dtb.data_misses 6689941 # DTB misses +system.cpu.dtb.write_accesses 163087859 # DTB write accesses +system.cpu.dtb.data_hits 613911595 # DTB hits +system.cpu.dtb.data_misses 6689678 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601389 # DTB accesses -system.cpu.itb.fetch_hits 598579568 # ITB hits +system.cpu.dtb.data_accesses 620601273 # DTB accesses +system.cpu.itb.fetch_hits 598493672 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598579587 # ITB accesses +system.cpu.itb.fetch_accesses 598493691 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,66 +325,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2400297316 # number of cpu cycles simulated +system.cpu.numCycles 2399548560 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52410829 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52395177 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.314239 # CPI: cycles per instruction -system.cpu.ipc 0.760897 # IPC: instructions per cycle -system.cpu.tickCycles 2077436531 # Number of cycles that the object actually ticked -system.cpu.idleCycles 322860785 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121980 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.680046 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601827690 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126076 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945943 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16791074000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.680046 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996260 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996260 # Average percentage of cache occupancy +system.cpu.cpi 1.313829 # CPI: cycles per instruction +system.cpu.ipc 0.761134 # IPC: instructions per cycle +system.cpu.tickCycles 2077217503 # Number of cycles that the object actually ticked +system.cpu.idleCycles 322331057 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121997 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.675710 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601828569 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.675710 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.996259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1617 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1613 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2310 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231838176 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231838176 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 443337984 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443337984 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158489706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158489706 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 601827690 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601827690 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 601827690 # number of overall hits -system.cpu.dcache.overall_hits::total 601827690 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7289564 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289564 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238796 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238796 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9528360 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9528360 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9528360 # number of overall misses -system.cpu.dcache.overall_misses::total 9528360 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178244544500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 178244544500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101115441000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101115441000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 279359985500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 279359985500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 279359985500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 279359985500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 450627548 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450627548 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 443338834 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158489735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 601828569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 601828569 # number of overall hits +system.cpu.dcache.overall_hits::total 601828569 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7289569 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9528336 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9528336 # number of overall misses +system.cpu.dcache.overall_misses::total 9528336 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 278998136500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 611356050 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 611356050 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356050 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 611356905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 611356905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013929 # miss rate for WriteReq accesses @@ -392,14 +393,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.015586 system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.015586 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24452.017226 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24452.017226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45165.098115 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45165.098115 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29318.789960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29318.789960 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24423.897490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45095.559520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,32 +409,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700593 # number of writebacks -system.cpu.dcache.writebacks::total 3700593 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50804 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50804 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351480 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 351480 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 402284 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 402284 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 402284 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 402284 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238760 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238760 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126076 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126076 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126076 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126076 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162288114750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162288114750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76072677250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76072677250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238360792000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 238360792000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238360792000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 238360792000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks +system.cpu.dcache.writebacks::total 3700624 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50811 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351432 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 402243 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 402243 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238758 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126093 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162083992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75948494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238032486500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238032486500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses @@ -442,66 +443,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014928 system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22419.325237 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22419.325237 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40307.334463 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40307.334463 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26118.650776 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26118.650776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26118.650776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26118.650776 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22391.132844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40241.130748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 751.335570 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 598578610 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 624821.096033 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 752.081160 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 598492713 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 959 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 624079.992701 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 751.335570 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366863 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366863 # 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number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6058136 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700624 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700624 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107885 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107885 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7166021 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7166021 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7166021 # number of overall hits +system.cpu.l2cache.overall_hits::total 7166021 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 779450 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 779450 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1961031 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1961031 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1961031 # number of overall misses +system.cpu.l2cache.overall_misses::total 1961031 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94315348250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94315348250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 62933867000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 62933867000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 157249215250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 157249215250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 157249215250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 157249215250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239717 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7239717 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3700624 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700624 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887335 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1887335 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9127052 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9127052 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9127052 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9127052 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214859 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214859 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214859 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214859 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80187.011450 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -617,91 +618,91 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks system.cpu.l2cache.writebacks::total 1018242 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1181592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779444 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 779444 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961036 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961036 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79676806000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79676806000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53247448000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53247448000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132924254000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 132924254000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132924254000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 132924254000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412991 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67431.741244 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67431.741244 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68314.655062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68314.655062 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67782.668957 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961031 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700593 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887316 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954661 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820906816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820968128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887335 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952810 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820909888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820971264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827676 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827627 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827676 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114406500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827676 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114462000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1631750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1635250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14010883500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14011262000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181592 # Transaction distribution -system.membus.trans_dist::ReadResp 1181592 # Transaction distribution +system.membus.trans_dist::ReadReq 1181581 # Transaction distribution +system.membus.trans_dist::ReadResp 1181581 # Transaction distribution system.membus.trans_dist::Writeback 1018242 # Transaction distribution -system.membus.trans_dist::ReadExReq 779444 # Transaction distribution -system.membus.trans_dist::ReadExResp 779444 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940314 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940314 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673792 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 779450 # Transaction distribution +system.membus.trans_dist::ReadExResp 779450 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940304 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190673472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979278 # Request fanout histogram +system.membus.snoop_fanout::samples 2979273 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979278 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979273 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979278 # Request fanout histogram -system.membus.reqLayer0.occupancy 11833253000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2979273 # Request fanout histogram +system.membus.reqLayer0.occupancy 11833185000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18446066000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18446289250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 704344325..9b6ff7bd3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.662267 # Number of seconds simulated -sim_ticks 662266942000 # Number of ticks simulated -final_tick 662266942000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.662030 # Number of seconds simulated +sim_ticks 662030381000 # Number of ticks simulated +final_tick 662030381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189043 # Simulator instruction rate (inst/s) -host_op_rate 189043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72116099 # Simulator tick rate (ticks/s) -host_mem_usage 239436 # Number of bytes of host memory used -host_seconds 9183.34 # Real time elapsed on the host +host_inst_rate 173779 # Simulator instruction rate (inst/s) +host_op_rate 173779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66269486 # Simulator tick rate (ticks/s) +host_mem_usage 296312 # Number of bytes of host memory used +host_seconds 9989.97 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 62272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125973696 # Number of bytes read from this memory -system.physmem.bytes_read::total 126035968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65304064 # Number of bytes written to this memory -system.physmem.bytes_written::total 65304064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968339 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020376 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020376 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190215890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190309919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94029 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94029 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98606861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98606861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98606861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190215890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 288916779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969312 # Number of read requests accepted -system.physmem.writeReqs 1020376 # Number of write requests accepted -system.physmem.readBursts 1969312 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020376 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125955072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80896 # Total number of bytes read from write queue -system.physmem.bytesWritten 65302080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126035968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65304064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1264 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125964224 # Number of bytes read from this memory +system.physmem.bytes_read::total 126026048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65301568 # Number of bytes written to this memory +system.physmem.bytes_written::total 65301568 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968191 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020337 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020337 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 190269552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 190362937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98638325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98638325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98638325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 190269552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 289001263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969157 # Number of read requests accepted +system.physmem.writeReqs 1020337 # Number of write requests accepted +system.physmem.readBursts 1969157 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020337 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125945216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80832 # Total number of bytes read from write queue +system.physmem.bytesWritten 65299584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126026048 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65301568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1263 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119151 # Per bank write bursts -system.physmem.perBankRdBursts::1 114520 # Per bank write bursts -system.physmem.perBankRdBursts::2 116626 # Per bank write bursts -system.physmem.perBankRdBursts::3 118169 # Per bank write bursts -system.physmem.perBankRdBursts::4 118249 # Per bank write bursts -system.physmem.perBankRdBursts::5 117904 # Per bank write bursts -system.physmem.perBankRdBursts::6 120341 # Per bank write bursts -system.physmem.perBankRdBursts::7 125053 # Per bank write bursts -system.physmem.perBankRdBursts::8 127649 # Per bank write bursts -system.physmem.perBankRdBursts::9 130602 # Per bank write bursts -system.physmem.perBankRdBursts::10 129289 # Per bank write bursts -system.physmem.perBankRdBursts::11 130962 # Per bank write bursts -system.physmem.perBankRdBursts::12 126769 # Per bank write bursts -system.physmem.perBankRdBursts::13 125905 # Per bank write bursts -system.physmem.perBankRdBursts::14 123070 # Per bank write bursts -system.physmem.perBankRdBursts::15 123789 # Per bank write bursts -system.physmem.perBankWrBursts::0 61320 # Per bank write bursts +system.physmem.perBankRdBursts::0 119107 # Per bank write bursts +system.physmem.perBankRdBursts::1 114513 # Per bank write bursts +system.physmem.perBankRdBursts::2 116588 # Per bank write bursts +system.physmem.perBankRdBursts::3 118130 # Per bank write bursts +system.physmem.perBankRdBursts::4 118281 # Per bank write bursts +system.physmem.perBankRdBursts::5 117894 # Per bank write bursts +system.physmem.perBankRdBursts::6 120372 # Per bank write bursts +system.physmem.perBankRdBursts::7 125027 # Per bank write bursts +system.physmem.perBankRdBursts::8 127642 # Per bank write bursts +system.physmem.perBankRdBursts::9 130604 # Per bank write bursts +system.physmem.perBankRdBursts::10 129295 # Per bank write bursts +system.physmem.perBankRdBursts::11 130929 # Per bank write bursts +system.physmem.perBankRdBursts::12 126770 # Per bank write bursts +system.physmem.perBankRdBursts::13 125862 # Per bank write bursts +system.physmem.perBankRdBursts::14 123081 # Per bank write bursts +system.physmem.perBankRdBursts::15 123799 # Per bank write bursts +system.physmem.perBankWrBursts::0 61289 # Per bank write bursts system.physmem.perBankWrBursts::1 61597 # Per bank write bursts -system.physmem.perBankWrBursts::2 60678 # Per bank write bursts -system.physmem.perBankWrBursts::3 61357 # Per bank write bursts -system.physmem.perBankWrBursts::4 61793 # Per bank write bursts -system.physmem.perBankWrBursts::5 63216 # Per bank write bursts -system.physmem.perBankWrBursts::6 64269 # Per bank write bursts -system.physmem.perBankWrBursts::7 65744 # Per bank write bursts -system.physmem.perBankWrBursts::8 65524 # Per bank write bursts -system.physmem.perBankWrBursts::9 65904 # Per bank write bursts -system.physmem.perBankWrBursts::10 65459 # Per bank write bursts -system.physmem.perBankWrBursts::11 65777 # Per bank write bursts -system.physmem.perBankWrBursts::12 64349 # Per bank write bursts -system.physmem.perBankWrBursts::13 64362 # Per bank write bursts -system.physmem.perBankWrBursts::14 64665 # Per bank write bursts -system.physmem.perBankWrBursts::15 64331 # Per bank write bursts +system.physmem.perBankWrBursts::2 60658 # Per bank write bursts +system.physmem.perBankWrBursts::3 61339 # Per bank write bursts +system.physmem.perBankWrBursts::4 61821 # Per bank write bursts +system.physmem.perBankWrBursts::5 63209 # Per bank write bursts +system.physmem.perBankWrBursts::6 64289 # Per bank write bursts +system.physmem.perBankWrBursts::7 65739 # Per bank write bursts +system.physmem.perBankWrBursts::8 65503 # Per bank write bursts +system.physmem.perBankWrBursts::9 65920 # Per bank write bursts +system.physmem.perBankWrBursts::10 65439 # Per bank write bursts +system.physmem.perBankWrBursts::11 65771 # Per bank write bursts +system.physmem.perBankWrBursts::12 64363 # Per bank write bursts +system.physmem.perBankWrBursts::13 64352 # Per bank write bursts +system.physmem.perBankWrBursts::14 64685 # Per bank write bursts +system.physmem.perBankWrBursts::15 64332 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 662266852500 # Total gap between requests +system.physmem.totGap 662030291500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969312 # Read request sizes (log2) +system.physmem.readPktSize::6 1969157 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020376 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020337 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 248303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 76115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,38 +144,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 63086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -193,151 +193,142 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1775882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.694867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.878503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.793796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1380775 77.75% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271356 15.28% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53913 3.04% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21326 1.20% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12854 0.72% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6480 0.36% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5132 0.29% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3787 0.21% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20259 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1775882 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59943 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.788466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.189780 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59903 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 15 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1776224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.667141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.863857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.742577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1381396 77.77% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271071 15.26% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53950 3.04% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21226 1.20% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12955 0.73% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6597 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5003 0.28% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3759 0.21% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20267 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1776224 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59925 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.795728 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.660245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59887 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59943 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59943 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.021921 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.980571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.225631 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 33661 56.16% 56.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 25267 42.15% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 929 1.55% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 52 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59943 # Writes before turning the bus around for reads -system.physmem.totQLat 41251747750 # Total ticks spent queuing -system.physmem.totMemAccLat 78152647750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9840240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20960.74 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59925 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.026383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.985304 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.212732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31950 53.32% 53.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1595 2.66% 55.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20819 34.74% 90.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4577 7.64% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 750 1.25% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 154 0.26% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 27 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59925 # Writes before turning the bus around for reads +system.physmem.totQLat 40790268000 # Total ticks spent queuing +system.physmem.totMemAccLat 77688280500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9839470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20727.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39710.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39477.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 190.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 98.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 190.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 98.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.26 # Data bus utilization in percentage system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 795732 # Number of row buffer hits during reads -system.physmem.writeRowHits 416769 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.84 # Row buffer hit rate for writes -system.physmem.avgGap 221517.05 # Average gap between requests -system.physmem.pageHitRate 40.57 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 126335534000 # Time in different power states -system.physmem.memoryStateTime::REF 22114300000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 513810229000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6510407400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 6915200040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3552305625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3773174625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7409890800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7939939800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3239831520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3372004080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 43255570800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 43255570800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 299907401805 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 307252084365 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 134279187750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 127836483750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 498154595700 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 500344457460 # Total energy per rank (pJ) -system.physmem.averagePower::0 752.204234 # Core power per rank (mW) -system.physmem.averagePower::1 755.510885 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1197969 # Transaction distribution -system.membus.trans_dist::ReadResp 1197969 # Transaction distribution -system.membus.trans_dist::Writeback 1020376 # Transaction distribution -system.membus.trans_dist::ReadExReq 771343 # Transaction distribution -system.membus.trans_dist::ReadExResp 771343 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959000 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4959000 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191340032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191340032 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2989688 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2989688 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2989688 # Request fanout histogram -system.membus.reqLayer0.occupancy 11823557000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18423875500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 410506798 # Number of BP lookups -system.cpu.branchPred.condPredicted 318826270 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16270103 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 283363020 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279346814 # Number of BTB hits +system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing +system.physmem.readRowHits 795786 # Number of row buffer hits during reads +system.physmem.writeRowHits 416180 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.79 # Row buffer hit rate for writes +system.physmem.avgGap 221452.29 # Average gap between requests +system.physmem.pageHitRate 40.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6511261680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3552771750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7409259000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3239617680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 299928124440 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134120853750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 498002202300 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.239455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 221171423750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 418748256250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6916946400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3774127500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7939518600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3371965200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 306633623535 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128238837000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 500115332235 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.431368 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 211341940750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 428577885750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 410531758 # Number of BP lookups +system.cpu.branchPred.condPredicted 318847451 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16269165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 283137932 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279377578 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.582664 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26372853 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.671900 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26373623 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646169518 # DTB read hits -system.cpu.dtb.read_misses 12159492 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 658329010 # DTB read accesses -system.cpu.dtb.write_hits 218199205 # DTB write hits -system.cpu.dtb.write_misses 7515385 # DTB write misses +system.cpu.dtb.read_hits 646133385 # DTB read hits +system.cpu.dtb.read_misses 12154937 # DTB read misses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_accesses 658288322 # DTB read accesses +system.cpu.dtb.write_hits 218173916 # DTB write hits +system.cpu.dtb.write_misses 7514058 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225714590 # DTB write accesses -system.cpu.dtb.data_hits 864368723 # DTB hits -system.cpu.dtb.data_misses 19674877 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 884043600 # DTB accesses -system.cpu.itb.fetch_hits 422435766 # ITB hits -system.cpu.itb.fetch_misses 46 # ITB misses +system.cpu.dtb.write_accesses 225687974 # DTB write accesses +system.cpu.dtb.data_hits 864307301 # DTB hits +system.cpu.dtb.data_misses 19668995 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 883976296 # DTB accesses +system.cpu.itb.fetch_hits 422458110 # ITB hits +system.cpu.itb.fetch_misses 45 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422435812 # ITB accesses +system.cpu.itb.fetch_accesses 422458155 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,98 +342,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1324533885 # number of cpu cycles simulated +system.cpu.numCycles 1324060763 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433728129 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419447982 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410506798 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305719667 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 867740174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45999556 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1859 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 122 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422435766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8419815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1324470151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.157662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433748906 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3419441963 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410531758 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305751201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 867248304 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45995858 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1804 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422458110 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8422260 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1323997070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582666 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.157790 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 697483370 52.66% 52.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48005474 3.62% 56.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24395138 1.84% 58.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45249876 3.42% 61.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142980828 10.80% 72.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66219617 5.00% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43796288 3.31% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29613001 2.24% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226726559 17.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 696991073 52.64% 52.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48002120 3.63% 56.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24407254 1.84% 58.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45263157 3.42% 61.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142993214 10.80% 72.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66222276 5.00% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43788088 3.31% 80.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29616004 2.24% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226713884 17.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1324470151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309925 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.581624 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355594570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 385179518 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525809516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34887563 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22998984 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62292881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264034617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2122 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22998984 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373946851 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 205483814 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7143 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538725666 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183307693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181027912 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1764061 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19006533 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140449897 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27939508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377346604 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126580900 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126409923 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 170976 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1323997070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310055 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.582542 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355597650 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 384696746 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525812607 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34892959 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22997108 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62293389 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 869 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264034948 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2192 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22997108 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373957968 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 205165673 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7731 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538730067 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183138523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181033284 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1755579 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18983042 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 140285341 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27927823 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377354751 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4126620289 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4126448707 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 171581 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001143641 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 182 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99171579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719206222 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272877842 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90853191 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58764648 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889718435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624030011 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1568714 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139278450 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505521247 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 134 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1324470151 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151140 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001151788 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 192 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 191 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99207749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719206023 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272877739 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90880933 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59162115 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889782486 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 178 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624016708 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1570062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1139342915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 505618557 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 149 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1323997070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981890 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.151111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 520285766 39.28% 39.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169352294 12.79% 52.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158263377 11.95% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149147598 11.26% 75.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126214674 9.53% 84.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84460771 6.38% 91.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68224303 5.15% 96.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33971144 2.56% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14550224 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 519747645 39.26% 39.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169377682 12.79% 52.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158338012 11.96% 64.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149173722 11.27% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126185648 9.53% 84.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84437665 6.38% 91.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68199937 5.15% 96.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33982775 2.57% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14553984 1.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1324470151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1323997070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13169928 35.70% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13171575 35.70% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available @@ -471,118 +462,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19111172 51.81% 87.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4608428 12.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19111155 51.80% 87.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4612971 12.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719281995 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719329788 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 125 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896550 0.03% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672977290 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230873835 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 895316 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 672939161 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230852080 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624030011 # Type of FU issued -system.cpu.iq.rate 1.981097 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36889528 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6609007948 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4027844088 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521909296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1980467 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1299263 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 893137 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659936163 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 983376 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69546745 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624016708 # Type of FU issued +system.cpu.iq.rate 1.981795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36895701 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014061 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6608517036 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4027973051 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2521923586 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1979213 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1297888 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 892539 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2659929620 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 982789 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69543206 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274610559 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379781 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 148802 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112149340 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274610360 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379362 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 147727 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112149237 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6024507 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6023017 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22998984 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147954834 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18526434 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3040938881 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6690511 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719206222 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272877842 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 163 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 822212 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17973283 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 148802 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10902941 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8845995 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19748936 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578346915 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658329015 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45683096 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22997108 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 147758887 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18474565 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3040988458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6691344 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719206023 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272877739 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 178 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 822290 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17921565 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 147727 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10901488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8843129 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19744617 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578330269 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658288327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45686439 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151220283 # number of nop insts executed -system.cpu.iew.exec_refs 884043668 # number of memory reference insts executed -system.cpu.iew.exec_branches 315967801 # Number of branches executed -system.cpu.iew.exec_stores 225714653 # Number of stores executed -system.cpu.iew.exec_rate 1.946607 # Inst execution rate -system.cpu.iew.wb_sent 2552803336 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522802433 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489230488 # num instructions producing a value -system.cpu.iew.wb_consumers 1920481156 # num instructions consuming a value +system.cpu.iew.exec_nop 151205794 # number of nop insts executed +system.cpu.iew.exec_refs 883976375 # number of memory reference insts executed +system.cpu.iew.exec_branches 315983093 # Number of branches executed +system.cpu.iew.exec_stores 225688048 # Number of stores executed +system.cpu.iew.exec_rate 1.947290 # Inst execution rate +system.cpu.iew.wb_sent 2552817971 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2522816125 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489246506 # num instructions producing a value +system.cpu.iew.wb_consumers 1920479792 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904672 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775447 # average fanout of values written-back +system.cpu.iew.wb_rate 1.905363 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775455 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005079964 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005136223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16269309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1185591559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.534913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558094 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16268344 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1185116972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.535528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.558449 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 696399330 58.74% 58.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159901902 13.49% 72.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79790439 6.73% 78.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52118707 4.40% 83.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28427889 2.40% 85.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19400301 1.64% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20045609 1.69% 89.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23104546 1.95% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106402836 8.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 695949152 58.72% 58.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159874809 13.49% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79784402 6.73% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52116706 4.40% 83.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28440614 2.40% 85.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19407125 1.64% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20027045 1.69% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23110908 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106406211 8.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1185591559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1185116972 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,233 +619,339 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106402836 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106406211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3818269613 # The number of ROB reads -system.cpu.rob.rob_writes 5788733936 # The number of ROB writes -system.cpu.timesIdled 729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3817847910 # The number of ROB reads +system.cpu.rob.rob_writes 5788846951 # The number of ROB writes +system.cpu.timesIdled 724 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 63693 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762961 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762961 # CPI: Total CPI of All Threads -system.cpu.ipc 1.310683 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.310683 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467602221 # number of integer regfile reads -system.cpu.int_regfile_writes 2022271322 # number of integer regfile writes -system.cpu.fp_regfile_reads 45596 # number of floating regfile reads -system.cpu.fp_regfile_writes 565 # number of floating regfile writes +system.cpu.cpi 0.762689 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762689 # CPI: Total CPI of All Threads +system.cpu.ipc 1.311151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.311151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3467581476 # number of integer regfile reads +system.cpu.int_regfile_writes 2022302956 # number of integer regfile writes +system.cpu.fp_regfile_reads 46080 # number of floating regfile reads +system.cpu.fp_regfile_writes 592 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 7335000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7335000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879134 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879134 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1946 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22171094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829183168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 829245440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12957100 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12957100 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12957100 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10221444363 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1621500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14117208750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 9209012 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.412521 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713854428 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9213108 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.482477 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.412521 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 751 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2935 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1472845170 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472845170 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558341279 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558341279 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155513145 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155513145 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713854424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713854424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713854424 # number of overall hits +system.cpu.dcache.overall_hits::total 713854424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12746245 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12746245 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5215357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5215357 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 17961602 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17961602 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17961602 # number of overall misses +system.cpu.dcache.overall_misses::total 17961602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 384451562750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 384451562750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289305166008 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289305166008 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 673756728758 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 673756728758 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 673756728758 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 673756728758 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731816026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731816026 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731816026 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731816026 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024544 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024544 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024544 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024544 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30161.946734 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30161.946734 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55471.785730 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55471.785730 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37510.948564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37510.948564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14120110 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8634302 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1055091 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67341 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.382836 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.217609 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3742780 # number of writebacks +system.cpu.dcache.writebacks::total 3742780 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412238 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5412238 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3336257 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3336257 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8748495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8748495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8748495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8748495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334007 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334007 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9213107 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9213107 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9213107 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9213107 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168659488250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168659488250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77208966781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77208966781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245868455031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245868455031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245868455031 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245868455031 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22996.908545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22996.908545 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41088.269268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41088.269268 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 772.533395 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422434249 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 973 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 434156.473792 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 770.158211 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422456585 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 437325.657350 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 772.533395 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 972 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844872503 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844872503 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422434249 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422434249 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422434249 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422434249 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422434249 # number of overall hits -system.cpu.icache.overall_hits::total 422434249 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1516 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1516 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1516 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1516 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1516 # number of overall misses -system.cpu.icache.overall_misses::total 1516 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 104441749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 104441749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 104441749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 104441749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 104441749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 104441749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422435765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422435765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422435765 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422435765 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422435765 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422435765 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 770.158211 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376054 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376054 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 965 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82761.808623 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73771.839671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82844.854468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82840.371662 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73771.839671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82844.854468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82840.371662 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.213629 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.213712 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73672.101449 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82621.398524 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82614.181535 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82599.592755 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82599.592755 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82608.467353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82608.467353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -863,188 +960,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1020376 # number of writebacks -system.cpu.l2cache.writebacks::total 1020376 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196996 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1197969 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 771343 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 973 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54083955498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58998750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137979730498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138038729248 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58998750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137979730498 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138038729248 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163211 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163322 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410478 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410478 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410452 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213644 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.213727 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.213712 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61182.939363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70337.426886 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213712 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61075.310559 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70093.929761 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70086.656869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70121.790747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70121.790747 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9209065 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.415581 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713883338 # 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number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12749578 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5214360 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5214360 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17963938 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17963938 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17963938 # number of overall misses -system.cpu.dcache.overall_misses::total 17963938 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 385716453000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 385716453000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289481531698 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289481531698 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 675197984698 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 675197984698 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 675197984698 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 675197984698 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571118770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571118770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024546 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024546 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024546 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024546 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30253.272148 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30253.272148 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55516.215163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55516.215163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37586.301216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37586.301216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14206702 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8627771 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1055420 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67280 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.460709 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.236787 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742826 # number of writebacks -system.cpu.dcache.writebacks::total 3742826 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5415535 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5415535 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335243 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3335243 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8750778 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8750778 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8750778 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8750778 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334043 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334043 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879117 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879117 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213160 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9213160 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9213160 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9213160 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168998137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168998137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77338215218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77338215218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 246336352218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 246336352218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 246336352218 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 246336352218 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23042.970569 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23042.970569 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41156.679024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41156.679024 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7334962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7334962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742780 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879112 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879112 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22170928 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829176832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829238656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12957003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12957003 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12957003 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221354853 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1610750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14117356000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1197871 # Transaction distribution +system.membus.trans_dist::ReadResp 1197871 # Transaction distribution +system.membus.trans_dist::Writeback 1020337 # Transaction distribution +system.membus.trans_dist::ReadExReq 771286 # Transaction distribution +system.membus.trans_dist::ReadExResp 771286 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4958651 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2989494 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989494 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2989494 # Request fanout histogram +system.membus.reqLayer0.occupancy 11823428000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 18423304250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index b905eb22a..1d6a1c5a9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.108945 # Number of seconds simulated -sim_ticks 1108944740000 # Number of ticks simulated -final_tick 1108944740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.108725 # Number of seconds simulated +sim_ticks 1108725388000 # Number of ticks simulated +final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239014 # Simulator instruction rate (inst/s) -host_op_rate 257501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171603826 # Simulator tick rate (ticks/s) -host_mem_usage 253696 # Number of bytes of host memory used -host_seconds 6462.24 # Real time elapsed on the host +host_inst_rate 243193 # Simulator instruction rate (inst/s) +host_op_rate 262004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174570169 # Simulator tick rate (ticks/s) +host_mem_usage 311428 # Number of bytes of host memory used +host_seconds 6351.17 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131625408 # Number of bytes read from this memory -system.physmem.bytes_read::total 131625408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 131558336 # Number of bytes read from this memory +system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66989632 # Number of bytes written to this memory -system.physmem.bytes_written::total 66989632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2056647 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2056647 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046713 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046713 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 118694289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 118694289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60408449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60408449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60408449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 118694289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 179102739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2056647 # Number of read requests accepted -system.physmem.writeReqs 1046713 # Number of write requests accepted -system.physmem.readBursts 2056647 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046713 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131542016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83392 # Total number of bytes read from write queue -system.physmem.bytesWritten 66988032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131625408 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66989632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1303 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory +system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2055599 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 118657277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055599 # Number of read requests accepted +system.physmem.writeReqs 1046417 # Number of write requests accepted +system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue +system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128036 # Per bank write bursts -system.physmem.perBankRdBursts::1 125234 # Per bank write bursts -system.physmem.perBankRdBursts::2 122300 # Per bank write bursts -system.physmem.perBankRdBursts::3 124230 # Per bank write bursts -system.physmem.perBankRdBursts::4 123415 # Per bank write bursts -system.physmem.perBankRdBursts::5 123345 # Per bank write bursts -system.physmem.perBankRdBursts::6 123964 # Per bank write bursts -system.physmem.perBankRdBursts::7 124409 # Per bank write bursts -system.physmem.perBankRdBursts::8 131872 # Per bank write bursts -system.physmem.perBankRdBursts::9 134140 # Per bank write bursts -system.physmem.perBankRdBursts::10 132473 # Per bank write bursts -system.physmem.perBankRdBursts::11 133756 # Per bank write bursts -system.physmem.perBankRdBursts::12 133901 # Per bank write bursts -system.physmem.perBankRdBursts::13 134102 # Per bank write bursts -system.physmem.perBankRdBursts::14 129958 # Per bank write bursts -system.physmem.perBankRdBursts::15 130209 # Per bank write bursts -system.physmem.perBankWrBursts::0 65849 # Per bank write bursts -system.physmem.perBankWrBursts::1 64131 # Per bank write bursts -system.physmem.perBankWrBursts::2 62381 # Per bank write bursts -system.physmem.perBankWrBursts::3 62840 # Per bank write bursts -system.physmem.perBankWrBursts::4 62871 # Per bank write bursts -system.physmem.perBankWrBursts::5 62990 # Per bank write bursts -system.physmem.perBankWrBursts::6 64312 # Per bank write bursts -system.physmem.perBankWrBursts::7 65310 # Per bank write bursts -system.physmem.perBankWrBursts::8 67027 # Per bank write bursts -system.physmem.perBankWrBursts::9 67624 # Per bank write bursts -system.physmem.perBankWrBursts::10 67292 # Per bank write bursts -system.physmem.perBankWrBursts::11 67645 # Per bank write bursts -system.physmem.perBankWrBursts::12 67063 # Per bank write bursts -system.physmem.perBankWrBursts::13 67560 # Per bank write bursts -system.physmem.perBankWrBursts::14 66200 # Per bank write bursts -system.physmem.perBankWrBursts::15 65593 # Per bank write bursts +system.physmem.perBankRdBursts::0 127971 # Per bank write bursts +system.physmem.perBankRdBursts::1 125115 # Per bank write bursts +system.physmem.perBankRdBursts::2 122192 # Per bank write bursts +system.physmem.perBankRdBursts::3 124223 # Per bank write bursts +system.physmem.perBankRdBursts::4 123351 # Per bank write bursts +system.physmem.perBankRdBursts::5 123340 # Per bank write bursts +system.physmem.perBankRdBursts::6 123758 # Per bank write bursts +system.physmem.perBankRdBursts::7 124120 # Per bank write bursts +system.physmem.perBankRdBursts::8 131994 # Per bank write bursts +system.physmem.perBankRdBursts::9 134060 # Per bank write bursts +system.physmem.perBankRdBursts::10 132574 # Per bank write bursts +system.physmem.perBankRdBursts::11 133683 # Per bank write bursts +system.physmem.perBankRdBursts::12 133864 # Per bank write bursts +system.physmem.perBankRdBursts::13 133891 # Per bank write bursts +system.physmem.perBankRdBursts::14 129793 # Per bank write bursts +system.physmem.perBankRdBursts::15 130326 # Per bank write bursts +system.physmem.perBankWrBursts::0 65785 # Per bank write bursts +system.physmem.perBankWrBursts::1 64106 # Per bank write bursts +system.physmem.perBankWrBursts::2 62369 # Per bank write bursts +system.physmem.perBankWrBursts::3 62872 # Per bank write bursts +system.physmem.perBankWrBursts::4 62855 # Per bank write bursts +system.physmem.perBankWrBursts::5 62943 # Per bank write bursts +system.physmem.perBankWrBursts::6 64256 # Per bank write bursts +system.physmem.perBankWrBursts::7 65177 # Per bank write bursts +system.physmem.perBankWrBursts::8 67064 # Per bank write bursts +system.physmem.perBankWrBursts::9 67603 # Per bank write bursts +system.physmem.perBankWrBursts::10 67361 # Per bank write bursts +system.physmem.perBankWrBursts::11 67637 # Per bank write bursts +system.physmem.perBankWrBursts::12 67067 # Per bank write bursts +system.physmem.perBankWrBursts::13 67487 # Per bank write bursts +system.physmem.perBankWrBursts::14 66154 # Per bank write bursts +system.physmem.perBankWrBursts::15 65656 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1108944651500 # Total gap between requests +system.physmem.totGap 1108725299500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2056647 # Read request sizes (log2) +system.physmem.readPktSize::6 2055599 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046713 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1923205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132121 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046417 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,28 +140,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -189,104 +189,114 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1918209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.496643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.775288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.095886 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1492147 77.79% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 306422 15.97% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52965 2.76% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21185 1.10% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13242 0.69% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7471 0.39% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5204 0.27% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3914 0.20% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15659 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1918209 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61025 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.632724 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.189303 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60982 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61025 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61025 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.151790 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.116821 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.097688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27581 45.20% 45.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1180 1.93% 47.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28172 46.16% 93.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3706 6.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 317 0.52% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 54 0.09% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61025 # Writes before turning the bus around for reads -system.physmem.totQLat 38537340500 # Total ticks spent queuing -system.physmem.totMemAccLat 77075040500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10276720000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18749.83 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads +system.physmem.totQLat 38268969000 # Total ticks spent queuing +system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37499.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 118.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 118.69 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.40 # Data bus utilization in percentage system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing -system.physmem.readRowHits 777039 # Number of row buffer hits during reads -system.physmem.writeRowHits 406774 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.86 # Row buffer hit rate for writes -system.physmem.avgGap 357336.77 # Average gap between requests +system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing +system.physmem.readRowHits 776845 # Number of row buffer hits during reads +system.physmem.writeRowHits 406412 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes +system.physmem.avgGap 357420.88 # Average gap between requests system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 313164826000 # Time in different power states -system.physmem.memoryStateTime::REF 37029980000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 758746776000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 7075638360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7426006560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3860715375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 4051888500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7760165400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 8271151200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3309232320 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3473305920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 72430640880 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 72430640880 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 416866648005 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 425333204280 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 299692308000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 292265504250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 810995348340 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 813251701590 # Total energy per rank (pJ) -system.physmem.averagePower::0 731.323936 # Core power per rank (mW) -system.physmem.averagePower::1 733.358627 # Core power per rank (mW) -system.cpu.branchPred.lookups 240152510 # Number of BP lookups -system.cpu.branchPred.condPredicted 186756179 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14598640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131763268 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122287171 # Number of BTB hits +system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.249224 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.347080 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 240158127 # Number of BP lookups +system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.808241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15660181 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -308,6 +318,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -329,6 +347,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -350,6 +376,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -372,90 +406,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2217889480 # number of cpu cycles simulated +system.cpu.numCycles 2217450776 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40077128 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435933 # CPI: cycles per instruction -system.cpu.ipc 0.696411 # IPC: instructions per cycle -system.cpu.tickCycles 1838736315 # Number of cycles that the object actually ticked -system.cpu.idleCycles 379153165 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9224311 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.608602 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624084220 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9228407 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.626430 # Average number of references to valid blocks. +system.cpu.cpi 1.435649 # CPI: cycles per instruction +system.cpu.ipc 0.696549 # IPC: instructions per cycle +system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked +system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9223724 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.608602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.606596 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1292 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2484 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276551305 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276551305 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 453737568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453737568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 170346530 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170346530 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 453740634 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 170346644 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 624084098 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624084098 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 624084098 # number of overall hits -system.cpu.dcache.overall_hits::total 624084098 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7337712 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7337712 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2239517 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2239517 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9577229 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9577229 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9577229 # number of overall misses -system.cpu.dcache.overall_misses::total 9577229 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183598363496 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183598363496 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101566510500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101566510500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 285164873996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 285164873996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 285164873996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 285164873996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 461075280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461075280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 624087278 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 624087278 # number of overall hits +system.cpu.dcache.overall_hits::total 624087278 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7337122 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2239403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9576525 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9576525 # number of overall misses +system.cpu.dcache.overall_misses::total 9576525 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183400270746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101399706750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 284799977496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 284799977496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 461077756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 633661327 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633661327 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633661327 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633661327 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 633663803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 633663803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015114 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015114 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015114 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015114 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25021.200545 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25021.200545 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45351.971206 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45351.971206 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29775.300768 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29775.300768 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24996.213876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45279.794101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -464,101 +498,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks -system.cpu.dcache.writebacks::total 3700618 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348609 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 348609 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 348822 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348822 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 348822 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348822 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7337499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7337499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890908 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890908 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9228407 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9228407 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9228407 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9228407 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168505826254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168505826254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77457723500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77457723500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245963549754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245963549754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245963549754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245963549754 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015914 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015914 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks +system.cpu.dcache.writebacks::total 3701129 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 221 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348484 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 348705 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9227820 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014564 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014564 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22965.022040 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22965.022040 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40963.242791 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40963.242791 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22940.075279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40891.286988 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.026879 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466133968 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 568456.058537 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.026879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322767 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322767 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 661.153981 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322829 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322829 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932270396 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932270396 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466133968 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466133968 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466133968 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466133968 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466133968 # number of overall hits -system.cpu.icache.overall_hits::total 466133968 # number of overall hits +system.cpu.icache.tags.tag_accesses 932342814 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932342814 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 466170177 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466170177 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466170177 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466170177 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466170177 # number of overall hits +system.cpu.icache.overall_hits::total 466170177 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # 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miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79808.657531 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80574.513558 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,60 +706,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046713 # number of writebacks -system.cpu.l2cache.writebacks::total 1046713 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks +system.cpu.l2cache.writebacks::total 1046417 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1256323 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1256323 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800324 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800324 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2056647 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2056647 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2056647 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2056647 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84521118250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84521118250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54527231750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54527231750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139048350000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 139048350000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139048350000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 139048350000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222841 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222841 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67276.582734 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67276.582734 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68131.446452 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68131.446452 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800096 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84332667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54391877500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138724544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138724544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67170.422532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67981.689072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7338319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7338319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22157432 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22159072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827457600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827510080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12929845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -734,41 +768,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12929845 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12929845 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10165540500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1391499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14187091746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1256323 # Transaction distribution -system.membus.trans_dist::ReadResp 1256323 # Transaction distribution -system.membus.trans_dist::Writeback 1046713 # Transaction distribution -system.membus.trans_dist::ReadExReq 800324 # Transaction distribution -system.membus.trans_dist::ReadExResp 800324 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5160007 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5160007 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198615040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198615040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255503 # Transaction distribution +system.membus.trans_dist::ReadResp 1255503 # Transaction distribution +system.membus.trans_dist::Writeback 1046417 # Transaction distribution +system.membus.trans_dist::ReadExReq 800096 # Transaction distribution +system.membus.trans_dist::ReadExResp 800096 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3103360 # Request fanout histogram +system.membus.snoop_fanout::samples 3102016 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3103360 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3103360 # Request fanout histogram -system.membus.reqLayer0.occupancy 12130659500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3102016 # Request fanout histogram +system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19439818500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index dd7b09a8e..2039a5a26 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.753004 # Number of seconds simulated -sim_ticks 753003557500 # Number of ticks simulated -final_tick 753003557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.756343 # Number of seconds simulated +sim_ticks 756342731500 # Number of ticks simulated +final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139146 # Simulator instruction rate (inst/s) -host_op_rate 149909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67836303 # Simulator tick rate (ticks/s) -host_mem_usage 311432 # Number of bytes of host memory used -host_seconds 11100.30 # Real time elapsed on the host +host_inst_rate 137786 # Simulator instruction rate (inst/s) +host_op_rate 148444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67471289 # Simulator tick rate (ticks/s) +host_mem_usage 311496 # Number of bytes of host memory used +host_seconds 11209.85 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 14592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 231381248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 95077696 # Number of bytes read from this memory -system.physmem.bytes_read::total 326473536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 107048704 # Number of bytes written to this memory -system.physmem.bytes_written::total 107048704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3615332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1485589 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5101149 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1672636 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1672636 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 307277762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 126264604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 433561744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 142162282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 142162282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 142162282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 307277762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 126264604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 575724026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5101149 # Number of read requests accepted -system.physmem.writeReqs 1672636 # Number of write requests accepted -system.physmem.readBursts 5101149 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1672636 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 326003456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 470080 # Total number of bytes read from write queue -system.physmem.bytesWritten 107046272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 326473536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 107048704 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7345 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory +system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory +system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4720345 # Number of read requests accepted +system.physmem.writeReqs 1638491 # Number of write requests accepted +system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue +system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 320458 # Per bank write bursts -system.physmem.perBankRdBursts::1 318552 # Per bank write bursts -system.physmem.perBankRdBursts::2 312159 # Per bank write bursts -system.physmem.perBankRdBursts::3 320321 # Per bank write bursts -system.physmem.perBankRdBursts::4 313091 # Per bank write bursts -system.physmem.perBankRdBursts::5 313451 # Per bank write bursts -system.physmem.perBankRdBursts::6 306429 # Per bank write bursts -system.physmem.perBankRdBursts::7 300886 # Per bank write bursts -system.physmem.perBankRdBursts::8 320656 # Per bank write bursts -system.physmem.perBankRdBursts::9 326914 # Per bank write bursts -system.physmem.perBankRdBursts::10 318873 # Per bank write bursts -system.physmem.perBankRdBursts::11 328947 # Per bank write bursts -system.physmem.perBankRdBursts::12 326980 # Per bank write bursts -system.physmem.perBankRdBursts::13 328236 # Per bank write bursts -system.physmem.perBankRdBursts::14 322345 # Per bank write bursts -system.physmem.perBankRdBursts::15 315506 # Per bank write bursts -system.physmem.perBankWrBursts::0 106372 # Per bank write bursts -system.physmem.perBankWrBursts::1 103970 # Per bank write bursts -system.physmem.perBankWrBursts::2 101390 # Per bank write bursts -system.physmem.perBankWrBursts::3 102163 # Per bank write bursts -system.physmem.perBankWrBursts::4 101308 # Per bank write bursts -system.physmem.perBankWrBursts::5 100856 # Per bank write bursts -system.physmem.perBankWrBursts::6 104858 # Per bank write bursts -system.physmem.perBankWrBursts::7 106447 # Per bank write bursts -system.physmem.perBankWrBursts::8 107624 # Per bank write bursts -system.physmem.perBankWrBursts::9 106732 # Per bank write bursts -system.physmem.perBankWrBursts::10 104273 # Per bank write bursts -system.physmem.perBankWrBursts::11 105282 # Per bank write bursts -system.physmem.perBankWrBursts::12 105198 # Per bank write bursts -system.physmem.perBankWrBursts::13 104874 # Per bank write bursts -system.physmem.perBankWrBursts::14 106564 # Per bank write bursts -system.physmem.perBankWrBursts::15 104687 # Per bank write bursts +system.physmem.perBankRdBursts::0 296862 # Per bank write bursts +system.physmem.perBankRdBursts::1 294626 # Per bank write bursts +system.physmem.perBankRdBursts::2 288270 # Per bank write bursts +system.physmem.perBankRdBursts::3 292812 # Per bank write bursts +system.physmem.perBankRdBursts::4 290199 # Per bank write bursts +system.physmem.perBankRdBursts::5 289793 # Per bank write bursts +system.physmem.perBankRdBursts::6 284872 # Per bank write bursts +system.physmem.perBankRdBursts::7 281493 # Per bank write bursts +system.physmem.perBankRdBursts::8 297311 # Per bank write bursts +system.physmem.perBankRdBursts::9 303290 # Per bank write bursts +system.physmem.perBankRdBursts::10 295469 # Per bank write bursts +system.physmem.perBankRdBursts::11 301855 # Per bank write bursts +system.physmem.perBankRdBursts::12 303298 # Per bank write bursts +system.physmem.perBankRdBursts::13 302373 # Per bank write bursts +system.physmem.perBankRdBursts::14 297652 # Per bank write bursts +system.physmem.perBankRdBursts::15 293020 # Per bank write bursts +system.physmem.perBankWrBursts::0 104131 # Per bank write bursts +system.physmem.perBankWrBursts::1 101826 # Per bank write bursts +system.physmem.perBankWrBursts::2 99098 # Per bank write bursts +system.physmem.perBankWrBursts::3 99979 # Per bank write bursts +system.physmem.perBankWrBursts::4 99438 # Per bank write bursts +system.physmem.perBankWrBursts::5 99115 # Per bank write bursts +system.physmem.perBankWrBursts::6 102674 # Per bank write bursts +system.physmem.perBankWrBursts::7 104427 # Per bank write bursts +system.physmem.perBankWrBursts::8 105209 # Per bank write bursts +system.physmem.perBankWrBursts::9 104570 # Per bank write bursts +system.physmem.perBankWrBursts::10 102342 # Per bank write bursts +system.physmem.perBankWrBursts::11 102683 # Per bank write bursts +system.physmem.perBankWrBursts::12 102787 # Per bank write bursts +system.physmem.perBankWrBursts::13 102808 # Per bank write bursts +system.physmem.perBankWrBursts::14 104630 # Per bank write bursts +system.physmem.perBankWrBursts::15 102728 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 753003515500 # Total gap between requests +system.physmem.totGap 756342591500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5101149 # Read request sizes (log2) +system.physmem.readPktSize::6 4720345 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1672636 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2761902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1096580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 406963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 307813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 214927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 130899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 69362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 43944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 6876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 4504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 473 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1638491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,38 +148,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 25442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 58935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 74795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 105264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 108420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 110279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 111519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 112924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 114921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 116959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 109523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 106852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 104984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 103460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -197,140 +197,132 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4344411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 99.679291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.657847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 113.406930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3407328 78.43% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 696147 16.02% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 107309 2.47% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 43326 1.00% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 33261 0.77% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16273 0.37% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9699 0.22% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6677 0.15% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24391 0.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4344411 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 100519 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 50.674768 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.618065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.194987 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 98006 97.50% 97.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1235 1.23% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 738 0.73% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 394 0.39% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 104 0.10% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 26 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 7 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3327 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 100519 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 100519 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.639620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.599991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.204272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73763 73.38% 73.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1810 1.80% 75.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17937 17.84% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4183 4.16% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1485 1.48% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 646 0.64% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 326 0.32% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 183 0.18% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 100 0.10% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 51 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 100519 # Writes before turning the bus around for reads -system.physmem.totQLat 147032532073 # Total ticks spent queuing -system.physmem.totMemAccLat 242541357073 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 25469020000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28864.98 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads +system.physmem.totQLat 132475907765 # Total ticks spent queuing +system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47614.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 432.94 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 142.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 433.56 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 142.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.49 # Data bus utilization in percentage -system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.11 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 2056015 # Number of row buffer hits during reads -system.physmem.writeRowHits 365966 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.88 # Row buffer hit rate for writes -system.physmem.avgGap 111164.37 # Average gap between requests -system.physmem.pageHitRate 35.79 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 77100737509 # Time in different power states -system.physmem.memoryStateTime::REF 25144340000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 650755672741 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 16285857840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 16557549120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 8886132750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 9034377000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19540895400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 20189722800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5361143760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5476960800 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 49182329040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 49182329040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 403433749845 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 404376910605 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 97911188250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 97083854250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 600601296885 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 601901703615 # Total energy per rank (pJ) -system.physmem.averagePower::0 797.610503 # Core power per rank (mW) -system.physmem.averagePower::1 799.337469 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4164250 # Transaction distribution -system.membus.trans_dist::ReadResp 4164249 # Transaction distribution -system.membus.trans_dist::Writeback 1672636 # Transaction distribution -system.membus.trans_dist::ReadExReq 936899 # Transaction distribution -system.membus.trans_dist::ReadExResp 936899 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11874933 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11874933 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 433522176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 433522176 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6773785 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6773785 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6773785 # Request fanout histogram -system.membus.reqLayer0.occupancy 21336071694 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 47387677526 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.3 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 286237274 # Number of BP lookups -system.cpu.branchPred.condPredicted 223376247 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157873028 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150326972 # Number of BTB hits +system.physmem.busUtil 4.20 # Data bus utilization in percentage +system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 1712938 # Number of row buffer hits during reads +system.physmem.writeRowHits 353078 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes +system.physmem.avgGap 118943.56 # Average gap between requests +system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.094387 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states +system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ) +system.physmem_1.averagePower 795.815775 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states +system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 286251205 # Number of BP lookups +system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.220174 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640209 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -352,6 +344,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -373,6 +373,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,6 +402,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -416,233 +432,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1506007116 # number of cpu cycles simulated +system.cpu.numCycles 1512685464 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13915908 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067206547 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286237274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166967181 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1477423210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29286859 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656844028 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 587 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1505982817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.470565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.223309 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 423738570 28.14% 28.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465347942 30.90% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101390896 6.73% 65.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515505409 34.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1505982817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.190064 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372641 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74738188 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 508470466 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849951241 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58180203 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642719 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42195522 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 748 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037029518 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52402529 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642719 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139800206 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 434773312 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14137 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837909741 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 78842702 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976226014 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26698193 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45123172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125355 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1314299 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18015097 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985707207 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127389229 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432660668 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310808262 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111604908 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542499825 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199292304 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26858708 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28865215 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947820848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 155 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857727691 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13537484 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 279225798 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 646033301 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1505982817 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.233565 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149736 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 553461726 36.75% 36.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325286672 21.60% 58.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378400557 25.13% 83.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219701727 14.59% 98.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29125951 1.93% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6184 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1505982817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166582994 41.01% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1992 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191579576 47.17% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 48024706 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138365513 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800977 0.04% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 26 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532245079 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186316069 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857727691 # Type of FU issued -system.cpu.iq.rate 1.233545 # Inst issue rate -system.cpu.iq.fu_busy_cnt 406189268 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218648 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5641164724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2227059400 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805827330 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263916833 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17868715 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued +system.cpu.iq.rate 1.228002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84193491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12979 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24445259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4569389 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5015263 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642719 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25280273 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1153411 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947821148 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542499825 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199292304 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158606 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 993784 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12979 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7710323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8723960 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16434283 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1828067374 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 517076026 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29660317 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 698832649 # number of memory reference insts executed -system.cpu.iew.exec_branches 229600081 # Number of branches executed -system.cpu.iew.exec_stores 181756623 # Number of stores executed -system.cpu.iew.exec_rate 1.213850 # Inst execution rate -system.cpu.iew.wb_sent 1808848691 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805827397 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169333238 # num instructions producing a value -system.cpu.iew.wb_consumers 1689629138 # num instructions consuming a value +system.cpu.iew.exec_nop 81 # number of nop insts executed +system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed +system.cpu.iew.exec_branches 229598858 # Number of branches executed +system.cpu.iew.exec_stores 181759645 # Number of stores executed +system.cpu.iew.exec_rate 1.208393 # Inst execution rate +system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169265268 # num instructions producing a value +system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.199083 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692065 # average fanout of values written-back +system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257853927 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630548 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1466512041 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.134687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.044179 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 886829793 60.47% 60.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250699029 17.09% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 109472668 7.46% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55016344 3.75% 88.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29216480 1.99% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 33954895 2.32% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24874922 1.70% 94.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18134171 1.24% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58313739 3.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1466512041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -688,390 +704,77 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 58313739 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3330084063 # The number of ROB reads -system.cpu.rob.rob_writes 3883248692 # The number of ROB writes -system.cpu.timesIdled 433 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24299 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3336711734 # The number of ROB reads +system.cpu.rob.rob_writes 3883178493 # The number of ROB writes +system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.975038 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.975038 # CPI: Total CPI of All Threads -system.cpu.ipc 1.025601 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.025601 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2176017062 # number of integer regfile reads -system.cpu.int_regfile_writes 1261587528 # number of integer regfile writes +system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads +system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads +system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 49 # number of floating regfile writes -system.cpu.cc_regfile_reads 6966468810 # number of cc regfile reads -system.cpu.cc_regfile_writes 551975360 # number of cc regfile writes -system.cpu.misc_regfile_reads 675847678 # number of misc regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads +system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes +system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 14271352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14271352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4800041 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2156446 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737659 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2176 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38815887 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38818063 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1395709696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1395779328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2156446 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23967212 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.089975 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.286146 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21810766 91.00% 91.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 2156446 9.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23967212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15706134446 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1655247 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25977831897 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 600 # number of replacements -system.cpu.icache.tags.tagsinuse 446.759697 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656842791 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1088 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 603715.800551 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 446.759697 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.872578 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.872578 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313689140 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313689140 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656842791 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656842791 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656842791 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656842791 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656842791 # number of overall hits -system.cpu.icache.overall_hits::total 656842791 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1235 # number of overall misses -system.cpu.icache.overall_misses::total 1235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31675742 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31675742 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31675742 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31675742 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31675742 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31675742 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656844026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656844026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656844026 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656844026 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656844026 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656844026 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25648.374089 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25648.374089 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25648.374089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25648.374089 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3135 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 123 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.487805 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1088 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1088 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1088 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1088 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1088 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1088 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25912248 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25912248 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25912248 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25912248 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25912248 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25912248 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23816.404412 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23816.404412 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 15355050 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 500576 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 12135733 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 866797 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 351771 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 1500173 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5090638 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 5094046 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16133.549273 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 15376042 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5109996 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.009013 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 29446587000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4939.304770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3.959471 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6800.251946 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4390.033086 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.301471 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000242 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.415054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.267946 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14923 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 102 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 570 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 346 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 521 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2353 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9340 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.910828 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 356792487 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 356792487 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 832 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 11525794 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11526626 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 4800041 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 4800041 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1796540 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1796540 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 832 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13322334 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13323166 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 832 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13322334 # number of overall hits -system.cpu.l2cache.overall_hits::total 13323166 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 256 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 2744470 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2744726 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 941119 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 941119 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 256 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3685589 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3685845 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 256 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3685589 # number of overall misses -system.cpu.l2cache.overall_misses::total 3685845 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19831249 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 216838606544 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 216858437793 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93637023447 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 93637023447 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19831249 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 310475629991 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 310495461240 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19831249 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 310475629991 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 310495461240 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1088 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 14270264 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 14271352 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 4800041 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 4800041 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737659 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737659 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1088 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17007923 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17009011 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1088 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17007923 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17009011 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.235294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.192321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.192324 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.343768 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.343768 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235294 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216698 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216700 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235294 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216698 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216700 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77465.816406 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79009.282865 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79009.138906 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 99495.412851 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 99495.412851 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77465.816406 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84240.437550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84239.967020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77465.816406 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84240.437550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84239.967020 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 114068 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3696 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30.862554 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1672636 # number of writebacks -system.cpu.l2cache.writebacks::total 1672636 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67618 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 67646 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 4482 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 4482 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 72100 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 72128 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 72100 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 72128 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2676852 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2677080 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1500168 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 936637 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 936637 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3613489 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3613717 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3613489 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5113885 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16681749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 190526161225 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 190542842974 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 108098150766 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 108098150766 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85432139513 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85432139513 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16681749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275958300738 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 275974982487 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16681749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275958300738 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 108098150766 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 384073133253 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.187583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.187584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.342131 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.342131 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212459 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.300657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73165.565789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.455806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71175.625298 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72057.363419 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91211.578779 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91211.578779 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76368.731278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75103.983225 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 17007411 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.965023 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638377840 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17007923 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.534145 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77012000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.965023 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17007297 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 449 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335546211 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335546211 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469430568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469430568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168947154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168947154 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638377722 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638377722 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638377722 # number of overall hits -system.cpu.dcache.overall_hits::total 638377722 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17252405 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17252405 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3638893 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3638893 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638259156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638259156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638259156 # number of overall hits +system.cpu.dcache.overall_hits::total 638259156 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17258559 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17258559 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3790674 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3790674 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 20891298 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20891298 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20891300 # number of overall misses -system.cpu.dcache.overall_misses::total 20891300 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 389285003128 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 389285003128 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129453998118 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129453998118 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 384750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 384750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 518739001246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 518739001246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 518739001246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 518739001246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486682973 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486682973 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21049235 # number of overall misses +system.cpu.dcache.overall_misses::total 21049235 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 392276819281 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 392276819281 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 143202458834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 143202458834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 535479278115 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 535479278115 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 535479278115 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -1080,92 +783,421 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659269020 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659269020 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659269022 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659269022 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035449 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035449 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.021085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.031689 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.031689 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031689 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031689 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22564.100665 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22564.100665 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35575.104329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35575.104329 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 96187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 96187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24830.386376 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24830.386376 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24830.383999 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24830.383999 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20820542 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1650046 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1039120 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 52884 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.036706 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 31.201233 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4800041 # number of writebacks -system.cpu.dcache.writebacks::total 4800041 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2982110 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2982110 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 901266 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 901266 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks +system.cpu.dcache.writebacks::total 4837992 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1053221 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3883376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3883376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3883376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3883376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270295 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14270295 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737627 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737627 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4041425 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4041425 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4041425 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4041425 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270355 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14270355 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737453 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737453 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17007922 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17007922 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17007923 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17007923 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 301459973376 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 301459973376 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108130443900 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 108130443900 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 101000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 101000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 409590417276 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 409590417276 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 409590518276 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 409590518276 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17007808 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17007808 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17007809 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17007809 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 303479537034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 303479537034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 110174073244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 110174073244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 413653610278 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 413653610278 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 413653672278 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 413653672278 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029319 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029319 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015861 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015861 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025798 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025798 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21124.999404 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21124.999404 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39497.873122 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39497.873122 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 101000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 101000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24082.331591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24082.331591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24082.336113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24082.336113 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025796 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025796 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21266.432197 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21266.432197 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40246.927799 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40246.927799 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24321.394637 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24321.394637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24321.396852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24321.396852 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 591 # number of replacements +system.cpu.icache.tags.tagsinuse 445.749905 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656876635 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 608782.794254 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 445.749905 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.870605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.870605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313757597 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313757597 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656876635 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656876635 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656876635 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656876635 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656876635 # 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mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.219377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75323.218263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73995.579018 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 14271401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 14271401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1352607 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3738412 # Transaction distribution +system.membus.trans_dist::ReadResp 3738412 # Transaction distribution +system.membus.trans_dist::Writeback 1638491 # Transaction distribution +system.membus.trans_dist::ReadExReq 981933 # Transaction distribution +system.membus.trans_dist::ReadExResp 981933 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6358836 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6358836 # Request fanout histogram +system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index fc3ec094e..c26ad4c6d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490000 # Number of ticks simulated final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2048371 # Simulator instruction rate (inst/s) -host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1103406177 # Simulator tick rate (ticks/s) -host_mem_usage 296712 # Number of bytes of host memory used -host_seconds 754.04 # Real time elapsed on the host +host_inst_rate 1680600 # Simulator instruction rate (inst/s) +host_op_rate 1810592 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 905297170 # Simulator tick rate (ticks/s) +host_mem_usage 301428 # Number of bytes of host memory used +host_seconds 919.05 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 750174605 # Wr system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution -system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution -system.membus.trans_dist::WriteReq 172586047 # Transaction distribution -system.membus.trans_dist::WriteResp 172586047 # Transaction distribution -system.membus.trans_dist::SoftPFReq 1 # Transaction distribution -system.membus.trans_dist::SoftPFResp 1 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondResp 61 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram -system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 2172060894 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction +system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution +system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution +system.membus.trans_dist::WriteReq 172586047 # Transaction distribution +system.membus.trans_dist::WriteResp 172586047 # Transaction distribution +system.membus.trans_dist::SoftPFReq 1 # Transaction distribution +system.membus.trans_dist::SoftPFResp 1 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondResp 61 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram +system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 2172060894 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 1aeb45981..89012dc1c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.363671 # Nu sim_ticks 2363670998000 # Number of ticks simulated final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1205605 # Simulator instruction rate (inst/s) -host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1851916301 # Simulator tick rate (ticks/s) -host_mem_usage 306192 # Number of bytes of host memory used -host_seconds 1276.34 # Real time elapsed on the host +host_inst_rate 1113267 # Simulator instruction rate (inst/s) +host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1710076181 # Simulator tick rate (ticks/s) +host_mem_usage 309628 # Number of bytes of host memory used +host_seconds 1382.20 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 27542188 # To system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1177898 # Transaction distribution -system.membus.trans_dist::ReadResp 1177898 # Transaction distribution -system.membus.trans_dist::Writeback 1017198 # Transaction distribution -system.membus.trans_dist::ReadExReq 780876 # Transaction distribution -system.membus.trans_dist::ReadExResp 780876 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2975972 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2975972 # Request fanout histogram -system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,137 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits +system.cpu.dcache.overall_hits::total 618379947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses +system.cpu.dcache.overall_misses::total 9115236 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks +system.cpu.dcache.writebacks::total 3697418 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. @@ -438,137 +577,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits -system.cpu.dcache.overall_hits::total 618379947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses -system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks -system.cpu.dcache.writebacks::total 3697418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution @@ -602,5 +610,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 957000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1177898 # Transaction distribution +system.membus.trans_dist::ReadResp 1177898 # Transaction distribution +system.membus.trans_dist::Writeback 1017198 # Transaction distribution +system.membus.trans_dist::ReadExReq 780876 # Transaction distribution +system.membus.trans_dist::ReadExResp 780876 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2975972 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2975972 # Request fanout histogram +system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 38e101aaf..3a5076b7f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.052167 # Nu sim_ticks 52167245000 # Number of ticks simulated final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231551 # Simulator instruction rate (inst/s) -host_op_rate 231551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131435822 # Simulator tick rate (ticks/s) -host_mem_usage 240584 # Number of bytes of host memory used -host_seconds 396.90 # Real time elapsed on the host +host_inst_rate 368966 # Simulator instruction rate (inst/s) +host_op_rate 368966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209437459 # Simulator tick rate (ticks/s) +host_mem_usage 299464 # Number of bytes of host memory used +host_seconds 249.08 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 386 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.254620 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.254822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.143137 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 322 33.06% 33.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190 19.51% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 9.86% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 102 10.47% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 61 6.26% 79.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.70% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 25 2.57% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 2.57% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 117 12.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 974 # Bytes accessed per row activation -system.physmem.totQLat 31955000 # Total ticks spent queuing -system.physmem.totMemAccLat 131667500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.971193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 211.834828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.374999 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 320 32.92% 32.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191 19.65% 52.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96 9.88% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 99 10.19% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 6.48% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 3.70% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.47% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 2.67% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 117 12.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 972 # Bytes accessed per row activation +system.physmem.totQLat 32099750 # Total ticks spent queuing +system.physmem.totMemAccLat 131812250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6008.84 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6036.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24758.84 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24786.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s @@ -212,43 +212,48 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4336 # Number of row buffer hits during reads +system.physmem.readRowHits 4338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9809545.60 # Average gap between requests -system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49062382500 # Time in different power states -system.physmem.memoryStateTime::REF 1741740000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1356240000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3530520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1926375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19827600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 21216000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1740241350 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1807017705 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29769681750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29711106000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34942051035 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34952037330 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.896806 # Core power per rank (mW) -system.physmem.averagePower::1 670.088260 # Core power per rank (mW) -system.cpu.branchPred.lookups 11476347 # Number of BP lookups +system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3530520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1926375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19827600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1740830445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29769165000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34942123380 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.898193 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49520504500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898118000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3772440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2058375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1807143390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29710995750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34952029395 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.088108 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49425818250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 995309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 11476348 # Number of BP lookups system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176736 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 1176737 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -267,10 +272,10 @@ system.cpu.dtb.data_hits 26977004 # DT system.cpu.dtb.data_misses 47407 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27024411 # DTB accesses -system.cpu.itb.fetch_hits 23068125 # ITB hits +system.cpu.itb.fetch_hits 23068130 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23068213 # ITB accesses +system.cpu.itb.fetch_accesses 23068218 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,15 +298,15 @@ system.cpu.discardedOps 2153944 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.135266 # CPI: cycles per instruction system.cpu.ipc 0.880851 # IPC: instructions per cycle -system.cpu.tickCycles 102681426 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1653064 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 102681434 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1653056 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.700924 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1448.700214 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700924 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700214 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -329,14 +334,14 @@ system.cpu.dcache.demand_misses::cpu.inst 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37712750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37712750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 194587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 194587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 232300250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232300250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 232300250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232300250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37684500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 195045500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 232730000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 232730000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 20070465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) @@ -353,14 +358,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72664.258189 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72664.258189 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66845.585709 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66845.585709 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67726.020408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67726.020408 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72609.826590 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67002.919959 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,14 +392,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151325500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151325500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151325500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151325500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34103500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117640500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151744000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151744000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses @@ -403,24 +408,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70379.381443 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70379.381443 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67158.452722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67158.452722 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70316.494845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67415.759312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13871 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.666168 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23052289 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.665289 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23052294 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1455.780802 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1455.781118 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.666168 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801107 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801107 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.665289 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801106 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -428,44 +433,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669 system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46152085 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46152085 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23052289 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23052289 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23052289 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23052289 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23052289 # number of overall hits -system.cpu.icache.overall_hits::total 23052289 # number of overall hits +system.cpu.icache.tags.tag_accesses 46152095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46152095 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23052294 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23052294 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23052294 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23052294 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23052294 # number of overall hits +system.cpu.icache.overall_hits::total 23052294 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses system.cpu.icache.overall_misses::total 15836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386603500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386603500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 386603500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386603500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 386603500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386603500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23068125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23068125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23068125 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23068125 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23068125 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23068125 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 386327750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 386327750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 386327750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 386327750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 386327750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 386327750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23068130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23068130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23068130 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23068130 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23068130 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23068130 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24412.951503 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24412.951503 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24412.951503 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24412.951503 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24395.538646 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24395.538646 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,33 +485,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15836 system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353567500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353567500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353567500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353567500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353567500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353567500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353292250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 353292250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353292250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 353292250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353292250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 353292250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22326.818641 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22326.818641 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2479.834280 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2479.833240 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.054210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.053168 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075136 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy @@ -537,14 +542,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5318 # system.cpu.l2cache.demand_misses::total 5318 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5318 # number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 244164500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 244164500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115186000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115186000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 359350500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359350500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 359350500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359350500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 243859250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115635000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 359494250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 359494250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 16320 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) @@ -563,14 +568,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.294381 system.cpu.l2cache.demand_miss_rate::total 0.294381 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.294381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67842.317310 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67842.317310 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67007.562536 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67007.562536 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67572.489658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67572.489658 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67757.502084 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67268.760908 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,14 +592,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5318 system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5318 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198927000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198927000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292296000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 292296000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292296000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 292296000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198623250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93817500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292440750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.220527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses @@ -603,14 +608,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294381 system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55272.853570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.853570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54315.881326 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54315.881326 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55188.455126 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54576.788831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution @@ -637,9 +642,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24435500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24435250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 3599 # Transaction distribution system.membus.trans_dist::ReadResp 3599 # Transaction distribution @@ -660,9 +665,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6477500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6478000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50028000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50027750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 3e567522b..fbd001a0c 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022159 # Nu sim_ticks 22159411000 # Number of ticks simulated final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173006 # Simulator instruction rate (inst/s) -host_op_rate 173006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45541949 # Simulator tick rate (ticks/s) -host_mem_usage 243048 # Number of bytes of host memory used -host_seconds 486.57 # Real time elapsed on the host +host_inst_rate 210811 # Simulator instruction rate (inst/s) +host_op_rate 210811 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55493646 # Simulator tick rate (ticks/s) +host_mem_usage 299980 # Number of bytes of host memory used +host_seconds 399.31 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # By system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 41291750 # Total ticks spent queuing -system.physmem.totMemAccLat 139391750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 41292000 # Total ticks spent queuing +system.physmem.totMemAccLat 139392000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7892.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7892.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26642.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26642.20 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 83.22 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 4235344.32 # Average gap between requests system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 20543925500 # Time in different power states -system.physmem.memoryStateTime::REF 739700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 868697500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3137400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3341520 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1711875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1823250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19453200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 20802600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 893934990 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 919865430 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 12507131250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 12484385250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 14872221915 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14877071250 # Total energy per rank (pJ) -system.physmem.averagePower::0 671.367239 # Core power per rank (mW) -system.physmem.averagePower::1 671.586150 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1709 # Transaction distribution -system.membus.trans_dist::ReadExResp 1709 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5232 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5232 # Request fanout histogram -system.membus.reqLayer0.occupancy 6530000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48921000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19453200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 894020490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12507056250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14872232415 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.367713 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20804380500 # Time in different power states +system.physmem_0.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 608242500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20802600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 920005650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12484262250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14877088470 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.586927 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20766250250 # Time in different power states +system.physmem_1.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 646430250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 16298030 # Number of BP lookups system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -314,22 +296,22 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 44318823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16859440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 16859439 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26218420 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 26218422 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44094962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 44094963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19653197 44.57% 44.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19653198 44.57% 44.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) @@ -341,11 +323,11 @@ system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44094962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 44094963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13063436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8246929 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 13063435 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8246931 # Number of cycles decode is blocked system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing @@ -354,16 +336,16 @@ system.cpu.decode.BranchMispred 12053 # Nu system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14206626 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4728528 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 14206625 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4728440 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3626870 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 3626960 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 46116 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 46206 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups @@ -384,23 +366,23 @@ system.cpu.iq.iqSquashedInstsIssued 120259 # Nu system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44094962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 44094963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7754469 17.59% 43.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7754470 17.59% 43.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4489383 10.18% 84.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2977389 6.75% 90.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4489384 10.18% 84.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2977388 6.75% 90.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44094962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44094963 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available @@ -473,7 +455,7 @@ system.cpu.iq.FU_type_0::total 100102500 # Ty system.cpu.iq.rate 2.258690 # Inst issue rate system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231175585 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 231175586 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads @@ -493,15 +475,15 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3707628 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461879 # Number of cycles IEW is unblocking +system.cpu.iew.iewBlockCycles 3707612 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 461807 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 414957 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 414885 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly @@ -517,8 +499,8 @@ system.cpu.iew.exec_stores 7162603 # Nu system.cpu.iew.exec_rate 2.227716 # Inst execution rate system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67088119 # num instructions producing a value -system.cpu.iew.wb_consumers 95122375 # num instructions consuming a value +system.cpu.iew.wb_producers 67088120 # num instructions producing a value +system.cpu.iew.wb_consumers 95122376 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back @@ -526,11 +508,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39466886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 39466887 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14969499 37.93% 37.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14969500 37.93% 37.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle @@ -542,7 +524,7 @@ system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39466886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39466887 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -590,10 +572,10 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 156894390 # The number of ROB reads +system.cpu.rob.rob_reads 156894391 # The number of ROB reads system.cpu.rob.rob_writes 251967276 # The number of ROB writes system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223861 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 223860 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction @@ -606,42 +588,149 @@ system.cpu.fp_regfile_reads 6250590 # nu system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes system.cpu.misc_regfile_reads 718773 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17856500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 160 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.564933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits +system.cpu.dcache.overall_hits::total 28680491 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses +system.cpu.dcache.overall_misses::total 9410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65475750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65475750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 523849968 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 523849968 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 589325718 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 589325718 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 589325718 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 589325718 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62836.612284 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62836.612284 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62601.573614 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62601.573614 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62627.600213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62627.600213 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29227 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.692394 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 110 # number of writebacks +system.cpu.dcache.writebacks::total 110 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36153000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36153000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125731745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 125731745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161884745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161884745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70473.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70473.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72509.656863 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72509.656863 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9583 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.631019 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1600.631053 # Cycle average of tags in use system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631019 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631053 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id @@ -665,12 +754,12 @@ system.cpu.icache.demand_misses::cpu.inst 14533 # n system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses system.cpu.icache.overall_misses::total 14533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419606250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419606250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419606250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419606250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419606250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419606250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 419570250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 419570250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 419570250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 419570250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 419570250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 419570250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses @@ -683,12 +772,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28872.651896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28872.651896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28872.651896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28872.651896 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28870.174775 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28870.174775 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28870.174775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28870.174775 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -709,34 +798,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11519 system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306578000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306578000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306551250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 306551250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306551250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 306551250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306551250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 306551250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26614.983940 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26614.983940 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.661689 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.661689 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2401.991277 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2401.991328 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.703654 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347182 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940441 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.703660 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347225 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940444 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy @@ -774,17 +863,17 @@ system.cpu.l2cache.demand_misses::total 5232 # nu system.cpu.l2cache.overall_misses::cpu.inst 3065 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2167 # number of overall misses system.cpu.l2cache.overall_misses::total 5232 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210511250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35108000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245619250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123622250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 123622250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210511250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158730250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369241500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210511250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158730250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369241500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210484500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35100000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245584500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123658250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 123658250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210484500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158758250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 369242750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210484500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158758250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 369242750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11519 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12032 # number of ReadReq accesses(hits+misses) @@ -809,17 +898,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380039 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266082 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963968 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.380039 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68682.300163 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76655.021834 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69718.776611 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72336.015214 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72336.015214 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70573.681193 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70573.681193 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68673.572594 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76637.554585 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69708.912858 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72357.080164 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72357.080164 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70573.920107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70573.920107 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,17 +928,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5232 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3065 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171684750 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 303872750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292803 # mshr miss rate for ReadReq accesses @@ -861,153 +950,69 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380039 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380039 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56014.600326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64243.449782 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57084.374113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60130.046811 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60130.046811 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.362153 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64224.890830 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57074.794209 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60151.111761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60151.111761 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 160 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.564755 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564755 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits -system.cpu.dcache.overall_hits::total 28680491 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses -system.cpu.dcache.overall_misses::total 9410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65491750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65491750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 523624968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 523624968 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 589116718 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 589116718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 589116718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 589116718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.967370 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.967370 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62574.685468 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62574.685468 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62605.389798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62605.389798 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29209 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.672260 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 110 # number of writebacks -system.cpu.dcache.writebacks::total 110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125695745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125695745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161856745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161856745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161856745 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161856745 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70489.278752 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70489.278752 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72488.895617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72488.895617 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17856250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3523 # Transaction distribution +system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.membus.trans_dist::ReadExReq 1709 # Transaction distribution +system.membus.trans_dist::ReadExResp 1709 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5232 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5232 # Request fanout histogram +system.membus.reqLayer0.occupancy 6529000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 48920250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index be651ff21..75d7eb795 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131746 # Nu sim_ticks 131745950000 # Number of ticks simulated final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190259 # Simulator instruction rate (inst/s) -host_op_rate 200564 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145463120 # Simulator tick rate (ticks/s) -host_mem_usage 256996 # Number of bytes of host memory used -host_seconds 905.70 # Real time elapsed on the host +host_inst_rate 246838 # Simulator instruction rate (inst/s) +host_op_rate 260207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188720644 # Simulator tick rate (ticks/s) +host_mem_usage 315756 # Number of bytes of host memory used +host_seconds 698.10 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # By system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 28129500 # Total ticks spent queuing -system.physmem.totMemAccLat 100635750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 28130750 # Total ticks spent queuing +system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7274.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26024.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 76.29 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 34069268.55 # Average gap between requests system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 125856871250 # Time in different power states -system.physmem.memoryStateTime::REF 4399200000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1487617250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3092040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1687125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 16177200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 13767000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 3575888730 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3595740120 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 75909421500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 75892008000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 88111101795 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 88112204505 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.807404 # Core power per rank (mW) -system.physmem.averagePower::1 668.815774 # Core power per rank (mW) +system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.807422 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.815773 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 49935043 # Number of BP lookups system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 95.508866 # BT system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -348,12 +385,12 @@ system.cpu.ipc 0.653978 # IP system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.772721 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772721 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772724 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -387,12 +424,12 @@ system.cpu.dcache.overall_misses::cpu.inst 2436 # system.cpu.dcache.overall_misses::total 2436 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54011984 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115580250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115580250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 169592234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169592234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 169592234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169592234 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115610250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 169622234 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 169622234 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 28356322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) @@ -415,12 +452,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000060 system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70304.288321 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70304.288321 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69619.143678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69619.143678 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70322.536496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,12 +486,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 1810 system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47293264 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76493500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76493500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123786764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123786764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123786764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 123786764 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76508500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123801764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses @@ -465,20 +502,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66423.123596 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69666.211293 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69666.211293 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69679.872495 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2909 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.880839 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880839 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id @@ -502,12 +539,12 @@ system.cpu.icache.demand_misses::cpu.inst 4706 # n system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses system.cpu.icache.overall_misses::total 4706 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186392247 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186392247 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186392247 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186392247 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186392247 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186392247 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses @@ -520,12 +557,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39607.362303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39607.362303 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39607.362303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39607.362303 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,33 +577,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4706 system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176061753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176061753 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176061753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176061753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176061753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176061753 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37412.187208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37412.187208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520468 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491287 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy @@ -597,14 +634,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 3885 # system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3885 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191698500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 191698500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75314000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75314000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 267012500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267012500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 267012500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267012500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191684250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75329000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 267013250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 267013250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) @@ -623,14 +660,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.596225 system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.596225 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68581.127013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69109.174312 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,14 +690,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155803750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155803750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61486500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61486500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217290250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 217290250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217290250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 217290250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155790000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61501500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217291500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217291500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses @@ -669,14 +706,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56079.913607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56423.394495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution @@ -707,7 +744,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 5 # system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7517747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) @@ -732,7 +769,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 3867 # Request fanout histogram system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36361250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index eede9a19d..30df36f38 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084956 # Number of seconds simulated -sim_ticks 84955935500 # Number of ticks simulated -final_tick 84955935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085008 # Number of seconds simulated +sim_ticks 85008313500 # Number of ticks simulated +final_tick 85008313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133775 # Simulator instruction rate (inst/s) -host_op_rate 141021 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65959289 # Simulator tick rate (ticks/s) -host_mem_usage 311648 # Number of bytes of host memory used -host_seconds 1288.01 # Real time elapsed on the host +host_inst_rate 130085 # Simulator instruction rate (inst/s) +host_op_rate 137131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64179279 # Simulator tick rate (ticks/s) +host_mem_usage 313784 # Number of bytes of host memory used +host_seconds 1324.54 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 35328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 268480 # Number of bytes read from this memory -system.physmem.bytes_read::total 322048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18240 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 552 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 4195 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5032 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 214700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 415839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 3160227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3790765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 214700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 214700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 214700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 415839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 3160227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3790765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5032 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory +system.physmem.bytes_read::total 246528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127168 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3852 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1495948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 564651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 839447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2900046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1495948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1495948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1495948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 564651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 839447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2900046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3852 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5032 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3852 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 322048 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246528 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 322048 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246528 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 395 # Per bank write bursts -system.physmem.perBankRdBursts::1 288 # Per bank write bursts -system.physmem.perBankRdBursts::2 188 # Per bank write bursts -system.physmem.perBankRdBursts::3 388 # Per bank write bursts -system.physmem.perBankRdBursts::4 399 # Per bank write bursts -system.physmem.perBankRdBursts::5 367 # Per bank write bursts -system.physmem.perBankRdBursts::6 381 # Per bank write bursts -system.physmem.perBankRdBursts::7 279 # Per bank write bursts -system.physmem.perBankRdBursts::8 314 # Per bank write bursts -system.physmem.perBankRdBursts::9 341 # Per bank write bursts -system.physmem.perBankRdBursts::10 369 # Per bank write bursts -system.physmem.perBankRdBursts::11 260 # Per bank write bursts -system.physmem.perBankRdBursts::12 244 # Per bank write bursts -system.physmem.perBankRdBursts::13 279 # Per bank write bursts -system.physmem.perBankRdBursts::14 295 # Per bank write bursts -system.physmem.perBankRdBursts::15 245 # Per bank write bursts +system.physmem.perBankRdBursts::0 309 # Per bank write bursts +system.physmem.perBankRdBursts::1 223 # Per bank write bursts +system.physmem.perBankRdBursts::2 142 # Per bank write bursts +system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::4 300 # Per bank write bursts +system.physmem.perBankRdBursts::5 302 # Per bank write bursts +system.physmem.perBankRdBursts::6 262 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts +system.physmem.perBankRdBursts::8 252 # Per bank write bursts +system.physmem.perBankRdBursts::9 218 # Per bank write bursts +system.physmem.perBankRdBursts::10 293 # Per bank write bursts +system.physmem.perBankRdBursts::11 194 # Per bank write bursts +system.physmem.perBankRdBursts::12 193 # Per bank write bursts +system.physmem.perBankRdBursts::13 212 # Per bank write bursts +system.physmem.perBankRdBursts::14 211 # Per bank write bursts +system.physmem.perBankRdBursts::15 194 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 84955621000 # Total gap between requests +system.physmem.totGap 85008170000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5032 # Read request sizes (log2) +system.physmem.readPktSize::6 3852 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,98 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 467.413643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 304.114713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 362.347713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 143 20.75% 20.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 123 17.85% 38.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 63 9.14% 47.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 10.01% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 45 6.53% 64.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 51 7.40% 71.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 42 6.10% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 3.05% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 132 19.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 689 # Bytes accessed per row activation -system.physmem.totQLat 114920157 # Total ticks spent queuing -system.physmem.totMemAccLat 209270157 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 25160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22837.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.936842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.366462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.047629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 237 31.18% 31.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 182 23.95% 55.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 69 9.08% 64.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 96 12.63% 76.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.61% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 5.92% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 2.37% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 14 1.84% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 64 8.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 760 # Bytes accessed per row activation +system.physmem.totQLat 36289181 # Total ticks spent queuing +system.physmem.totMemAccLat 108514181 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19260000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9420.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41587.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28170.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing +system.physmem.avgRdQLen 3.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4343 # Number of row buffer hits during reads +system.physmem.readRowHits 3085 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 16883072.54 # Average gap between requests -system.physmem.pageHitRate 86.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 81214099250 # Time in different power states -system.physmem.memoryStateTime::REF 2836600000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 905088250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2585520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2623320 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1410750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1431375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 20943000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 18306600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 5548898160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 5548898160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2301036705 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2237438385 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 48955167000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 49010955000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 56830041135 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 56819652840 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.934726 # Core power per rank (mW) -system.physmem.averagePower::1 668.812447 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4821 # Transaction distribution -system.membus.trans_dist::ReadResp 4821 # Transaction distribution -system.membus.trans_dist::ReadExReq 211 # Transaction distribution -system.membus.trans_dist::ReadExResp 211 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 322048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 322048 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5032 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5032 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5032 # Request fanout histogram -system.membus.reqLayer0.occupancy 5681641 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46027985 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85925623 # Number of BP lookups -system.cpu.branchPred.condPredicted 68405598 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6015157 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40113883 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39024614 # Number of BTB hits +system.physmem.avgGap 22068579.96 # Average gap between requests +system.physmem.pageHitRate 80.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2721600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1485000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2339255205 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48949672500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56861323425 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.935094 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81434793722 # Time in different power states +system.physmem_0.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 733662278 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3001320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1637625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13540800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2301878880 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48982450500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56854458645 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.854443 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81486384408 # Time in different power states +system.physmem_1.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 678791592 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 85929478 # Number of BP lookups +system.cpu.branchPred.condPredicted 68409655 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6016514 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40103730 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39019729 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.284559 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3701789 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81904 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.297007 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3701200 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81899 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -303,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -324,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -345,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -367,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169911872 # number of cpu cycles simulated +system.cpu.numCycles 170016628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5595281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349266175 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85925623 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42726403 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158254745 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12044333 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingQuiesceStallCycles 37 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 592 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78952832 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17522 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169872950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.151005 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.046766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5612512 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349284796 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85929478 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42720929 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158258026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12046973 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1522 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 2068 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78953849 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17938 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169897637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150791 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.046975 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17324644 10.20% 10.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30203623 17.78% 27.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31840188 18.74% 46.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90504495 53.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17345965 10.21% 10.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30201314 17.78% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31838054 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90512304 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169872950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505707 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.055573 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17551129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17096204 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122646615 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6731659 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5847343 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11137012 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306601093 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27639828 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5847343 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37738327 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8403981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578579 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108919553 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8385167 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278647204 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13415116 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3048397 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841923 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187656 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 31854 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 78402 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483062515 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196895890 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297562467 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006395 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169897637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505418 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.054416 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17565023 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17095500 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122663721 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6724834 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5848559 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11136257 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190151 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306621954 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27645544 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5848559 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37752791 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8406678 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 578098 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108929543 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8381968 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278665579 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13416120 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3045260 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842372 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187359 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 31268 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 80203 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483123422 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196973277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297590130 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005585 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190085586 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23420 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13351603 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34138378 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14478835 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2550837 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1806189 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264810642 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 190146493 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23418 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13341047 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34139788 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476953 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2546690 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1793951 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264825375 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214907655 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190996 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82629036 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219889900 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 214906973 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5192109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82644277 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219958197 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169872950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.265108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 169897637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017502 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52803027 31.08% 31.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36096104 21.25% 52.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65778237 38.72% 91.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13576092 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571163 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47813 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 514 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52826553 31.09% 31.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36096362 21.25% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65782146 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13572889 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571303 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47864 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 520 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169872950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169897637 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35609099 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152890 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35601312 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152935 0.28% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available @@ -475,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1075 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35725 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 330 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35738 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 318 0.00% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 815 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34388 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 217 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 812 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34382 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 216 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14076935 26.13% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3950981 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078938 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3947834 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167347451 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918969 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167350726 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918985 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -509,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33024 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165192 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245769 0.11% 78.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460683 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206710 0.10% 78.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71622 0.03% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460475 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32005523 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13376375 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32004909 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373295 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214907655 # Type of FU issued -system.cpu.iq.rate 1.264818 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53862656 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250632 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654786826 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 345480396 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204601887 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3955086 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2012108 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806636 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266634716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2135595 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601086 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214906973 # Type of FU issued +system.cpu.iq.rate 1.264035 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53853755 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654805304 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 345511813 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204602678 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952143 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2010627 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806422 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266627552 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133176 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600193 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6242234 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7548 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7115 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1834201 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6243644 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7556 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7106 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832319 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25938 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 647 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 661 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5847343 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682283 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37485 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264872462 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5848559 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681569 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36478 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264887188 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34138378 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14478835 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 34139788 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476953 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3828 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30448 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7115 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3233466 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3245683 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6479149 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207525838 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30720478 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7381817 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3814 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29479 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7106 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3233640 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247282 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6480922 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207527385 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30721175 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7379588 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15970 # number of nop insts executed -system.cpu.iew.exec_refs 43862877 # number of memory reference insts executed -system.cpu.iew.exec_branches 44936358 # Number of branches executed -system.cpu.iew.exec_stores 13142399 # Number of stores executed -system.cpu.iew.exec_rate 1.221373 # Inst execution rate -system.cpu.iew.wb_sent 206743657 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206408523 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129467920 # num instructions producing a value -system.cpu.iew.wb_consumers 221670950 # num instructions consuming a value +system.cpu.iew.exec_nop 15963 # number of nop insts executed +system.cpu.iew.exec_refs 43860513 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937173 # Number of branches executed +system.cpu.iew.exec_stores 13139338 # Number of stores executed +system.cpu.iew.exec_rate 1.220630 # Inst execution rate +system.cpu.iew.wb_sent 206744227 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206409100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129466460 # num instructions producing a value +system.cpu.iew.wb_consumers 221676348 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.214798 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584055 # average fanout of values written-back +system.cpu.iew.wb_rate 1.214052 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584034 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69532618 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69543087 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5840334 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158431709 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146553 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646732 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5841587 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158455572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146380 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73650115 46.49% 46.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41279051 26.05% 72.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22553954 14.24% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9627262 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3547678 2.24% 95.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2148088 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1282361 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 989322 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3353878 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73674398 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41276379 26.05% 72.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22551197 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9630660 6.08% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3550983 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2150131 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280461 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 988669 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3352694 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158431709 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158455572 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -641,487 +655,505 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 3353878 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3352694 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 406255589 # The number of ROB reads -system.cpu.rob.rob_writes 513821132 # The number of ROB writes -system.cpu.timesIdled 2630 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38922 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 406291105 # The number of ROB reads +system.cpu.rob.rob_writes 513842853 # The number of ROB writes +system.cpu.timesIdled 3394 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 118991 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986122 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986122 # CPI: Total CPI of All Threads -system.cpu.ipc 1.014073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.014073 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218958580 # number of integer regfile reads -system.cpu.int_regfile_writes 114511116 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904510 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441819 # number of floating regfile writes -system.cpu.cc_regfile_reads 709580018 # number of cc regfile reads -system.cpu.cc_regfile_writes 229533397 # number of cc regfile writes -system.cpu.misc_regfile_reads 59318521 # number of misc regfile reads +system.cpu.cpi 0.986730 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986730 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013448 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013448 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218960053 # number of integer regfile reads +system.cpu.int_regfile_writes 114514072 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904445 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441481 # number of floating regfile writes +system.cpu.cc_regfile_reads 709585079 # number of cc regfile reads +system.cpu.cc_regfile_writes 229544416 # number of cc regfile writes +system.cpu.misc_regfile_reads 59313443 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 119664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 7801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8632 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109774 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211691 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321465 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3512768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 7801 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 200978 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.038815 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.193155 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 193177 96.12% 96.12% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 7801 3.88% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 200978 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161464494 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82370974 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110177995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 54375 # number of replacements -system.cpu.icache.tags.tagsinuse 510.661166 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78896017 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54887 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1437.426294 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84218922500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.661166 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997385 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997385 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157960533 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157960533 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78896017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78896017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78896017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78896017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78896017 # number of overall hits -system.cpu.icache.overall_hits::total 78896017 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 56806 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 56806 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 56806 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 56806 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 56806 # number of overall misses -system.cpu.icache.overall_misses::total 56806 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 474677200 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 474677200 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 474677200 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 474677200 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 474677200 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 474677200 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78952823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78952823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78952823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78952823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78952823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78952823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000719 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000719 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000719 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000719 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000719 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8356.110270 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8356.110270 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8356.110270 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8356.110270 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 16306 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2267 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7.192766 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1919 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1919 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1919 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1919 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1919 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1919 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54887 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54887 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54887 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54887 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54887 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54887 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 380604754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 380604754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 380604754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 380604754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 380604754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 380604754 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6934.333339 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6934.333339 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 435044 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 3068 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 422406 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3291 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 894 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 5385 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 26500 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3680.652694 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 181097 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4769 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 37.973789 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 700.245747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 217.753448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 276.465568 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2486.187931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042740 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.013291 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016874 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.151745 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.224649 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 3319 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1450 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 648 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2491 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 987 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.202576 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.088501 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3104105 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3104105 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 54552 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 64413 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 118965 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 64873 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 64873 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8421 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8421 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 54552 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 72834 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 127386 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 54552 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 72834 # number of overall hits -system.cpu.l2cache.overall_hits::total 127386 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 364 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 699 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 575 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 910 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 575 # number of overall misses -system.cpu.l2cache.overall_misses::total 910 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24852997 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26184000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 51036997 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15318999 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15318999 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24852997 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 41502999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 66355996 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24852997 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 41502999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 66355996 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 54887 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 64777 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 119664 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 64873 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 64873 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8632 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8632 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54887 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 128296 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54887 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 128296 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.006103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.005619 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.005841 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.024444 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.024444 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.006103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.007833 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.007093 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.006103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.007833 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.007093 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74188.050746 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71934.065934 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73014.301860 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72601.890995 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72601.890995 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72918.676923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72918.676923 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 2973 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 134 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.186567 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 50 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 50 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 50 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 285 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 5385 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 5385 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 285 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 552 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 285 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 552 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 5385 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 6222 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20480998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 42531748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 326822301 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13544999 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13544999 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20480998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 35595749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 56076747 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20480998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 35595749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 382899048 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.005264 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005231 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.024444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.024444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.006524 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.048497 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71863.150877 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64664.956012 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67942.089457 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60691.235097 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64194.308057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64194.308057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66997.308244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61539.544841 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 72897 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.503812 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115488 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.439547 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41117509 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.087837 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 471699000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.503812 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999031 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999031 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 560.115367 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 497141250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.439547 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998905 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998905 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82528199 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82528199 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28728737 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28728737 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341838 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341838 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82532283 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82532283 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28730746 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28730746 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341850 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341850 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41070575 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41070575 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41070936 # number of overall hits -system.cpu.dcache.overall_hits::total 41070936 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89075 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89075 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22449 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22449 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 121 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41072596 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41072596 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41072957 # number of overall hits +system.cpu.dcache.overall_hits::total 41072957 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22437 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22437 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 111524 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 111524 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 111645 # number of overall misses -system.cpu.dcache.overall_misses::total 111645 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 824002993 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 824002993 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 221780748 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 221780748 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2327000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2327000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1045783741 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1045783741 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1045783741 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1045783741 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28817812 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28817812 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 111548 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 111548 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 111666 # number of overall misses +system.cpu.dcache.overall_misses::total 111666 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 835319240 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 835319240 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 222952999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 222952999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2325000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2325000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1058272239 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1058272239 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1058272239 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1058272239 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28819857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28819857 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 482 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 482 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41182099 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41182099 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41182581 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41182581 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003091 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003091 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001816 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001816 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.251037 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.251037 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41184144 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41184144 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41184623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41184623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003092 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003092 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001815 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001815 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002708 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002708 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9250.665091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9250.665091 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9879.315248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9879.315248 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8881.679389 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8881.679389 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9377.207964 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9377.207964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9367.045018 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9367.045018 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 279 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7362 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 531 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.864407 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9373.918371 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9373.918371 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9936.845345 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9936.845345 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8874.045802 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8874.045802 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9487.146690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9487.146690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9477.121407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9477.121407 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7730 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 532 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14.530075 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64873 # number of writebacks -system.cpu.dcache.writebacks::total 64873 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24343 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24343 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13890 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 13890 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 64874 # number of writebacks +system.cpu.dcache.writebacks::total 64874 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24383 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24383 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13871 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 13871 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38233 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38233 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38233 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38233 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64732 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64732 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8559 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8559 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 118 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 118 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73291 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73291 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 38254 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38254 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38254 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38254 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64728 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64728 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8566 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8566 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73294 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73294 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 483955005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 483955005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74150498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 74150498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1036250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1036250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 558105503 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 558105503 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 559141753 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 559141753 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 491417758 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 491417758 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74043249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 74043249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 982500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 982500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 565461007 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 565461007 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 566443507 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 566443507 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.244813 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.244813 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001783 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7476.286921 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7476.286921 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8663.453441 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8663.453441 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8781.779661 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8781.779661 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7614.925475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7614.925475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7616.801114 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7616.801114 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7592.042980 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7592.042980 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8643.853491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8643.853491 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8543.478261 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8543.478261 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7714.969943 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7714.969943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7716.267855 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7716.267855 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 54440 # number of replacements +system.cpu.icache.tags.tagsinuse 510.617911 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78896507 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54952 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.734951 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84258685250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.617911 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 157962600 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157962600 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78896507 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78896507 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78896507 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78896507 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78896507 # number of overall hits +system.cpu.icache.overall_hits::total 78896507 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57317 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57317 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57317 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57317 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57317 # number of overall misses +system.cpu.icache.overall_misses::total 57317 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 586515679 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 586515679 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 586515679 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 586515679 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 586515679 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 586515679 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78953824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78953824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78953824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78953824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78953824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78953824 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000726 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000726 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000726 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000726 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000726 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000726 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10232.839803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10232.839803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10232.839803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10232.839803 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 47827 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2525 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.941386 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2365 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 749 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2295 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015991 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.203003 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3103985 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3103985 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 52960 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 64249 # 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number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1987 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2502 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1816 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1816 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1987 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 750 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035470 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52440.613991 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58060.679612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53597.422062 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34908.254405 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56717.021277 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56717.021277 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53865.272196 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46304.115967 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 119724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8637 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321596 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12367040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2213 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 195448 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011323 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105804 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 193235 98.87% 98.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 2213 1.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 195448 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161491500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 82814471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 110208992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3617 # Transaction distribution +system.membus.trans_dist::ReadResp 3617 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7704 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3852 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3852 # Request fanout histogram +system.membus.reqLayer0.occupancy 5007645 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 36124927 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index b068c4279..7ececc2b6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491000 # Number of ticks simulated final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2060285 # Simulator instruction rate (inst/s) -host_op_rate 2171872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1190808654 # Simulator tick rate (ticks/s) -host_mem_usage 300012 # Number of bytes of host memory used -host_seconds 83.64 # Real time elapsed on the host +host_inst_rate 1699536 # Simulator instruction rate (inst/s) +host_op_rate 1791584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 982302061 # Simulator tick rate (ticks/s) +host_mem_usage 304728 # Number of bytes of host memory used +host_seconds 101.39 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 454362795 # Wr system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 217614902 # Transaction distribution -system.membus.trans_dist::ReadResp 217637309 # Transaction distribution -system.membus.trans_dist::WriteReq 12364287 # Transaction distribution -system.membus.trans_dist::WriteResp 12364287 # Transaction distribution -system.membus.trans_dist::SoftPFReq 463 # Transaction distribution -system.membus.trans_dist::SoftPFResp 463 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 230024466 # Request fanout histogram -system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 230024466 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction +system.membus.trans_dist::ReadReq 217614902 # Transaction distribution +system.membus.trans_dist::ReadResp 217637309 # Transaction distribution +system.membus.trans_dist::WriteReq 12364287 # Transaction distribution +system.membus.trans_dist::WriteResp 12364287 # Transaction distribution +system.membus.trans_dist::SoftPFReq 463 # Transaction distribution +system.membus.trans_dist::SoftPFResp 463 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 230024466 # Request fanout histogram +system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 230024466 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 394a8f6cf..62a10ca2c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230173 # Nu sim_ticks 230173357000 # Number of ticks simulated final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1215411 # Simulator instruction rate (inst/s) -host_op_rate 1281349 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1627973861 # Simulator tick rate (ticks/s) -host_mem_usage 309492 # Number of bytes of host memory used -host_seconds 141.39 # Real time elapsed on the host +host_inst_rate 1229194 # Simulator instruction rate (inst/s) +host_op_rate 1295881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1646435898 # Simulator tick rate (ticks/s) +host_mem_usage 312932 # Number of bytes of host memory used +host_seconds 139.80 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 480751 # In system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 2361 # Transaction distribution -system.membus.trans_dist::ReadResp 2361 # Transaction distribution -system.membus.trans_dist::ReadExReq 1092 # Transaction distribution -system.membus.trans_dist::ReadExResp 1092 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3453 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,139 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits +system.cpu.dcache.overall_hits::total 40117812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses +system.cpu.dcache.overall_misses::total 1789 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. @@ -430,139 +572,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits -system.cpu.dcache.overall_hits::total 40117812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses -system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution @@ -596,5 +605,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 4576500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 2361 # Transaction distribution +system.membus.trans_dist::ReadResp 2361 # Transaction distribution +system.membus.trans_dist::ReadExReq 1092 # Transaction distribution +system.membus.trans_dist::ReadExResp 1092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3453 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3453 # Request fanout histogram +system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index c2d74a54c..85460c89a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148694 # Number of seconds simulated -sim_ticks 148694012000 # Number of ticks simulated -final_tick 148694012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148652 # Number of seconds simulated +sim_ticks 148652306000 # Number of ticks simulated +final_tick 148652306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81223 # Simulator instruction rate (inst/s) -host_op_rate 136137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91445548 # Simulator tick rate (ticks/s) -host_mem_usage 288088 # Number of bytes of host memory used -host_seconds 1626.04 # Real time elapsed on the host +host_inst_rate 83185 # Simulator instruction rate (inst/s) +host_op_rate 139426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93628996 # Simulator tick rate (ticks/s) +host_mem_usage 346568 # Number of bytes of host memory used +host_seconds 1587.67 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 223936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125888 # Number of bytes read from this memory -system.physmem.bytes_read::total 349824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 223936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 223936 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1967 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5466 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1506019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 846625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2352643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1506019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1506019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1506019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 846625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2352643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5466 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125696 # Number of bytes read from this memory +system.physmem.bytes_read::total 350464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1964 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5476 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1512038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 845570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2357609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1512038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1512038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1512038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 845570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2357609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5476 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5466 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5476 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 349824 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 350464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 349824 # Total read bytes from the system interface side +system.physmem.bytesReadSys 350464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 294 # Per bank write bursts -system.physmem.perBankRdBursts::1 361 # Per bank write bursts -system.physmem.perBankRdBursts::2 463 # Per bank write bursts -system.physmem.perBankRdBursts::3 372 # Per bank write bursts -system.physmem.perBankRdBursts::4 337 # Per bank write bursts -system.physmem.perBankRdBursts::5 332 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 324 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 295 # Per bank write bursts +system.physmem.perBankRdBursts::1 363 # Per bank write bursts +system.physmem.perBankRdBursts::2 461 # Per bank write bursts +system.physmem.perBankRdBursts::3 370 # Per bank write bursts +system.physmem.perBankRdBursts::4 335 # Per bank write bursts +system.physmem.perBankRdBursts::5 334 # Per bank write bursts system.physmem.perBankRdBursts::6 400 # Per bank write bursts -system.physmem.perBankRdBursts::7 384 # Per bank write bursts -system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 235 # Per bank write bursts -system.physmem.perBankRdBursts::11 262 # Per bank write bursts -system.physmem.perBankRdBursts::12 222 # Per bank write bursts -system.physmem.perBankRdBursts::13 508 # Per bank write bursts +system.physmem.perBankRdBursts::7 383 # Per bank write bursts +system.physmem.perBankRdBursts::8 340 # Per bank write bursts +system.physmem.perBankRdBursts::9 286 # Per bank write bursts +system.physmem.perBankRdBursts::10 236 # Per bank write bursts +system.physmem.perBankRdBursts::11 261 # Per bank write bursts +system.physmem.perBankRdBursts::12 219 # Per bank write bursts +system.physmem.perBankRdBursts::13 509 # Per bank write bursts system.physmem.perBankRdBursts::14 392 # Per bank write bursts -system.physmem.perBankRdBursts::15 281 # Per bank write bursts +system.physmem.perBankRdBursts::15 292 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 148693969000 # Total gap between requests +system.physmem.totGap 148652208500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5466 # Read request sizes (log2) +system.physmem.readPktSize::6 5476 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,336 +186,314 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.532444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.678629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.994757 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 454 40.36% 40.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 235 20.89% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 101 8.98% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 52 4.62% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 60 5.33% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 5.24% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 19 1.69% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20 1.78% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1125 # Bytes accessed per row activation -system.physmem.totQLat 38946250 # Total ticks spent queuing -system.physmem.totMemAccLat 141433750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7125.18 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.265039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.960981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.625541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 464 40.45% 40.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 245 21.36% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 104 9.07% 70.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 4.97% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 54 4.71% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.97% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.09% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 15 1.31% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 127 11.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1147 # Bytes accessed per row activation +system.physmem.totQLat 37377750 # Total ticks spent queuing +system.physmem.totMemAccLat 140052750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27380000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6825.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25875.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25575.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.35 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4331 # Number of row buffer hits during reads +system.physmem.readRowHits 4321 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27203433.77 # Average gap between requests -system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 142073657250 # Time in different power states -system.physmem.memoryStateTime::REF 4964960000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1647900000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 4982040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3500280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2718375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1909875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 22776000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 19507800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 9711461760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 9711461760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 4022315865 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3825718020 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 85683555000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 85856009250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 99447809040 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 99418106985 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.842205 # Core power per rank (mW) -system.physmem.averagePower::1 668.642442 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 3933 # Transaction distribution -system.membus.trans_dist::ReadResp 3932 # Transaction distribution -system.membus.trans_dist::UpgradeReq 296 # Transaction distribution -system.membus.trans_dist::UpgradeResp 296 # Transaction distribution -system.membus.trans_dist::ReadExReq 1533 # Transaction distribution -system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5762 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5762 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5762 # Request fanout histogram -system.membus.reqLayer0.occupancy 7167000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 51861454 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 22382097 # Number of BP lookups -system.cpu.branchPred.condPredicted 22382097 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1553409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 14143770 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13239374 # Number of BTB hits +system.physmem.avgGap 27146130.11 # Average gap between requests +system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5072760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2767875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22791600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4015280925 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 85666359000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 99421191120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.838371 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 142511183750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1172773250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3575880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1951125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19585800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3861811845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 85800972750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 99396816360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.674456 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 142739163750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 947728750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 22375930 # Number of BP lookups +system.cpu.branchPred.condPredicted 22375930 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1550820 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14142904 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13245564 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.605694 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1523861 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22060 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.655193 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1524021 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21798 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 297388032 # number of cpu cycles simulated +system.cpu.numCycles 297304620 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27880008 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 249058784 # Number of instructions fetch has processed -system.cpu.fetch.Branches 22382097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14763235 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 267434691 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3695049 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 15 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4561 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42381 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27866919 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 248846814 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22375930 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14769585 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267364531 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3698749 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 56 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 42690 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26649696 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 257275 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 297209306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.380725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.789359 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26638460 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 257102 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 297128244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.381645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.790124 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 229177022 77.11% 77.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5084587 1.71% 78.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4138437 1.39% 80.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4791887 1.61% 81.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4876855 1.64% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5109175 1.72% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5334492 1.79% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4008000 1.35% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34688851 11.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229068376 77.09% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5099613 1.72% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4127262 1.39% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4784384 1.61% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4893969 1.65% 83.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5110538 1.72% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5334476 1.80% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3994023 1.34% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34715603 11.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 297209306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075262 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.837488 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16317003 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 231094890 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26094955 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21854934 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1847524 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 359064274 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1847524 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24114798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 162761005 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 33475 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38241804 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70210700 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350324590 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 42142 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 61992199 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7946895 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 152925 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 405428411 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 972465740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 641794462 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4665474 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 297128244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075263 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.837010 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16329336 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 230975824 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26113582 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21860128 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1849374 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359242894 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1849374 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24118008 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162656356 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 38273 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38263619 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70202614 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350538626 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 41453 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 61947521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7945702 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 153558 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405817730 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972424276 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 641996744 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4657501 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 145998961 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2154 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2076 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 128653734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89733483 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32018253 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63985001 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21567740 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 341091248 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266696686 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73290 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119329162 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 250439001 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3632 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 297209306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.897336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363195 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 146388280 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2397 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2322 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128546417 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89512895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32023027 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63891013 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21581901 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341300793 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5145 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266928835 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 76764 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119543073 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250225997 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3900 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 297128244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.898362 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364631 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 171484109 57.70% 57.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54269493 18.26% 75.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33638460 11.32% 87.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19147986 6.44% 93.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10817239 3.64% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4351297 1.46% 98.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2217356 0.75% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 890190 0.30% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 393176 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171384973 57.68% 57.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54250707 18.26% 75.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33605057 11.31% 87.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19187938 6.46% 93.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10808168 3.64% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4369052 1.47% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2227260 0.75% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 898004 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 397085 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 297209306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 297128244 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 237582 7.35% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2582537 79.93% 87.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 410926 12.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 240256 7.42% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2591676 80.04% 87.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 406020 12.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211351 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167148119 62.67% 63.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789126 0.30% 63.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035938 2.64% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1214032 0.46% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66518900 24.94% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22779220 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211341 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167360520 62.70% 63.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 793230 0.30% 63.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7036198 2.64% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1213739 0.45% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66512723 24.92% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22801084 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266696686 # Type of FU issued -system.cpu.iq.rate 0.896797 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3231045 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 828907957 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 456425026 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260744620 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4999056 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4321531 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2398079 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266200144 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2516236 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18853700 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266928835 # Type of FU issued +system.cpu.iq.rate 0.897829 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3237952 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012130 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 829304993 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 456859927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 261005005 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4995637 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4315017 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2397122 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266441955 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2513491 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18899538 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33083896 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14048 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 327034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11502536 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 32863308 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14004 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 331776 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11507310 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52807 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52520 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1847524 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 126225383 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5553775 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 341096125 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 111900 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89733483 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32018253 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2073 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2221761 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 397558 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 327034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 687554 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 924641 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1612195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264577830 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65651803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2118856 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1849374 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126083228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5521965 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341305938 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 113234 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89512895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32023027 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2291 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2224383 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 364956 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 331776 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 682604 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 926974 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1609578 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264820941 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65644877 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2107894 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 88227876 # number of memory reference insts executed -system.cpu.iew.exec_branches 14574542 # Number of branches executed -system.cpu.iew.exec_stores 22576073 # Number of stores executed -system.cpu.iew.exec_rate 0.889672 # Inst execution rate -system.cpu.iew.wb_sent 263857804 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 263142699 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208771445 # num instructions producing a value -system.cpu.iew.wb_consumers 376756650 # num instructions consuming a value +system.cpu.iew.exec_refs 88243318 # number of memory reference insts executed +system.cpu.iew.exec_branches 14594562 # Number of branches executed +system.cpu.iew.exec_stores 22598441 # Number of stores executed +system.cpu.iew.exec_rate 0.890739 # Inst execution rate +system.cpu.iew.wb_sent 264116022 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263402127 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208929627 # num instructions producing a value +system.cpu.iew.wb_consumers 376950815 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.884846 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554128 # average fanout of values written-back +system.cpu.iew.wb_rate 0.885967 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554262 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119784082 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119991036 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1557714 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 280934178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.787955 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.593006 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1555160 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280815934 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.788286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.594389 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 181002455 64.43% 64.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57799506 20.57% 85.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14236358 5.07% 90.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11930779 4.25% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4218902 1.50% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2886432 1.03% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 918195 0.33% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1050521 0.37% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6891030 2.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180962849 64.44% 64.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57749972 20.57% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14199777 5.06% 90.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11927311 4.25% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4203723 1.50% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2893126 1.03% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 916943 0.33% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048119 0.37% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6914114 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 280934178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280815934 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -561,252 +539,336 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6891030 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6914114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 615190614 # The number of ROB reads -system.cpu.rob.rob_writes 698614569 # The number of ROB writes -system.cpu.timesIdled 3122 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 178726 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615256240 # The number of ROB reads +system.cpu.rob.rob_writes 699066092 # The number of ROB writes +system.cpu.timesIdled 3079 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 176376 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.251725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.251725 # CPI: Total CPI of All Threads -system.cpu.ipc 0.444104 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.444104 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 456362005 # number of integer regfile reads -system.cpu.int_regfile_writes 239113538 # number of integer regfile writes -system.cpu.fp_regfile_reads 3275482 # number of floating regfile reads -system.cpu.fp_regfile_writes 2058196 # number of floating regfile writes -system.cpu.cc_regfile_reads 102983282 # number of cc regfile reads -system.cpu.cc_regfile_writes 60177632 # number of cc regfile writes -system.cpu.misc_regfile_reads 136798826 # number of misc regfile reads +system.cpu.cpi 2.251094 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.251094 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444229 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444229 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456513966 # number of integer regfile reads +system.cpu.int_regfile_writes 239334814 # number of integer regfile writes +system.cpu.fp_regfile_reads 3274089 # number of floating regfile reads +system.cpu.fp_regfile_writes 2057271 # number of floating regfile writes +system.cpu.cc_regfile_reads 102998380 # number of cc regfile reads +system.cpu.cc_regfile_writes 60202762 # number of cc regfile writes +system.cpu.misc_regfile_reads 136901121 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 8736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16221 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4632 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 20853 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 509376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 638784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 301 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10583 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10583 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10583 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5301999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12991249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3546296 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 5983 # number of replacements -system.cpu.icache.tags.tagsinuse 1649.665059 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26639065 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7962 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3345.775559 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 52 # number of replacements +system.cpu.dcache.tags.tagsinuse 1443.647680 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 67095165 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2013 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33330.931446 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1443.647680 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352453 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352453 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1961 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 441 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.478760 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134197329 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134197329 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46580786 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46580786 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513865 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513865 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67094651 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67094651 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67094651 # number of overall hits +system.cpu.dcache.overall_hits::total 67094651 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1141 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1866 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1866 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3007 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3007 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3007 # number of overall misses +system.cpu.dcache.overall_misses::total 3007 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64283437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64283437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116004574 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116004574 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 180288011 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 180288011 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 180288011 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 180288011 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46581927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46581927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 67097658 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67097658 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67097658 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67097658 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000091 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000091 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56339.559159 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56339.559159 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62167.510182 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62167.510182 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59956.106086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59956.106086 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 248 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.600000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 10 # number of writebacks +system.cpu.dcache.writebacks::total 10 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 666 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 667 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 667 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 667 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 667 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1865 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1865 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2340 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2340 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2340 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2340 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33671000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33671000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111589176 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 111589176 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145260176 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 145260176 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145260176 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 145260176 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000091 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000091 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70886.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70886.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59833.338338 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59833.338338 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 5851 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.461746 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26627917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7830 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3400.755683 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1649.665059 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.805501 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.805501 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.461746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801495 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801495 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 796 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 813 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 767 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 53307648 # Number of tag accesses -system.cpu.icache.tags.data_accesses 53307648 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26639065 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26639065 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26639065 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26639065 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26639065 # number of overall hits -system.cpu.icache.overall_hits::total 26639065 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10629 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10629 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10629 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10629 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10629 # number of overall misses -system.cpu.icache.overall_misses::total 10629 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 394374749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 394374749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 394374749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 394374749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 394374749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 394374749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26649694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26649694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26649694 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26649694 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26649694 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26649694 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37103.655000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37103.655000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37103.655000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37103.655000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1302 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 53285074 # Number of tag accesses +system.cpu.icache.tags.data_accesses 53285074 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26627919 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26627919 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26627919 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26627919 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26627919 # number of overall hits +system.cpu.icache.overall_hits::total 26627919 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10540 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10540 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10540 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10540 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10540 # number of overall misses +system.cpu.icache.overall_misses::total 10540 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 391405749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 391405749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 391405749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 391405749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 391405749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 391405749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26638459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26638459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26638459 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26638459 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26638459 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26638459 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000396 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000396 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000396 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000396 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000396 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37135.270304 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37135.270304 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37135.270304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37135.270304 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1286 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.461538 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2666 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120361 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 86925 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 86925 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 4317 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 44 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 4361 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # 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miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990826 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990826 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.439643 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.977634 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.548180 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.439643 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.977634 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.548180 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68764.357143 # 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number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3500 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 434 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3934 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 296 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 296 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3513 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 431 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3944 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 324 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 324 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.466390 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989967 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989967 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3513 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1964 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5477 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3513 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1964 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5477 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196758000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27393000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 224151000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3240823 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3240823 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 83086000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 83086000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196758000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110479000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 307237000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196758000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110479000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 307237000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.907368 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.474895 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990826 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.548180 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.548180 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56229.214286 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63407.258065 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57021.098119 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.685811 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.685811 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54695.205479 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54695.205479 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.556436 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.556436 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56008.539710 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63556.844548 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56833.417850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.540123 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.540123 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54198.303979 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54198.303979 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 52 # number of replacements -system.cpu.dcache.tags.tagsinuse 1451.665096 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 67147234 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33373.376740 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1451.665096 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.354410 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.354410 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1960 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1416 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.478516 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 134301424 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 134301424 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46632911 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46632911 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67146804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67146804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67146804 # number of overall hits -system.cpu.dcache.overall_hits::total 67146804 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1064 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1064 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2902 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2902 # number of overall misses -system.cpu.dcache.overall_misses::total 2902 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63689380 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63689380 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116173296 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116173296 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 179862676 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 179862676 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 179862676 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 179862676 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46633975 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46633975 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67149706 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67149706 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67149706 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67149706 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59858.439850 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59858.439850 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63206.363439 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63206.363439 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61978.868367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61978.868367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 10 # number of writebacks -system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 590 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 590 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 591 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 591 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 591 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 474 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 474 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1837 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1837 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2311 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2311 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2311 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2311 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33789250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33789250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111812454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 111812454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145601704 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 145601704 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145601704 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 145601704 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71285.337553 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71285.337553 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60866.877518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60866.877518 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 8632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 20676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 630528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 327 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10507 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10507 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5263999 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 12826749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3560824 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3943 # Transaction distribution +system.membus.trans_dist::ReadResp 3943 # Transaction distribution +system.membus.trans_dist::UpgradeReq 324 # Transaction distribution +system.membus.trans_dist::UpgradeResp 324 # Transaction distribution +system.membus.trans_dist::ReadExReq 1533 # Transaction distribution +system.membus.trans_dist::ReadExResp 1533 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5800 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5800 # Request fanout histogram +system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 51890176 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |