diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-11-17 04:54:14 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-11-17 04:54:14 -0500 |
| commit | 6ed567d6002df081dd6cf2db6685d3e66c11272b (patch) | |
| tree | d6df4c0abaf10391c9ca9fb9dfc833737c979e37 /tests/long/se | |
| parent | 74249f80df4e6128da38dfb5dbf5f61285c673a2 (diff) | |
| download | gem5-6ed567d6002df081dd6cf2db6685d3e66c11272b.tar.xz | |
alpha: Remove ALPHA tru64 support and associated tests
No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.
Diffstat (limited to 'tests/long/se')
74 files changed, 0 insertions, 27259 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/NOTE b/tests/long/se/20.parser/ref/alpha/tru64/NOTE deleted file mode 100644 index 5e7d8c358..000000000 --- a/tests/long/se/20.parser/ref/alpha/tru64/NOTE +++ /dev/null @@ -1,6 +0,0 @@ -I removed the reference outputs for this program because it's taking -way too long... over an hour for simple-atomic and over 19 hrs for -o3-timing. We need to find a shorter input if we want to keep this -in the regressions. - -Steve diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 4a417985d..000000000 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=parser 2.1.dict -batch -cwd=build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/parser -gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index 8606e90c7..000000000 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,72 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28069 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - - Reading the dictionary files: ************************************************* - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 422342506500 because target called exit() diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 61f620036..000000000 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,833 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.422343 # Number of seconds simulated -sim_ticks 422342506500 # Number of ticks simulated -final_tick 422342506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 474436 # Simulator instruction rate (inst/s) -host_op_rate 474436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 327462122 # Simulator tick rate (ticks/s) -host_mem_usage 257604 # Number of bytes of host memory used -host_seconds 1289.74 # Real time elapsed on the host -sim_insts 611901617 # Number of instructions simulated -sim_ops 611901617 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 156672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24196288 # Number of bytes read from this memory -system.physmem.bytes_read::total 24352960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18839168 # Number of bytes written to this memory -system.physmem.bytes_written::total 18839168 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 378067 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380515 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294362 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294362 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 370960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57290677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 57661636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 370960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 370960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 44606374 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 44606374 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 44606374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 370960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57290677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 102268011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380515 # Number of read requests accepted -system.physmem.writeReqs 294362 # Number of write requests accepted -system.physmem.readBursts 380515 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294362 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24331840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue -system.physmem.bytesWritten 18837824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24352960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18839168 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23759 # Per bank write bursts -system.physmem.perBankRdBursts::1 23180 # Per bank write bursts -system.physmem.perBankRdBursts::2 23498 # Per bank write bursts -system.physmem.perBankRdBursts::3 24625 # Per bank write bursts -system.physmem.perBankRdBursts::4 25498 # Per bank write bursts -system.physmem.perBankRdBursts::5 23629 # Per bank write bursts -system.physmem.perBankRdBursts::6 23701 # Per bank write bursts -system.physmem.perBankRdBursts::7 23987 # Per bank write bursts -system.physmem.perBankRdBursts::8 23227 # Per bank write bursts -system.physmem.perBankRdBursts::9 24022 # Per bank write bursts -system.physmem.perBankRdBursts::10 24752 # Per bank write bursts -system.physmem.perBankRdBursts::11 22836 # Per bank write bursts -system.physmem.perBankRdBursts::12 23786 # Per bank write bursts -system.physmem.perBankRdBursts::13 24450 # Per bank write bursts -system.physmem.perBankRdBursts::14 22762 # Per bank write bursts -system.physmem.perBankRdBursts::15 22473 # Per bank write bursts -system.physmem.perBankWrBursts::0 17837 # Per bank write bursts -system.physmem.perBankWrBursts::1 17476 # Per bank write bursts -system.physmem.perBankWrBursts::2 17996 # Per bank write bursts -system.physmem.perBankWrBursts::3 18950 # Per bank write bursts -system.physmem.perBankWrBursts::4 19553 # Per bank write bursts -system.physmem.perBankWrBursts::5 18644 # Per bank write bursts -system.physmem.perBankWrBursts::6 18825 # Per bank write bursts -system.physmem.perBankWrBursts::7 18731 # Per bank write bursts -system.physmem.perBankWrBursts::8 18487 # Per bank write bursts -system.physmem.perBankWrBursts::9 18977 # Per bank write bursts -system.physmem.perBankWrBursts::10 19288 # Per bank write bursts -system.physmem.perBankWrBursts::11 18104 # Per bank write bursts -system.physmem.perBankWrBursts::12 18331 # Per bank write bursts -system.physmem.perBankWrBursts::13 18778 # Per bank write bursts -system.physmem.perBankWrBursts::14 17209 # Per bank write bursts -system.physmem.perBankWrBursts::15 17155 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 422342412500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380515 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294362 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 379040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 138956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.667780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.031528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.663803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47467 34.16% 34.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38428 27.65% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13549 9.75% 71.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8124 5.85% 77.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5242 3.77% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3828 2.75% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3157 2.27% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2628 1.89% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16533 11.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 138956 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17561 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.649109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.965863 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 233.199678 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17556 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17561 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17561 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.761061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.733847 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.964147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10711 60.99% 60.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 371 2.11% 63.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 6450 36.73% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 26 0.15% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17561 # Writes before turning the bus around for reads -system.physmem.totQLat 8688901500 # Total ticks spent queuing -system.physmem.totMemAccLat 15817370250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1900925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22854.40 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41604.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 57.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 44.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 57.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 44.61 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.80 # Data bus utilization in percentage -system.physmem.busUtilRead 0.45 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.60 # Average write queue length when enqueuing -system.physmem.readRowHits 314590 # Number of row buffer hits during reads -system.physmem.writeRowHits 220977 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.07 # Row buffer hit rate for writes -system.physmem.avgGap 625806.50 # Average gap between requests -system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 505526280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 268693590 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1370001780 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 772622640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 11362849680.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8093551410 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 616183200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 31552584270 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 13412815680 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 73287717855 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 141246410115 # Total energy per rank (pJ) -system.physmem_0.averagePower 334.435695 # Core power per rank (mW) -system.physmem_0.totalIdleTime 402979630750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 931134000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4824278000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 298856786250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 34929182250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13606935500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 69194190500 # Time in different power states -system.physmem_1.actEnergy 486640980 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 258644430 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1344519120 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 763837380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 10801683360.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7884425820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 575860800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 29572982250 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 12813870240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 74790220020 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 139297315230 # Total energy per rank (pJ) -system.physmem_1.averagePower 329.820729 # Core power per rank (mW) -system.physmem_1.totalIdleTime 403542198250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 850086750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4586322000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 305319724750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 33369590750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13363845750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 64852936500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 124433445 # Number of BP lookups -system.cpu.branchPred.condPredicted 87996604 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6213149 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71713401 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67452940 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.059045 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15161931 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1121038 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7034 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4431 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2603 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 736 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149830728 # DTB read hits -system.cpu.dtb.read_misses 559329 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150390057 # DTB read accesses -system.cpu.dtb.write_hits 57603632 # DTB write hits -system.cpu.dtb.write_misses 71396 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57675028 # DTB write accesses -system.cpu.dtb.data_hits 207434360 # DTB hits -system.cpu.dtb.data_misses 630725 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 208065085 # DTB accesses -system.cpu.itb.fetch_hits 227956774 # ITB hits -system.cpu.itb.fetch_misses 48 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 227956822 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 844685013 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 611901617 # Number of instructions committed -system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14840042 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.380426 # CPI: cycles per instruction -system.cpu.ipc 0.724414 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction -system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction -system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 66.61% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::MemRead 146469180 23.94% 90.63% # Class of committed instruction -system.cpu.op_class_0::MemWrite 57213427 9.35% 99.98% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 96355 0.02% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 7556 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 611901617 # Class of committed instruction -system.cpu.tickCycles 746838140 # Number of cycles that the object actually ticked -system.cpu.idleCycles 97846873 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2535505 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.585414 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 203187430 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539601 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 80.007619 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1692948500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.585414 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997946 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997946 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 827 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3149 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 415624517 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 415624517 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147521210 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147521210 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666220 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666220 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 203187430 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 203187430 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 203187430 # number of overall hits -system.cpu.dcache.overall_hits::total 203187430 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1811214 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1811214 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543814 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543814 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3355028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3355028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3355028 # number of overall misses -system.cpu.dcache.overall_misses::total 3355028 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39457833000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39457833000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 51431912500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 51431912500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90889745500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90889745500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90889745500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90889745500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 149332424 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 149332424 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206542458 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206542458 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206542458 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206542458 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012129 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012129 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016244 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016244 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016244 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21785.295940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21785.295940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33314.837474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33314.837474 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27090.607142 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27090.607142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27090.607142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27090.607142 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2339286 # number of writebacks -system.cpu.dcache.writebacks::total 2339286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 46422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769005 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769005 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 815427 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 815427 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 815427 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 815427 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764792 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764792 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774809 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774809 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539601 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539601 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539601 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539601 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36307875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36307875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25218661500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25218661500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61526536500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61526536500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61526536500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61526536500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011818 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011818 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012296 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012296 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20573.458515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20573.458515 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32548.229951 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32548.229951 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24226.851580 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24226.851580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24226.851580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24226.851580 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3176 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.241776 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 227951769 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5005 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45544.808991 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.241776 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545040 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545040 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1592 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 455918553 # Number of tag accesses -system.cpu.icache.tags.data_accesses 455918553 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 227951769 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 227951769 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 227951769 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 227951769 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 227951769 # number of overall hits -system.cpu.icache.overall_hits::total 227951769 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5005 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5005 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5005 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5005 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5005 # number of overall misses -system.cpu.icache.overall_misses::total 5005 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293603500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293603500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293603500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293603500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293603500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293603500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 227956774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 227956774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 227956774 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 227956774 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 227956774 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 227956774 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58662.037962 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58662.037962 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58662.037962 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58662.037962 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58662.037962 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58662.037962 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3176 # number of writebacks -system.cpu.icache.writebacks::total 3176 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5005 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5005 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5005 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5005 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5005 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5005 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 288598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 288598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 288598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 288598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 288598500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 288598500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57662.037962 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57662.037962 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57662.037962 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 57662.037962 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57662.037962 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 57662.037962 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 348623 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30598.806406 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4701891 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 381391 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.328269 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 70474186000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 42.061592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.646104 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30397.098711 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001284 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.927646 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.933801 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1626 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30708 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41047687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41047687 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2339286 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2339286 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3176 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3176 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 571694 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571694 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2557 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2557 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1589840 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1589840 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2557 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2161534 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164091 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2557 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2161534 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164091 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 206458 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206458 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2448 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2448 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 171609 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 171609 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2448 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 378067 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380515 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2448 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 378067 # number of overall misses -system.cpu.l2cache.overall_misses::total 380515 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18097806000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 18097806000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 254224000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 254224000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16908659000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 16908659000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 254224000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35006465000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35260689000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 254224000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35006465000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35260689000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2339286 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2339286 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3176 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3176 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 778152 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778152 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5005 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5005 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1761449 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1761449 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5005 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2539601 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544606 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5005 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2539601 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544606 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265318 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265318 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.489111 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.489111 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.097425 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.097425 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.489111 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148869 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149538 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.489111 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148869 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149538 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87658.535877 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87658.535877 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103849.673203 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103849.673203 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98530.141193 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98530.141193 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103849.673203 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92593.283730 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 92665.700432 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103849.673203 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92593.283730 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 92665.700432 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 294362 # number of writebacks -system.cpu.l2cache.writebacks::total 294362 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 5 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206458 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206458 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2448 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2448 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 171609 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 171609 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2448 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 378067 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380515 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2448 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 378067 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380515 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16033226000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16033226000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 229744000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 229744000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15192569000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15192569000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229744000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 31225795000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31455539000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229744000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 31225795000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31455539000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265318 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265318 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.489111 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097425 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097425 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149538 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149538 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77658.535877 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77658.535877 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93849.673203 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93849.673203 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88530.141193 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88530.141193 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93849.673203 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82593.283730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82665.700432 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93849.673203 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82593.283730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82665.700432 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5083287 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538681 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2446 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2446 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1766454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 250480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778152 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778152 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761449 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13186 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614707 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7627893 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 523584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312248768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312772352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348623 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18839168 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2893229 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.029064 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2890783 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2446 0.08% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2893229 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4884105500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7507500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3809401500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 726697 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 346182 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 174057 # Transaction distribution -system.membus.trans_dist::WritebackDirty 294362 # Transaction distribution -system.membus.trans_dist::CleanEvict 51820 # Transaction distribution -system.membus.trans_dist::ReadExReq 206458 # Transaction distribution -system.membus.trans_dist::ReadExResp 206458 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174057 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1107212 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1107212 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43192128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43192128 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 380515 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 380515 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 380515 # Request fanout histogram -system.membus.reqLayer0.occupancy 2021742500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2013933750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 63271ea71..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index 9c10deefc..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,53 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index 6a622d0db..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28070 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.233333 -Exiting @ tick 233641094500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 2ec97b33e..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,794 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.233641 # Number of seconds simulated -sim_ticks 233641094500 # Number of ticks simulated -final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 449379 # Simulator instruction rate (inst/s) -host_op_rate 449379 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263362780 # Simulator tick rate (ticks/s) -host_mem_usage 260228 # Number of bytes of host memory used -host_seconds 887.15 # Real time elapsed on the host -sim_insts 398664651 # Number of instructions simulated -sim_ops 398664651 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory -system.physmem.bytes_read::total 503872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1066936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1089671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2156607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1066936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1066936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1066936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1089671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2156607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7873 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 548 # Per bank write bursts -system.physmem.perBankRdBursts::1 675 # Per bank write bursts -system.physmem.perBankRdBursts::2 473 # Per bank write bursts -system.physmem.perBankRdBursts::3 633 # Per bank write bursts -system.physmem.perBankRdBursts::4 475 # Per bank write bursts -system.physmem.perBankRdBursts::5 477 # Per bank write bursts -system.physmem.perBankRdBursts::6 563 # Per bank write bursts -system.physmem.perBankRdBursts::7 560 # Per bank write bursts -system.physmem.perBankRdBursts::8 471 # Per bank write bursts -system.physmem.perBankRdBursts::9 437 # Per bank write bursts -system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 323 # Per bank write bursts -system.physmem.perBankRdBursts::12 430 # Per bank write bursts -system.physmem.perBankRdBursts::13 556 # Per bank write bursts -system.physmem.perBankRdBursts::14 473 # Per bank write bursts -system.physmem.perBankRdBursts::15 425 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233641000500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7873 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.298625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.524272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.958390 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 522 34.18% 34.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 350 22.92% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 181 11.85% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 105 6.88% 75.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 64 4.19% 80.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 46 3.01% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 1.96% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 42 2.75% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 187 12.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation -system.physmem.totQLat 179319500 # Total ticks spent queuing -system.physmem.totMemAccLat 326938250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22776.51 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41526.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6337 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29676235.30 # Average gap between requests -system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6326040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3347190 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 31444560 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 242168160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 105016230 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 11391840 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 673376340 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 320465280 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 55494876360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 56888412000 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.486327 # Core power per rank (mW) -system.physmem_0.totalIdleTime 233381065000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 19761500 # Time in different power states -system.physmem_0.memoryStateTime::REF 102860000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 231069881000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 834517500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 137354250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1476720250 # Time in different power states -system.physmem_1.actEnergy 4641000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2447775 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 24768660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 215124000.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84187860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12227040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 535263060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 280836480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 55611059460 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 56770555335 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.981892 # Core power per rank (mW) -system.physmem_1.totalIdleTime 233423818750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 23567500 # Time in different power states -system.physmem_1.memoryStateTime::REF 91510000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 231519465750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 731339000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101377500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1173834750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912950 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702746 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186743 # Number of BTB lookups -system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689212 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249876 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13973 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95338456 # DTB read hits -system.cpu.dtb.read_misses 116 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95338572 # DTB read accesses -system.cpu.dtb.write_hits 73578378 # DTB write hits -system.cpu.dtb.write_misses 847 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73579225 # DTB write accesses -system.cpu.dtb.data_hits 168916834 # DTB hits -system.cpu.dtb.data_misses 963 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917797 # DTB accesses -system.cpu.itb.fetch_hits 96959253 # ITB hits -system.cpu.itb.fetch_misses 1239 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960492 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467282189 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664651 # Number of instructions committed -system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.172118 # CPI: cycles per instruction -system.cpu.ipc 0.853156 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction -system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction -system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction -system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::MemRead 46072315 11.56% 69.35% # Class of committed instruction -system.cpu.op_class_0::MemWrite 30396984 7.62% 76.97% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 48682195 12.21% 89.18% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 43123780 10.82% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455741730 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11540459 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.586193 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817015 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.200480 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.586193 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803610 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803610 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 335652183 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 335652183 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 94302219 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94302219 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514796 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514796 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817015 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817015 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817015 # number of overall hits -system.cpu.dcache.overall_hits::total 167817015 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5933 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5933 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6994 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6994 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6994 # number of overall misses -system.cpu.dcache.overall_misses::total 6994 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 94695000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 94695000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 540363000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 540363000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 635058000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 635058000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 635058000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 635058000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94303280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94303280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167824009 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167824009 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167824009 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167824009 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 90800.400343 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 90800.400343 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 654 # number of writebacks -system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2737 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2737 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2829 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2829 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2829 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2829 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86354000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86354000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 303749000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 303749000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 390103000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 390103000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 390103000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 390103000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3194 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.615846 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954081 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5172 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18745.955336 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.615846 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937312 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937312 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923678 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923678 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954081 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954081 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954081 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954081 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954081 # number of overall hits -system.cpu.icache.overall_hits::total 96954081 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5172 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5172 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5172 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5172 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5172 # number of overall misses -system.cpu.icache.overall_misses::total 5172 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 373067500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 373067500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 373067500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 373067500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 373067500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 373067500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959253 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959253 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959253 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959253 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72132.153906 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72132.153906 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72132.153906 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72132.153906 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3194 # number of writebacks -system.cpu.icache.writebacks::total 3194 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5172 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5172 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5172 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5172 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5172 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5172 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 367895500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 367895500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 367895500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 367895500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 367895500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 367895500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71132.153906 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71132.153906 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 7128.397001 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5429 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.689572 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.799627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.597374 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104120 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113422 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.217541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7186 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114289 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114289 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3194 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3194 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1277 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1277 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1277 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1464 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1277 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits -system.cpu.l2cache.overall_hits::total 1464 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3895 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3895 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 841 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 841 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses -system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 298441000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 298441000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 346727500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 346727500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 83414000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 83414000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 346727500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 381855000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 728582500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 346727500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 381855000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 728582500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3194 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3194 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5172 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5172 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5172 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9337 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5172 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9337 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753094 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753094 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753094 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.843204 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753094 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.843204 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95135.798534 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95135.798534 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89018.613607 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89018.613607 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99184.304400 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99184.304400 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 92541.915407 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 92541.915407 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3895 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3895 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 267071000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 267071000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307777500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307777500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 75004000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 75004000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307777500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 342075000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 649852500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307777500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 342075000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 649852500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753094 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843204 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843204 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85135.798534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85135.798534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79018.613607 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79018.613607 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89184.304400 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89184.304400 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 13302 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3965 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3194 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5172 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13538 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 843840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 9337 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 9337 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9337 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10499000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7758000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4736 # Transaction distribution -system.membus.trans_dist::ReadExReq 3137 # Transaction distribution -system.membus.trans_dist::ReadExResp 3137 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4736 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7873 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9215000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41791500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index c2a5884c8..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index 9c10deefc..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,53 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index ee5bfc401..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28057 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.050000 -Exiting @ tick 64255452000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index 54dc9e079..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1059 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.064255 # Number of seconds simulated -sim_ticks 64255452000 # Number of ticks simulated -final_tick 64255452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 443081 # Simulator instruction rate (inst/s) -host_op_rate 443081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75804731 # Simulator tick rate (ticks/s) -host_mem_usage 261252 # Number of bytes of host memory used -host_seconds 847.64 # Real time elapsed on the host -sim_insts 375574794 # Number of instructions simulated -sim_ops 375574794 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 476096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3436284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3973141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7409426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3436284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3436284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3436284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3973141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7409426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7439 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 524 # Per bank write bursts -system.physmem.perBankRdBursts::1 651 # Per bank write bursts -system.physmem.perBankRdBursts::2 450 # Per bank write bursts -system.physmem.perBankRdBursts::3 600 # Per bank write bursts -system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 454 # Per bank write bursts -system.physmem.perBankRdBursts::6 513 # Per bank write bursts -system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 438 # Per bank write bursts -system.physmem.perBankRdBursts::9 408 # Per bank write bursts -system.physmem.perBankRdBursts::10 339 # Per bank write bursts -system.physmem.perBankRdBursts::11 306 # Per bank write bursts -system.physmem.perBankRdBursts::12 414 # Per bank write bursts -system.physmem.perBankRdBursts::13 540 # Per bank write bursts -system.physmem.perBankRdBursts::14 452 # Per bank write bursts -system.physmem.perBankRdBursts::15 380 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64255349500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7439 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.644181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.715239 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.080632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 429 31.80% 31.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 311 23.05% 54.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 151 11.19% 66.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 87 6.45% 72.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 68 5.04% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.89% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.82% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 2.22% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation -system.physmem.totQLat 165053250 # Total ticks spent queuing -system.physmem.totMemAccLat 304534500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22187.56 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40937.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6085 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8637632.68 # Average gap between requests -system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5454960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2880405 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29716680 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128459760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63558420 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 5463840 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 397888500 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 152192640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15095921460 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 15881536665 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.162475 # Core power per rank (mW) -system.physmem_0.totalIdleTime 64101767750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 8572500 # Time in different power states -system.physmem_0.memoryStateTime::REF 54520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62832935750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 396328750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 90536500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 872558500 # Time in different power states -system.physmem_1.actEnergy 4212600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2239050 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 23397780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 172713840.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 67790100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10409760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 394655460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 234464640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 15065735460 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 15975618690 # Total energy per rank (pJ) -system.physmem_1.averagePower 248.626662 # Core power per rank (mW) -system.physmem_1.totalIdleTime 64079571000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 20607500 # Time in different power states -system.physmem_1.memoryStateTime::REF 73504000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 62603628000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 610590500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 81643000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 865479000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 47858833 # Number of BP lookups -system.cpu.branchPred.condPredicted 27887840 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 573531 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 23350857 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19575248 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.830962 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8687752 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1405 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2338807 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2307668 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 31139 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111329 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 98831063 # DTB read hits -system.cpu.dtb.read_misses 28342 # DTB read misses -system.cpu.dtb.read_acv 849 # DTB read access violations -system.cpu.dtb.read_accesses 98859405 # DTB read accesses -system.cpu.dtb.write_hits 75501441 # DTB write hits -system.cpu.dtb.write_misses 1449 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 75502890 # DTB write accesses -system.cpu.dtb.data_hits 174332504 # DTB hits -system.cpu.dtb.data_misses 29791 # DTB misses -system.cpu.dtb.data_acv 852 # DTB access violations -system.cpu.dtb.data_accesses 174362295 # DTB accesses -system.cpu.itb.fetch_hits 46958874 # ITB hits -system.cpu.itb.fetch_misses 432 # ITB misses -system.cpu.itb.fetch_acv 5 # ITB acv -system.cpu.itb.fetch_accesses 46959306 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 128510907 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 47429437 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 424837073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 47858833 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 30570668 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80085665 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1247776 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 297 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13295 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 46958874 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 226146 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128152674 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.315086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349633 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53168247 41.49% 41.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4330315 3.38% 44.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6713619 5.24% 50.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5107106 3.99% 54.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10970093 8.56% 62.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7524949 5.87% 68.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5303300 4.14% 72.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1847075 1.44% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33187970 25.90% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128152674 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372411 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.305844 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42097840 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13659925 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67904561 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3870622 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 619726 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 8883416 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4205 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 421920314 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 13831 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 619726 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43662514 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3075430 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 529984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70109441 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10155579 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419899923 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 443686 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2538434 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2849903 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3565226 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 273976095 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 552171720 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 393714640 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 158457079 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14443776 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37564 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15805009 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 99734698 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 76520876 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11857010 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9264279 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392184083 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 389210637 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 196187 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16609578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7664570 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128152674 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.037086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.181467 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17313559 13.51% 13.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19411245 15.15% 28.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22012922 17.18% 45.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17948678 14.01% 59.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19074074 14.88% 74.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13271943 10.36% 85.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8797733 6.87% 91.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6095055 4.76% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4227465 3.30% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128152674 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 253970 1.29% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138834 0.71% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 79013 0.40% 2.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3443745 17.54% 19.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1647907 8.39% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3789083 19.30% 47.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1973005 10.05% 57.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 5150981 26.24% 83.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3150937 16.05% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 146989472 37.77% 37.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128309 0.55% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 36418443 9.36% 47.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7355119 1.89% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2800065 0.72% 50.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556449 4.25% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584163 0.41% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 48929897 12.57% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 31583157 8.11% 75.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 50573051 12.99% 88.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 44258931 11.37% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 389210637 # Type of FU issued -system.cpu.iq.rate 3.028619 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19631071 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.050438 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 593561800 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 242185048 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 227933309 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332839406 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166679024 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158288157 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 235646895 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 173161232 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19364531 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4980212 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 92962 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 70485 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3000148 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382479 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3666 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 619726 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1854972 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162334 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 415907776 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 109026 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 99734698 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 76520876 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8920 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 152322 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 70485 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 412161 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230865 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 643026 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 387624331 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98860283 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1586306 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 23723403 # number of nop insts executed -system.cpu.iew.exec_refs 174363211 # number of memory reference insts executed -system.cpu.iew.exec_branches 45864022 # Number of branches executed -system.cpu.iew.exec_stores 75502928 # Number of stores executed -system.cpu.iew.exec_rate 3.016276 # Inst execution rate -system.cpu.iew.wb_sent 386484413 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 386221466 # cumulative count of insts written-back -system.cpu.iew.wb_producers 192314001 # num instructions producing a value -system.cpu.iew.wb_consumers 273852153 # num instructions consuming a value -system.cpu.iew.wb_rate 3.005359 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.702255 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17244606 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125687681 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.171867 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.248348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42136978 33.53% 33.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17569311 13.98% 47.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 8725420 6.94% 54.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9050963 7.20% 61.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6228783 4.96% 66.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4113989 3.27% 69.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4743327 3.77% 73.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2404790 1.91% 75.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30714120 24.44% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125687681 # Number of insts commited each cycle -system.cpu.commit.committedInsts 398664569 # Number of instructions committed -system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 168275214 # Number of memory references committed -system.cpu.commit.loads 94754486 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 44587530 # Number of branches committed -system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. -system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. -system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 141652533 35.53% 41.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 46072297 11.56% 69.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 30396955 7.62% 76.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 48682189 12.21% 89.18% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 43123773 10.82% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction -system.cpu.commit.bw_lim_events 30714120 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 510879759 # The number of ROB reads -system.cpu.rob.rob_writes 834289662 # The number of ROB writes -system.cpu.timesIdled 3136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 358233 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 375574794 # Number of Instructions Simulated -system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.342171 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.342171 # CPI: Total CPI of All Threads -system.cpu.ipc 2.922513 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.922513 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 385452576 # number of integer regfile reads -system.cpu.int_regfile_writes 165252743 # number of integer regfile writes -system.cpu.fp_regfile_reads 154537274 # number of floating regfile reads -system.cpu.fp_regfile_writes 102070951 # number of floating regfile writes -system.cpu.misc_regfile_reads 350572 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 774 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.451205 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 152580730 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36555.038333 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.451205 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803577 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803577 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 305207642 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 305207642 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 79079190 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79079190 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501534 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501534 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 152580724 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152580724 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152580724 # number of overall hits -system.cpu.dcache.overall_hits::total 152580724 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19194 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19194 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21004 # number of overall misses -system.cpu.dcache.overall_misses::total 21004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 137671000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 137671000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1331646003 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1331646003 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1469317003 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1469317003 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1469317003 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1469317003 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79081000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79081000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 152601728 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 152601728 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 152601728 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 152601728 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76061.325967 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76061.325967 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69378.243357 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69378.243357 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69954.151733 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69954.151733 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 57813 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 689 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.908563 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 94 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16830 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16830 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16830 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16830 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 83512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 83512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 299984000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 299984000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 383496000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 383496000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 383496000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 383496000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84697.768763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84697.768763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94097.867001 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94097.867001 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91877.335889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 91877.335889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91877.335889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 91877.335889 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2132 # number of replacements -system.cpu.icache.tags.tagsinuse 1829.599220 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 46953196 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4059 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11567.675782 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1829.599220 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.893359 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.893359 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1342 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 93921805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 93921805 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 46953196 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 46953196 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 46953196 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 46953196 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 46953196 # number of overall hits -system.cpu.icache.overall_hits::total 46953196 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5677 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5677 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5677 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5677 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5677 # number of overall misses -system.cpu.icache.overall_misses::total 5677 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 436957499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 436957499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 436957499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 436957499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 436957499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 436957499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 46958873 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 46958873 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 46958873 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 46958873 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 46958873 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 46958873 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000121 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76969.790206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76969.790206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76969.790206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76969.790206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76969.790206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76969.790206 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 896 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.733333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2132 # number of writebacks -system.cpu.icache.writebacks::total 2132 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1618 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1618 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1618 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1618 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1618 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1618 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4059 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4059 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4059 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4059 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4059 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4059 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323146500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 323146500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323146500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 323146500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323146500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 323146500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79612.342942 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79612.342942 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79612.342942 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79612.342942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79612.342942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79612.342942 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6685.408988 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3700 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7439 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.497379 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2964.630490 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.778498 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090473 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113549 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.204022 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7439 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6755 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.227020 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 96551 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 96551 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2132 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 125 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 125 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 609 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 185 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 794 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 609 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 185 # number of overall hits -system.cpu.l2cache.overall_hits::total 794 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 3128 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3128 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3450 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3450 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 861 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 861 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3450 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3989 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3450 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses -system.cpu.l2cache.overall_misses::total 7439 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 294472000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 294472000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 310569500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 310569500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 80627500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 80627500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 310569500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 375099500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 685669000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 310569500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 375099500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 685669000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 655 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 655 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2132 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2132 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4059 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4059 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 986 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 986 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4059 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8233 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4059 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8233 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981179 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.981179 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.849963 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.849963 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.873225 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.873225 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849963 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955678 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.903559 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849963 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955678 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.903559 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94140.664962 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94140.664962 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 90020.144928 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 90020.144928 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93644.018583 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93644.018583 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 90020.144928 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94033.467034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 92172.200565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 90020.144928 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94033.467034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 92172.200565 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3128 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3128 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3450 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3450 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 861 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 861 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7439 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 263192000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 263192000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 276069500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 276069500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 72017500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72017500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 276069500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335209500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 611279000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 276069500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335209500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 611279000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849963 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.873225 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.873225 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903559 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903559 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84140.664962 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84140.664962 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80020.144928 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80020.144928 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83644.018583 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83644.018583 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 11139 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2906 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 119 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4059 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 986 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9122 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19372 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 705280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 8233 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8233 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8233 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8356500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6088500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6261000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4311 # Transaction distribution -system.membus.trans_dist::ReadExReq 3128 # Transaction distribution -system.membus.trans_dist::ReadExResp 3128 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4311 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14878 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 476096 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7439 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7439 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7439 # Request fanout histogram -system.membus.reqLayer0.occupancy 9229500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39165500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index 7b7341967..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 870cfd899..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,52 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index 1c6cb75e4..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4302 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.566667 -Exiting @ tick 567385356500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 6d86d3450..000000000 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,555 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.567393 # Number of seconds simulated -sim_ticks 567392530500 # Number of ticks simulated -final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1833225 # Simulator instruction rate (inst/s) -host_op_rate 1833225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2609105944 # Simulator tick rate (ticks/s) -host_mem_usage 258692 # Number of bytes of host memory used -host_seconds 217.47 # Real time elapsed on the host -sim_insts 398664609 # Number of instructions simulated -sim_ops 398664609 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory -system.physmem.bytes_read::total 459136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754490 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754511 # DTB read accesses -system.cpu.dtb.write_hits 73520730 # DTB write hits -system.cpu.dtb.write_misses 35 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73520765 # DTB write accesses -system.cpu.dtb.data_hits 168275220 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275276 # DTB accesses -system.cpu.itb.fetch_hits 398664666 # ITB hits -system.cpu.itb.fetch_misses 173 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398664839 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1134785061 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664609 # Number of instructions committed -system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses -system.cpu.num_func_calls 16015498 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls -system.cpu.num_int_insts 316365921 # number of integer instructions -system.cpu.num_fp_insts 155295119 # number of float instructions -system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read -system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written -system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read -system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written -system.cpu.num_mem_refs 168275276 # number of memory refs -system.cpu.num_load_insts 94754511 # Number of load instructions -system.cpu.num_store_insts 73520765 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134785061 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 44587535 # Number of branches fetched -system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction -system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction -system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction -system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction -system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 46072316 11.56% 69.35% # Class of executed instruction -system.cpu.op_class::MemWrite 30396985 7.62% 76.97% # Class of executed instruction -system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 398664665 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits -system.cpu.dcache.overall_hits::total 168271068 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses -system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 649 # number of writebacks -system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses -system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits -system.cpu.icache.overall_hits::total 398660993 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses -system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1769 # number of writebacks -system.cpu.icache.writebacks::total 1769 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits -system.cpu.l2cache.overall_hits::total 651 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses -system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4032 # Transaction distribution -system.membus.trans_dist::ReadExReq 3142 # Transaction distribution -system.membus.trans_dist::ReadExResp 3142 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7174 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 1dc6d91c8..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index 8954fa36f..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,8 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index c97afb693..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28059 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 -592000: 2038558826 -591000: 3948772976 -590000: 439262378 -589000: 329537197 -588000: 3678661972 -587000: 4240182727 -586000: 2283602206 -585000: 1129811410 -584000: 2831949168 -583000: 1224559023 -582000: 3161562107 -581000: 2695467835 -580000: 1234192577 -579000: 1974816198 -578000: 449576701 -577000: 1424873035 -576000: 2370444290 -575000: 1743089134 -574000: 2624046998 -573000: 2071148441 -572000: 2449219691 -571000: 3774476172 -570000: 1111630327 -569000: 121721805 -568000: 2981212266 -567000: 3811833647 -566000: 3676851843 -565000: 1766252334 -564000: 1622887950 -563000: 1684409857 -562000: 1686489387 -561000: 610219569 -560000: 2705092362 -559000: 108031723 -558000: 1316736987 -557000: 2434129258 -556000: 1411819652 -555000: 1173886179 -554000: 3044539233 -553000: 151590417 -552000: 3759426289 -551000: 3451520306 -550000: 294242855 -549000: 890241051 -548000: 876385779 -547000: 119864600 -546000: 3065674956 -545000: 1670853168 -544000: 997261561 -543000: 660227344 -542000: 3132294889 -541000: 521956271 -540000: 1133928405 -539000: 3838154786 -538000: 58624572 -537000: 3544030439 -536000: 432804999 -535000: 1021857051 -534000: 2644812356 -533000: 773094580 -532000: 901027171 -531000: 3976696839 -530000: 4167278216 -529000: 504481120 -528000: 320399857 -527000: 638048690 -526000: 3348998474 -525000: 2660662065 -524000: 2641437803 -523000: 626927006 -522000: 4063917554 -521000: 3212249308 -520000: 2561025301 -519000: 1078140141 -518000: 653939181 -517000: 2154098204 -516000: 3773089676 -515000: 2568381435 -514000: 3838886937 -513000: 941125346 -512000: 1318900410 -511000: 297013287 -510000: 241723934 -509000: 1835499795 -508000: 2309451230 -507000: 1174814430 -506000: 3615943386 -505000: 51034971 -504000: 3950453295 -503000: 4186097241 -502000: 327518343 -501000: 3052462710 -500000: 1586937404 -499000: 2169094819 -498000: 3613195151 -497000: 817359591 -496000: 1470916579 -495000: 2091261583 -494000: 2080080890 -493000: 1772858697 -492000: 2085609872 -491000: 3280632925 -490000: 1689322569 -489000: 2947406469 -488000: 765163324 -487000: 3122594732 -486000: 3385418480 -485000: 1712345567 -484000: 3675825158 -483000: 1558929764 -482000: 2672493410 -481000: 3822528440 -480000: 3741769935 -479000: 2794026235 -478000: 2541364185 -477000: 3964482316 -476000: 1202478165 -475000: 4027617791 -474000: 1905026738 -473000: 2573787636 -472000: 1170529797 -471000: 2272525618 -470000: 820833429 -469000: 3219769529 -468000: 2121197441 -467000: 269331764 -466000: 3038487237 -465000: 2462675338 -464000: 2703163101 -463000: 547052037 -462000: 3454526671 -461000: 2124641794 -460000: 1043737466 -459000: 1785834964 -458000: 3312335313 -457000: 1213835042 -456000: 3099430685 -455000: 3003350806 -454000: 3646781335 -453000: 1474165966 -452000: 705795987 -451000: 2723908407 -450000: 1323056304 -449000: 1157256530 -448000: 4077983523 -447000: 3189085703 -446000: 2241002747 -445000: 3229050072 -444000: 3500150226 -443000: 1290722604 -442000: 1866107725 -441000: 4238277470 -440000: 847346408 -439000: 2474557496 -438000: 2243092317 -437000: 706909230 -436000: 1303503693 -435000: 1456129560 -434000: 1073061079 -433000: 692226634 -432000: 186498656 -431000: 2203415525 -430000: 2183000701 -429000: 1007776545 -428000: 941117387 -427000: 3805851413 -426000: 1474193180 -425000: 4231673903 -424000: 2622576664 -423000: 388097625 -422000: 1165097488 -421000: 3226044518 -420000: 2531461570 -419000: 1509806310 -418000: 2667519114 -417000: 1751592438 -416000: 1286773513 -415000: 1098182293 -414000: 2111912709 -413000: 1230737431 -412000: 4090873946 -411000: 3998652133 -410000: 2486660396 -409000: 2120483596 -408000: 587404533 -407000: 188697995 -406000: 3265346093 -405000: 4234961905 -404000: 1211873901 -403000: 4265173305 -402000: 2208355316 -401000: 3315952806 -400000: 3917328941 -399000: 2523594649 -398000: 3805986783 -397000: 2624925960 -396000: 3716020189 -395000: 2016201122 -394000: 912930261 -393000: 596904160 -392000: 3571173642 -391000: 2290782861 -390000: 1162492227 -389000: 1738718380 -388000: 2599667355 -387000: 2382332909 -386000: 1471269037 -385000: 2238392684 -384000: 4034826126 -383000: 1378654892 -382000: 3702601850 -381000: 397206179 -380000: 2437704230 -379000: 4187604139 -378000: 779452169 -377000: 2010372403 -376000: 531902409 -375000: 1371470602 -374000: 4137796987 -373000: 567426549 -372000: 3082742955 -371000: 2271575596 -370000: 759731212 -369000: 4063369437 -368000: 299356452 -367000: 536656228 -366000: 3014961694 -365000: 3016542135 -364000: 2841873124 -363000: 524434057 -362000: 2887828889 -361000: 3865529589 -360000: 671363647 -359000: 3104594256 -358000: 1502485940 -357000: 1776624159 -356000: 4222478488 -355000: 4127624139 -354000: 2439477793 -353000: 1593794891 -352000: 591275342 -351000: 2177291538 -350000: 1923444781 -349000: 758084193 -348000: 775471359 -347000: 191356974 -346000: 494488375 -345000: 1990489399 -344000: 124118372 -343000: 2046377904 -342000: 1395427716 -341000: 1342299790 -340000: 38145994 -339000: 2291884417 -338000: 351940574 -337000: 3984301480 -336000: 2468666235 -335000: 371500747 -334000: 969922131 -333000: 240854580 -332000: 1644465214 -331000: 1539846168 -330000: 940087216 -329000: 1491329232 -328000: 2281687201 -327000: 3030170550 -326000: 3648503863 -325000: 2037898355 -324000: 174369956 -323000: 2433605668 -322000: 2334905107 -321000: 1597704047 -320000: 302297707 -319000: 3209203690 -318000: 3894539879 -317000: 2868907580 -316000: 2808087076 -315000: 4034586233 -314000: 3694191694 -313000: 2001671958 -312000: 559582279 -311000: 3043016195 -310000: 2785098502 -309000: 4104602138 -308000: 966154914 -307000: 2446376687 -306000: 789956605 -305000: 1708137092 -304000: 1733063901 -303000: 2924555399 -302000: 971356234 -301000: 481382543 -300000: 2647080988 -299000: 4065744916 -298000: 921140 -297000: 654346784 -296000: 485492098 -295000: 217516816 -294000: 4050820137 -293000: 534726686 -292000: 1686691079 -291000: 1316587195 -290000: 3746020838 -289000: 1641967381 -288000: 3492475215 -287000: 3154885393 -286000: 3686450617 -285000: 3589739293 -284000: 3558041700 -283000: 4130142319 -282000: 3132446063 -281000: 982677436 -280000: 799322395 -279000: 151715214 -278000: 3765942871 -277000: 1712470933 -276000: 3807622752 -275000: 4163730108 -274000: 1633425299 -273000: 1654241631 -272000: 1131025394 -271000: 1375475855 -270000: 553294237 -269000: 4091487177 -268000: 2841855980 -267000: 2997369904 -266000: 454385594 -265000: 3757482634 -264000: 3856197465 -263000: 1084605457 -262000: 2552759023 -261000: 3786548799 -260000: 272762545 -259000: 2670277860 -258000: 76233700 -257000: 476168167 -256000: 8969192 -255000: 1998841030 -254000: 1240074303 -253000: 1771564446 -252000: 710374418 -251000: 821383716 -250000: 3157726088 -249000: 3083379502 -248000: 2563632690 -247000: 33723341 -246000: 3303336748 -245000: 4110677892 -244000: 3811702913 -243000: 53856215 -242000: 243571468 -241000: 52177779 -240000: 46805590 -239000: 1622010618 -238000: 1321640849 -237000: 3106837291 -236000: 4102944642 -235000: 137904396 -234000: 339510135 -233000: 88415957 -232000: 3157666382 -231000: 2571005912 -230000: 3586247649 -229000: 4172761781 -228000: 2463305780 -227000: 956927307 -226000: 2169861547 -225000: 1751989251 -224000: 673059158 -223000: 2782464516 -222000: 3741392140 -221000: 2856154963 -220000: 3778376854 -219000: 1538476717 -218000: 2879698522 -217000: 3734645735 -216000: 1899042577 -215000: 371356008 -214000: 2416663698 -213000: 1595919347 -212000: 2816045438 -211000: 132438808 -210000: 1098603890 -209000: 834913667 -208000: 2707567283 -207000: 3154122448 -206000: 3696516104 -205000: 1427952551 -204000: 280496321 -203000: 1185678745 -202000: 3461951699 -201000: 1369208434 -200000: 3900136261 -199000: 870818876 -198000: 327248310 -197000: 3116959470 -196000: 1544241188 -195000: 1568248814 -194000: 2978831302 -193000: 205660429 -192000: 1704239501 -191000: 3570135474 -190000: 3878512103 -189000: 1212729210 -188000: 1873588815 -187000: 324853813 -186000: 432676298 -185000: 1641364437 -184000: 1568401301 -183000: 525792402 -182000: 861154382 -181000: 2357325066 -180000: 3626762590 -179000: 4172125462 -178000: 2108738993 -177000: 2084782857 -176000: 3956924509 -175000: 17183073 -174000: 3676839474 -173000: 458250029 -172000: 2635215219 -171000: 1801029767 -170000: 3602628987 -169000: 370704281 -168000: 177963345 -167000: 924067814 -166000: 3577678376 -165000: 3717789117 -164000: 3285809386 -163000: 3738962897 -162000: 3172510171 -161000: 417992786 -160000: 2591600214 -159000: 3315096579 -158000: 3590763949 -157000: 198872871 -156000: 2960653534 -155000: 2246563682 -154000: 2304045306 -153000: 2647353543 -152000: 2043381015 -151000: 3952056867 -150000: 2644058641 -149000: 3477151018 -148000: 1740210241 -147000: 3314851112 -146000: 1604832482 -145000: 2572410736 -144000: 1965059167 -143000: 889666293 -142000: 1024747903 -141000: 226685285 -140000: 3149168519 -139000: 403638872 -138000: 1725889104 -137000: 1417402331 -136000: 422304488 -135000: 2595894054 -134000: 4266597695 -133000: 1116326556 -132000: 3537080833 -131000: 2181246909 -130000: 1241997223 -129000: 628191304 -128000: 3074132403 -127000: 2112958836 -126000: 1371260930 -125000: 2272975771 -124000: 1379085607 -123000: 1998991877 -122000: 2760271255 -121000: 3784187756 -120000: 311188417 -119000: 1123593459 -118000: 1249155194 -117000: 908703020 -116000: 3765244393 -115000: 3040869794 -114000: 437536659 -113000: 3343598822 -112000: 2419089776 -111000: 1263143640 -110000: 1384687523 -109000: 1727931349 -108000: 2861733388 -107000: 963829093 -106000: 431354627 -105000: 3568623360 -104000: 2957399361 -103000: 1071045618 -102000: 3968457714 -101000: 3448338394 -100000: 2586060251 -99000: 3401651822 -98000: 1579089478 -97000: 3722618916 -96000: 759319595 -95000: 1269278712 -94000: 150489448 -93000: 390013662 -92000: 3663029784 -91000: 555197170 -90000: 166476858 -89000: 1658807720 -88000: 3430520531 -87000: 2946861093 -86000: 3000600326 -85000: 300034452 -84000: 2813719249 -83000: 3009927425 -82000: 1127728469 -81000: 2667791855 -80000: 2632316050 -79000: 2180301200 -78000: 418999983 -77000: 4254858933 -76000: 2728734498 -75000: 1863202698 -74000: 4226419921 -73000: 1917572494 -72000: 3117082625 -71000: 1032601538 -70000: 2992135524 -69000: 670119660 -68000: 638731522 -67000: 1460114012 -66000: 1232274665 -65000: 3667669961 -64000: 191277965 -63000: 3868442802 -62000: 700664540 -61000: 2271087482 -60000: 3274078227 -59000: 159900296 -58000: 2778747772 -57000: 2788477153 -56000: 3965957780 -55000: 2276993918 -54000: 1986966104 -53000: 3416414682 -52000: 2162594060 -51000: 2947744069 -50000: 4024793290 -49000: 631161701 -48000: 728285173 -47000: 1487641693 -46000: 4049519424 -45000: 613160608 -44000: 1566126172 -43000: 3731725133 -42000: 2746368727 -41000: 4168967735 -40000: 1319649932 -39000: 2964978784 -38000: 967937134 -37000: 3116555742 -36000: 2279790642 -35000: 2852914953 -34000: 1040410911 -33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 521167228000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 42592acc9..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,829 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.521167 # Number of seconds simulated -sim_ticks 521167228000 # Number of ticks simulated -final_tick 521167228000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 492017 # Simulator instruction rate (inst/s) -host_op_rate 492017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 276083455 # Simulator tick rate (ticks/s) -host_mem_usage 263220 # Number of bytes of host memory used -host_seconds 1887.72 # Real time elapsed on the host -sim_insts 928789150 # Number of instructions simulated -sim_ops 928789150 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 356861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35537338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35894199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 356861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 356861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8188757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8188757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8188757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 356861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35537338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44082956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292295 # Number of read requests accepted -system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292295 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18686976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18028 # Per bank write bursts -system.physmem.perBankRdBursts::1 18369 # Per bank write bursts -system.physmem.perBankRdBursts::2 18396 # Per bank write bursts -system.physmem.perBankRdBursts::3 18341 # Per bank write bursts -system.physmem.perBankRdBursts::4 18255 # Per bank write bursts -system.physmem.perBankRdBursts::5 18258 # Per bank write bursts -system.physmem.perBankRdBursts::6 18325 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18235 # Per bank write bursts -system.physmem.perBankRdBursts::10 18232 # Per bank write bursts -system.physmem.perBankRdBursts::11 18375 # Per bank write bursts -system.physmem.perBankRdBursts::12 18268 # Per bank write bursts -system.physmem.perBankRdBursts::13 18134 # Per bank write bursts -system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18187 # Per bank write bursts -system.physmem.perBankWrBursts::0 4123 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4221 # Per bank write bursts -system.physmem.perBankWrBursts::3 4157 # Per bank write bursts -system.physmem.perBankWrBursts::4 4141 # Per bank write bursts -system.physmem.perBankWrBursts::5 4097 # Per bank write bursts -system.physmem.perBankWrBursts::6 4260 # Per bank write bursts -system.physmem.perBankWrBursts::7 4224 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4192 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 521167139500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292295 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.106731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.105135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 271.560992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28950 30.16% 30.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41784 43.53% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11694 12.18% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2599 2.71% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 913 0.95% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 756 0.79% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 331 0.34% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 447 0.47% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8515 8.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95989 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.753823 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.637200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 730.740597 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.441539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.421503 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.829633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3159 77.92% 77.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 895 22.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads -system.physmem.totQLat 15194551500 # Total ticks spent queuing -system.physmem.totMemAccLat 20669251500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 52038.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70788.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 35.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 35.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.19 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.34 # Data bus utilization in percentage -system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 210474 # Number of row buffer hits during reads -system.physmem.writeRowHits 52167 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes -system.physmem.avgGap 1451808.02 # Average gap between requests -system.physmem.pageHitRate 73.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341770380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 181632495 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1044360660 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174280140 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 28691395200.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8105258640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1605839040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 57337999170 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 51043667520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 64046185080 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 212592411075 # Total energy per rank (pJ) -system.physmem_0.averagePower 407.915916 # Core power per rank (mW) -system.physmem_0.totalIdleTime 499165974500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3167480750 # Time in different power states -system.physmem_0.memoryStateTime::REF 12206580000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 240498579500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 132926079750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6626927000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 125741581000 # Time in different power states -system.physmem_1.actEnergy 343648200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 182645760 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1040405100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 173653740 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 28803874320.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8196268830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616284320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 57528037740 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 51141308640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 63870409695 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 212914803135 # Total energy per rank (pJ) -system.physmem_1.averagePower 408.534516 # Core power per rank (mW) -system.physmem_1.totalIdleTime 498942805750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3183963500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12254448000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 239604631750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 133180372750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6785962500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 126157849500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851675 # Number of BP lookups -system.cpu.branchPred.condPredicted 79872959 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 686742 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066154 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190152 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.809759 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697401 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 11223 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14052181 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14048615 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3566 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11656 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237539296 # DTB read hits -system.cpu.dtb.read_misses 195211 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305023 # DTB write hits -system.cpu.dtb.write_misses 7170 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312193 # DTB write accesses -system.cpu.dtb.data_hits 335844319 # DTB hits -system.cpu.dtb.data_misses 202381 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046700 # DTB accesses -system.cpu.itb.fetch_hits 286584578 # ITB hits -system.cpu.itb.fetch_misses 119 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584697 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1042334456 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928789150 # Number of instructions committed -system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319598 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.122251 # CPI: cycles per instruction -system.cpu.ipc 0.891066 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction -system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::MemRead 228135214 24.56% 88.39% # Class of committed instruction -system.cpu.op_class_0::MemWrite 94471145 10.17% 98.56% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 9570033 1.03% 99.59% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 3836926 0.41% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962817000 # Number of cycles that the object actually ticked -system.cpu.idleCycles 79517456 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.209717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318705 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320442 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 968708500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.209717 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999075 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999075 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 957 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115675 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115675 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164048 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164048 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318705 # number of overall hits -system.cpu.dcache.overall_hits::total 320318705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137152 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137152 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 848805 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 848805 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 848805 # number of overall misses -system.cpu.dcache.overall_misses::total 848805 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36922839000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36922839000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10957317000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10957317000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 47880156000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 47880156000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 47880156000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 47880156000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167510 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167510 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167510 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167510 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51883.205720 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51883.205720 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79891.777007 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79891.777007 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56408.899571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56408.899571 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks -system.cpu.dcache.writebacks::total 88440 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68141 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68141 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68150 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68150 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68150 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68150 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711644 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711644 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780655 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36210490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36210490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5501688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5501688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41712178500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41712178500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41712178500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41712178500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50882.871913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50882.871913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79721.899407 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79721.899407 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10581 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.101724 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572250 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12327 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23247.525756 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1690.101724 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825245 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825245 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181483 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181483 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572250 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572250 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572250 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286572250 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286572250 # number of overall hits -system.cpu.icache.overall_hits::total 286572250 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12328 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12328 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12328 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12328 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12328 # number of overall misses -system.cpu.icache.overall_misses::total 12328 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 376885500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 376885500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 376885500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 376885500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 376885500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 376885500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286584578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286584578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286584578 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286584578 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286584578 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286584578 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30571.503894 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30571.503894 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30571.503894 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30571.503894 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10581 # number of writebacks -system.cpu.icache.writebacks::total 10581 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12328 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12328 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12328 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 364558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 364558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 364558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 364558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 364558500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 364558500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29571.585010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29571.585010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259984 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32658.667775 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1287369 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292752 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.397473 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 3857784000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51.730334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.865838 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32527.071603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001579 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002437 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.992647 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996663 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2875 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12933736 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12933736 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88440 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88440 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10581 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10581 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488900 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488900 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9421 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491266 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 500687 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9421 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491266 # number of overall hits -system.cpu.l2cache.overall_hits::total 500687 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2907 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2907 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222744 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222744 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289389 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292296 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2907 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289389 # number of overall misses -system.cpu.l2cache.overall_misses::total 292296 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5373301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5373301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 247147500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 247147500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30009565500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30009565500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 247147500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35382867000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35630014500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 247147500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35382867000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35630014500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88440 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88440 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10581 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10581 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12328 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12328 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12328 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780655 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792983 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12328 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792983 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312999 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312999 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.368603 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.368603 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80625.725861 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80625.725861 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85018.059856 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85018.059856 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134726.706443 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134726.706443 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 121897.030750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 121897.030750 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292296 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4706851500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4706851500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 218087500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 218087500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27782125500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27782125500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218087500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32488977000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32707064500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218087500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32488977000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32707064500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368603 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368603 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70625.725861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70625.725861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75021.499828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75021.499828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124726.706443 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124726.706443 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580123 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787140 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1466112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57088192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259984 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052967 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001991 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044571 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050871 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2096 0.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052967 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889082500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18490500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170982500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 550183 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257888 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225650 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191205 # Transaction distribution -system.membus.trans_dist::ReadExReq 66645 # Transaction distribution -system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225650 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842478 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22974592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292295 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292295 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292295 # Request fanout histogram -system.membus.reqLayer0.occupancy 925387500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1555624500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index 49d14f26b..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index 8954fa36f..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,8 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 2bef733aa..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28086 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 -592000: 2038558826 -591000: 3948772976 -590000: 439262378 -589000: 329537197 -588000: 3678661972 -587000: 4240182727 -586000: 2283602206 -585000: 1129811410 -584000: 2831949168 -583000: 1224559023 -582000: 3161562107 -581000: 2695467835 -580000: 1234192577 -579000: 1974816198 -578000: 449576701 -577000: 1424873035 -576000: 2370444290 -575000: 1743089134 -574000: 2624046998 -573000: 2071148441 -572000: 2449219691 -571000: 3774476172 -570000: 1111630327 -569000: 121721805 -568000: 2981212266 -567000: 3811833647 -566000: 3676851843 -565000: 1766252334 -564000: 1622887950 -563000: 1684409857 -562000: 1686489387 -561000: 610219569 -560000: 2705092362 -559000: 108031723 -558000: 1316736987 -557000: 2434129258 -556000: 1411819652 -555000: 1173886179 -554000: 3044539233 -553000: 151590417 -552000: 3759426289 -551000: 3451520306 -550000: 294242855 -549000: 890241051 -548000: 876385779 -547000: 119864600 -546000: 3065674956 -545000: 1670853168 -544000: 997261561 -543000: 660227344 -542000: 3132294889 -541000: 521956271 -540000: 1133928405 -539000: 3838154786 -538000: 58624572 -537000: 3544030439 -536000: 432804999 -535000: 1021857051 -534000: 2644812356 -533000: 773094580 -532000: 901027171 -531000: 3976696839 -530000: 4167278216 -529000: 504481120 -528000: 320399857 -527000: 638048690 -526000: 3348998474 -525000: 2660662065 -524000: 2641437803 -523000: 626927006 -522000: 4063917554 -521000: 3212249308 -520000: 2561025301 -519000: 1078140141 -518000: 653939181 -517000: 2154098204 -516000: 3773089676 -515000: 2568381435 -514000: 3838886937 -513000: 941125346 -512000: 1318900410 -511000: 297013287 -510000: 241723934 -509000: 1835499795 -508000: 2309451230 -507000: 1174814430 -506000: 3615943386 -505000: 51034971 -504000: 3950453295 -503000: 4186097241 -502000: 327518343 -501000: 3052462710 -500000: 1586937404 -499000: 2169094819 -498000: 3613195151 -497000: 817359591 -496000: 1470916579 -495000: 2091261583 -494000: 2080080890 -493000: 1772858697 -492000: 2085609872 -491000: 3280632925 -490000: 1689322569 -489000: 2947406469 -488000: 765163324 -487000: 3122594732 -486000: 3385418480 -485000: 1712345567 -484000: 3675825158 -483000: 1558929764 -482000: 2672493410 -481000: 3822528440 -480000: 3741769935 -479000: 2794026235 -478000: 2541364185 -477000: 3964482316 -476000: 1202478165 -475000: 4027617791 -474000: 1905026738 -473000: 2573787636 -472000: 1170529797 -471000: 2272525618 -470000: 820833429 -469000: 3219769529 -468000: 2121197441 -467000: 269331764 -466000: 3038487237 -465000: 2462675338 -464000: 2703163101 -463000: 547052037 -462000: 3454526671 -461000: 2124641794 -460000: 1043737466 -459000: 1785834964 -458000: 3312335313 -457000: 1213835042 -456000: 3099430685 -455000: 3003350806 -454000: 3646781335 -453000: 1474165966 -452000: 705795987 -451000: 2723908407 -450000: 1323056304 -449000: 1157256530 -448000: 4077983523 -447000: 3189085703 -446000: 2241002747 -445000: 3229050072 -444000: 3500150226 -443000: 1290722604 -442000: 1866107725 -441000: 4238277470 -440000: 847346408 -439000: 2474557496 -438000: 2243092317 -437000: 706909230 -436000: 1303503693 -435000: 1456129560 -434000: 1073061079 -433000: 692226634 -432000: 186498656 -431000: 2203415525 -430000: 2183000701 -429000: 1007776545 -428000: 941117387 -427000: 3805851413 -426000: 1474193180 -425000: 4231673903 -424000: 2622576664 -423000: 388097625 -422000: 1165097488 -421000: 3226044518 -420000: 2531461570 -419000: 1509806310 -418000: 2667519114 -417000: 1751592438 -416000: 1286773513 -415000: 1098182293 -414000: 2111912709 -413000: 1230737431 -412000: 4090873946 -411000: 3998652133 -410000: 2486660396 -409000: 2120483596 -408000: 587404533 -407000: 188697995 -406000: 3265346093 -405000: 4234961905 -404000: 1211873901 -403000: 4265173305 -402000: 2208355316 -401000: 3315952806 -400000: 3917328941 -399000: 2523594649 -398000: 3805986783 -397000: 2624925960 -396000: 3716020189 -395000: 2016201122 -394000: 912930261 -393000: 596904160 -392000: 3571173642 -391000: 2290782861 -390000: 1162492227 -389000: 1738718380 -388000: 2599667355 -387000: 2382332909 -386000: 1471269037 -385000: 2238392684 -384000: 4034826126 -383000: 1378654892 -382000: 3702601850 -381000: 397206179 -380000: 2437704230 -379000: 4187604139 -378000: 779452169 -377000: 2010372403 -376000: 531902409 -375000: 1371470602 -374000: 4137796987 -373000: 567426549 -372000: 3082742955 -371000: 2271575596 -370000: 759731212 -369000: 4063369437 -368000: 299356452 -367000: 536656228 -366000: 3014961694 -365000: 3016542135 -364000: 2841873124 -363000: 524434057 -362000: 2887828889 -361000: 3865529589 -360000: 671363647 -359000: 3104594256 -358000: 1502485940 -357000: 1776624159 -356000: 4222478488 -355000: 4127624139 -354000: 2439477793 -353000: 1593794891 -352000: 591275342 -351000: 2177291538 -350000: 1923444781 -349000: 758084193 -348000: 775471359 -347000: 191356974 -346000: 494488375 -345000: 1990489399 -344000: 124118372 -343000: 2046377904 -342000: 1395427716 -341000: 1342299790 -340000: 38145994 -339000: 2291884417 -338000: 351940574 -337000: 3984301480 -336000: 2468666235 -335000: 371500747 -334000: 969922131 -333000: 240854580 -332000: 1644465214 -331000: 1539846168 -330000: 940087216 -329000: 1491329232 -328000: 2281687201 -327000: 3030170550 -326000: 3648503863 -325000: 2037898355 -324000: 174369956 -323000: 2433605668 -322000: 2334905107 -321000: 1597704047 -320000: 302297707 -319000: 3209203690 -318000: 3894539879 -317000: 2868907580 -316000: 2808087076 -315000: 4034586233 -314000: 3694191694 -313000: 2001671958 -312000: 559582279 -311000: 3043016195 -310000: 2785098502 -309000: 4104602138 -308000: 966154914 -307000: 2446376687 -306000: 789956605 -305000: 1708137092 -304000: 1733063901 -303000: 2924555399 -302000: 971356234 -301000: 481382543 -300000: 2647080988 -299000: 4065744916 -298000: 921140 -297000: 654346784 -296000: 485492098 -295000: 217516816 -294000: 4050820137 -293000: 534726686 -292000: 1686691079 -291000: 1316587195 -290000: 3746020838 -289000: 1641967381 -288000: 3492475215 -287000: 3154885393 -286000: 3686450617 -285000: 3589739293 -284000: 3558041700 -283000: 4130142319 -282000: 3132446063 -281000: 982677436 -280000: 799322395 -279000: 151715214 -278000: 3765942871 -277000: 1712470933 -276000: 3807622752 -275000: 4163730108 -274000: 1633425299 -273000: 1654241631 -272000: 1131025394 -271000: 1375475855 -270000: 553294237 -269000: 4091487177 -268000: 2841855980 -267000: 2997369904 -266000: 454385594 -265000: 3757482634 -264000: 3856197465 -263000: 1084605457 -262000: 2552759023 -261000: 3786548799 -260000: 272762545 -259000: 2670277860 -258000: 76233700 -257000: 476168167 -256000: 8969192 -255000: 1998841030 -254000: 1240074303 -253000: 1771564446 -252000: 710374418 -251000: 821383716 -250000: 3157726088 -249000: 3083379502 -248000: 2563632690 -247000: 33723341 -246000: 3303336748 -245000: 4110677892 -244000: 3811702913 -243000: 53856215 -242000: 243571468 -241000: 52177779 -240000: 46805590 -239000: 1622010618 -238000: 1321640849 -237000: 3106837291 -236000: 4102944642 -235000: 137904396 -234000: 339510135 -233000: 88415957 -232000: 3157666382 -231000: 2571005912 -230000: 3586247649 -229000: 4172761781 -228000: 2463305780 -227000: 956927307 -226000: 2169861547 -225000: 1751989251 -224000: 673059158 -223000: 2782464516 -222000: 3741392140 -221000: 2856154963 -220000: 3778376854 -219000: 1538476717 -218000: 2879698522 -217000: 3734645735 -216000: 1899042577 -215000: 371356008 -214000: 2416663698 -213000: 1595919347 -212000: 2816045438 -211000: 132438808 -210000: 1098603890 -209000: 834913667 -208000: 2707567283 -207000: 3154122448 -206000: 3696516104 -205000: 1427952551 -204000: 280496321 -203000: 1185678745 -202000: 3461951699 -201000: 1369208434 -200000: 3900136261 -199000: 870818876 -198000: 327248310 -197000: 3116959470 -196000: 1544241188 -195000: 1568248814 -194000: 2978831302 -193000: 205660429 -192000: 1704239501 -191000: 3570135474 -190000: 3878512103 -189000: 1212729210 -188000: 1873588815 -187000: 324853813 -186000: 432676298 -185000: 1641364437 -184000: 1568401301 -183000: 525792402 -182000: 861154382 -181000: 2357325066 -180000: 3626762590 -179000: 4172125462 -178000: 2108738993 -177000: 2084782857 -176000: 3956924509 -175000: 17183073 -174000: 3676839474 -173000: 458250029 -172000: 2635215219 -171000: 1801029767 -170000: 3602628987 -169000: 370704281 -168000: 177963345 -167000: 924067814 -166000: 3577678376 -165000: 3717789117 -164000: 3285809386 -163000: 3738962897 -162000: 3172510171 -161000: 417992786 -160000: 2591600214 -159000: 3315096579 -158000: 3590763949 -157000: 198872871 -156000: 2960653534 -155000: 2246563682 -154000: 2304045306 -153000: 2647353543 -152000: 2043381015 -151000: 3952056867 -150000: 2644058641 -149000: 3477151018 -148000: 1740210241 -147000: 3314851112 -146000: 1604832482 -145000: 2572410736 -144000: 1965059167 -143000: 889666293 -142000: 1024747903 -141000: 226685285 -140000: 3149168519 -139000: 403638872 -138000: 1725889104 -137000: 1417402331 -136000: 422304488 -135000: 2595894054 -134000: 4266597695 -133000: 1116326556 -132000: 3537080833 -131000: 2181246909 -130000: 1241997223 -129000: 628191304 -128000: 3074132403 -127000: 2112958836 -126000: 1371260930 -125000: 2272975771 -124000: 1379085607 -123000: 1998991877 -122000: 2760271255 -121000: 3784187756 -120000: 311188417 -119000: 1123593459 -118000: 1249155194 -117000: 908703020 -116000: 3765244393 -115000: 3040869794 -114000: 437536659 -113000: 3343598822 -112000: 2419089776 -111000: 1263143640 -110000: 1384687523 -109000: 1727931349 -108000: 2861733388 -107000: 963829093 -106000: 431354627 -105000: 3568623360 -104000: 2957399361 -103000: 1071045618 -102000: 3968457714 -101000: 3448338394 -100000: 2586060251 -99000: 3401651822 -98000: 1579089478 -97000: 3722618916 -96000: 759319595 -95000: 1269278712 -94000: 150489448 -93000: 390013662 -92000: 3663029784 -91000: 555197170 -90000: 166476858 -89000: 1658807720 -88000: 3430520531 -87000: 2946861093 -86000: 3000600326 -85000: 300034452 -84000: 2813719249 -83000: 3009927425 -82000: 1127728469 -81000: 2667791855 -80000: 2632316050 -79000: 2180301200 -78000: 418999983 -77000: 4254858933 -76000: 2728734498 -75000: 1863202698 -74000: 4226419921 -73000: 1917572494 -72000: 3117082625 -71000: 1032601538 -70000: 2992135524 -69000: 670119660 -68000: 638731522 -67000: 1460114012 -66000: 1232274665 -65000: 3667669961 -64000: 191277965 -63000: 3868442802 -62000: 700664540 -61000: 2271087482 -60000: 3274078227 -59000: 159900296 -58000: 2778747772 -57000: 2788477153 -56000: 3965957780 -55000: 2276993918 -54000: 1986966104 -53000: 3416414682 -52000: 2162594060 -51000: 2947744069 -50000: 4024793290 -49000: 631161701 -48000: 728285173 -47000: 1487641693 -46000: 4049519424 -45000: 613160608 -44000: 1566126172 -43000: 3731725133 -42000: 2746368727 -41000: 4168967735 -40000: 1319649932 -39000: 2964978784 -38000: 967937134 -37000: 3116555742 -36000: 2279790642 -35000: 2852914953 -34000: 1040410911 -33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 180964610500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index b479c4175..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1097 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.180965 # Number of seconds simulated -sim_ticks 180964610500 # Number of ticks simulated -final_tick 180964610500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 431391 # Simulator instruction rate (inst/s) -host_op_rate 431391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92673550 # Simulator tick rate (ticks/s) -host_mem_usage 265016 # Number of bytes of host memory used -host_seconds 1952.71 # Real time elapsed on the host -sim_insts 842382029 # Number of instructions simulated -sim_ops 842382029 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18525056 # Number of bytes read from this memory -system.physmem.bytes_read::total 18699008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292172 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 961249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102368391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103329640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 961249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 961249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 23582777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 23582777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 23582777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 961249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102368391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 126912416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292172 # Number of read requests accepted -system.physmem.writeReqs 66682 # Number of write requests accepted -system.physmem.readBursts 292172 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18678912 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18699008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18010 # Per bank write bursts -system.physmem.perBankRdBursts::1 18337 # Per bank write bursts -system.physmem.perBankRdBursts::2 18388 # Per bank write bursts -system.physmem.perBankRdBursts::3 18350 # Per bank write bursts -system.physmem.perBankRdBursts::4 18232 # Per bank write bursts -system.physmem.perBankRdBursts::5 18236 # Per bank write bursts -system.physmem.perBankRdBursts::6 18319 # Per bank write bursts -system.physmem.perBankRdBursts::7 18311 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18232 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18381 # Per bank write bursts -system.physmem.perBankRdBursts::12 18250 # Per bank write bursts -system.physmem.perBankRdBursts::13 18122 # Per bank write bursts -system.physmem.perBankRdBursts::14 18054 # Per bank write bursts -system.physmem.perBankRdBursts::15 18189 # Per bank write bursts -system.physmem.perBankWrBursts::0 4125 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4223 # Per bank write bursts -system.physmem.perBankWrBursts::3 4160 # Per bank write bursts -system.physmem.perBankWrBursts::4 4142 # Per bank write bursts -system.physmem.perBankWrBursts::5 4099 # Per bank write bursts -system.physmem.perBankWrBursts::6 4261 # Per bank write bursts -system.physmem.perBankWrBursts::7 4226 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4182 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 180964514000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292172 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 214643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.251837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.294089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.548448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30650 32.23% 32.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40922 43.03% 75.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11798 12.41% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 210 0.22% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 215 0.23% 88.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 192 0.20% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 361 0.38% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1740 1.83% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9017 9.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95105 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.502343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.667312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 739.938886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4047 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4055 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4055 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.438224 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.418308 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.827243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3164 78.03% 78.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.17% 78.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 882 21.75% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4055 # Writes before turning the bus around for reads -system.physmem.totQLat 10146386000 # Total ticks spent queuing -system.physmem.totMemAccLat 15618723500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34764.80 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53514.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 23.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.33 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 23.58 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.99 # Data bus utilization in percentage -system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.18 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing -system.physmem.readRowHits 211326 # Number of row buffer hits during reads -system.physmem.writeRowHits 52079 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.10 # Row buffer hit rate for writes -system.physmem.avgGap 504284.51 # Average gap between requests -system.physmem.pageHitRate 73.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 339192840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 180273885 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1043746620 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174348000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 16047635760.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5505974850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 757646880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 38977794150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 26263488480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 5833398105 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 95148801450 # Total energy per rank (pJ) -system.physmem_0.averagePower 525.786736 # Core power per rank (mW) -system.physmem_0.totalIdleTime 166860797500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1403220500 # Time in different power states -system.physmem_0.memoryStateTime::REF 6819966000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 12988477500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 68394436250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5880505500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 85478004750 # Time in different power states -system.physmem_1.actEnergy 339892560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 180649590 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1040119500 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 173601540 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 16056240720.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5469389970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 750054720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 39161701800 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 26293456800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 5720767110 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 95209751490 # Total energy per rank (pJ) -system.physmem_1.averagePower 526.123579 # Core power per rank (mW) -system.physmem_1.totalIdleTime 166963691000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1377166250 # Time in different power states -system.physmem_1.memoryStateTime::REF 6823618000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 12610325250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 68472559500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5800086000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 85880855500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 129261099 # Number of BP lookups -system.cpu.branchPred.condPredicted 83045520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 145257 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93509067 # Number of BTB lookups -system.cpu.branchPred.BTBHits 70599314 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 75.499966 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19428116 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1153 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14846448 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14825593 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 20855 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 243608266 # DTB read hits -system.cpu.dtb.read_misses 267709 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 243875975 # DTB read accesses -system.cpu.dtb.write_hits 101634051 # DTB write hits -system.cpu.dtb.write_misses 39619 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 101673670 # DTB write accesses -system.cpu.dtb.data_hits 345242317 # DTB hits -system.cpu.dtb.data_misses 307328 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 345549645 # DTB accesses -system.cpu.itb.fetch_hits 116218000 # ITB hits -system.cpu.itb.fetch_misses 1612 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 116219612 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 361929222 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 116540326 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973682349 # Number of instructions fetch has processed -system.cpu.fetch.Branches 129261099 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 104853023 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 244730119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 756754 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 840 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 15490 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 116218000 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 168019 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 361665180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.692220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.078693 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 164951201 45.61% 45.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 21852654 6.04% 51.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15621060 4.32% 55.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24569981 6.79% 62.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 38586382 10.67% 73.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15690881 4.34% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 12539815 3.47% 81.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3986839 1.10% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63866367 17.66% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 361665180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.357145 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.690256 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85732697 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98146269 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158921683 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18492948 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371583 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11928940 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7011 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 968666226 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25451 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371583 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93249960 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12380390 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 169252258 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86395583 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 966785843 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1367 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25166874 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 51736906 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7729074 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 666569704 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1151545318 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114509565 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 37035752 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27602546 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 87961020 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 245059340 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 102632582 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35344831 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4698812 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 877945756 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 74 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 871651299 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 10628 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35563800 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10965429 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 361665180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.410106 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.146787 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 87893149 24.30% 24.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 61352794 16.96% 41.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 57499290 15.90% 57.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51081168 14.12% 71.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45042350 12.45% 83.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20636672 5.71% 89.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18146014 5.02% 94.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10282367 2.84% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9731376 2.69% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 361665180 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3586644 18.56% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11632892 60.20% 78.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3008624 15.57% 94.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 913480 4.73% 99.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 182872 0.95% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 505104722 57.95% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7855 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13297886 1.53% 59.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826557 0.44% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 234518362 26.91% 87.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 97834915 11.22% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 9747446 1.12% 99.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 3972470 0.46% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 871651299 # Type of FU issued -system.cpu.iq.rate 2.408347 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19324512 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2054837876 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 876768256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 835988686 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69465042 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36778231 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34166819 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855694014 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35280521 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65597237 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7548743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37089 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4331382 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2716 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4307 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371583 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4257057 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 608088 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 966007295 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16673 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 245059340 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 102632582 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 74 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 538259 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83477 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37089 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128251 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 15992 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 144243 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 871026557 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 243876094 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 624742 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88061465 # number of nop insts executed -system.cpu.iew.exec_refs 345550079 # number of memory reference insts executed -system.cpu.iew.exec_branches 127153600 # Number of branches executed -system.cpu.iew.exec_stores 101673985 # Number of stores executed -system.cpu.iew.exec_rate 2.406621 # Inst execution rate -system.cpu.iew.wb_sent 870617196 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 870155505 # cumulative count of insts written-back -system.cpu.iew.wb_producers 525001925 # num instructions producing a value -system.cpu.iew.wb_consumers 821956019 # num instructions consuming a value -system.cpu.iew.wb_rate 2.404215 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.638723 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 31805123 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 138464 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 357537289 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.597177 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.046569 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121797842 34.07% 34.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 81929888 22.92% 56.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 29949089 8.38% 65.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19779772 5.53% 70.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17819434 4.98% 75.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7962754 2.23% 78.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3039675 0.85% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3979990 1.11% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71278845 19.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 357537289 # Number of insts commited each cycle -system.cpu.commit.committedInsts 928587628 # Number of instructions committed -system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 335811797 # Number of memory references committed -system.cpu.commit.loads 237510597 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 123111018 # Number of branches committed -system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions. -system.cpu.commit.int_insts 821934723 # Number of committed integer instructions. -system.cpu.commit.function_calls 18524163 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 227943648 24.55% 88.38% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 94464282 10.17% 98.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 9566949 1.03% 99.59% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 3836918 0.41% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 71278845 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1244030057 # The number of ROB reads -system.cpu.rob.rob_writes 1924915650 # The number of ROB writes -system.cpu.timesIdled 3145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 264042 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 842382029 # Number of Instructions Simulated -system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.429650 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.429650 # CPI: Total CPI of All Threads -system.cpu.ipc 2.327477 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.327477 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1104175341 # number of integer regfile reads -system.cpu.int_regfile_writes 635597274 # number of integer regfile writes -system.cpu.fp_regfile_reads 36400867 # number of floating regfile reads -system.cpu.fp_regfile_writes 24677538 # number of floating regfile writes -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776666 # number of replacements -system.cpu.dcache.tags.tagsinuse 4090.964650 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 273860034 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780762 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 350.759942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 396630500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4090.964650 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998771 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2527 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 553391630 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 553391630 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 176451824 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 176451824 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408197 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408197 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 273860021 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 273860021 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 273860021 # number of overall hits -system.cpu.dcache.overall_hits::total 273860021 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1552397 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1552397 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 893003 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 893003 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2445400 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2445400 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2445400 # number of overall misses -system.cpu.dcache.overall_misses::total 2445400 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 96567477000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 96567477000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 65926918364 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 65926918364 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 162494395364 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 162494395364 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 162494395364 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 162494395364 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 178004221 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 178004221 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 276305421 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 276305421 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 276305421 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 276305421 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008721 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008721 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009084 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008850 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008850 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008850 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008850 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62205.400423 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62205.400423 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73826.088338 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73826.088338 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66449.004402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66449.004402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66449.004402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66449.004402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25561 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 192860 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 308 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.990260 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 371.599229 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88570 # number of writebacks -system.cpu.dcache.writebacks::total 88570 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840254 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 840254 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824384 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 824384 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1664638 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1664638 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1664638 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1664638 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712143 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712143 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68619 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68619 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780762 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780762 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780762 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780762 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30603980500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30603980500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6049145998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6049145998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36653126498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36653126498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36653126498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36653126498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42974.487568 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42974.487568 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88155.554555 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88155.554555 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46945.325846 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46945.325846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46945.325846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46945.325846 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.809929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 116209747 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6323 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18378.894038 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.809929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1545 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 232442323 # Number of tag accesses -system.cpu.icache.tags.data_accesses 232442323 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 116209747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 116209747 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 116209747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 116209747 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 116209747 # number of overall hits -system.cpu.icache.overall_hits::total 116209747 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8253 # number of overall misses -system.cpu.icache.overall_misses::total 8253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 382535999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 382535999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 382535999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 382535999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 382535999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 382535999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 116218000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 116218000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 116218000 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 116218000 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 116218000 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 116218000 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46351.144917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46351.144917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46351.144917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46351.144917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46351.144917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46351.144917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 811 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.384615 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4618 # number of writebacks -system.cpu.icache.writebacks::total 4618 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1929 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1929 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1929 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1929 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1929 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1929 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6324 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6324 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6324 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6324 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6324 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6324 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 282422000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 282422000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 282422000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 282422000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 282422000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 282422000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44658.760278 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44658.760278 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44658.760278 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44658.760278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44658.760278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44658.760278 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259808 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32653.135367 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1275792 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292576 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.360549 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 1306360000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 44.057169 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.938267 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32540.139931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001345 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002104 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.993046 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996495 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 834 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8358 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 23070 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12839536 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12839536 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88570 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88570 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3605 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3605 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489315 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 489315 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3605 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 494913 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3605 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491308 # number of overall hits -system.cpu.l2cache.overall_hits::total 494913 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66626 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66626 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2719 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2719 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222828 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222828 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2719 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289454 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292173 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2719 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289454 # number of overall misses -system.cpu.l2cache.overall_misses::total 292173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5925054000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5925054000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234987000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 234987000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 24391913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 24391913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 234987000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30316967000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30551954000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 234987000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30316967000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30551954000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88570 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88570 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68619 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68619 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6324 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6324 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712143 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712143 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6324 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780762 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 787086 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6324 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780762 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 787086 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.970956 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.970956 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.429949 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.429949 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312898 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312898 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.429949 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370733 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.371208 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.429949 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370733 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.371208 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88930.057335 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88930.057335 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86424.052961 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86424.052961 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109465.206347 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109465.206347 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86424.052961 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104738.462761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 104568.026477 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86424.052961 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104738.462761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 104568.026477 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66682 # number of writebacks -system.cpu.l2cache.writebacks::total 66682 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66626 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66626 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2719 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2719 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222828 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222828 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2719 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289454 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2719 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289454 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5258794000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5258794000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207807000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207807000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 22163633000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 22163633000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207807000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27422427000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27630234000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207807000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27422427000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27630234000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970956 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970956 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.429949 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312898 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312898 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370733 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.371208 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370733 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.371208 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78930.057335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78930.057335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76427.730783 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76427.730783 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99465.206347 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99465.206347 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76427.730783 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94738.462761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94568.060704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76427.730783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94738.462761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94568.060704 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1568370 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781284 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2012 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 718466 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6324 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712143 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2355455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55637248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56337472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259808 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1046894 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001922 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043797 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1044882 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2012 0.19% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1046894 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877373000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9484500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171143000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 549969 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257797 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution -system.membus.trans_dist::CleanEvict 191115 # Transaction distribution -system.membus.trans_dist::ReadExReq 66626 # Transaction distribution -system.membus.trans_dist::ReadExResp 66626 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225546 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842141 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842141 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22966656 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292172 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292172 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292172 # Request fanout histogram -system.membus.reqLayer0.occupancy 877590500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551176250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 0452b264c..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 54e31201a..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 3f843823b..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4304 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 -592000: 2038558826 -591000: 3948772976 -590000: 439262378 -589000: 329537197 -588000: 3678661972 -587000: 4240182727 -586000: 2283602206 -585000: 1129811410 -584000: 2831949168 -583000: 1224559023 -582000: 3161562107 -581000: 2695467835 -580000: 1234192577 -579000: 1974816198 -578000: 449576701 -577000: 1424873035 -576000: 2370444290 -575000: 1743089134 -574000: 2624046998 -573000: 2071148441 -572000: 2449219691 -571000: 3774476172 -570000: 1111630327 -569000: 121721805 -568000: 2981212266 -567000: 3811833647 -566000: 3676851843 -565000: 1766252334 -564000: 1622887950 -563000: 1684409857 -562000: 1686489387 -561000: 610219569 -560000: 2705092362 -559000: 108031723 -558000: 1316736987 -557000: 2434129258 -556000: 1411819652 -555000: 1173886179 -554000: 3044539233 -553000: 151590417 -552000: 3759426289 -551000: 3451520306 -550000: 294242855 -549000: 890241051 -548000: 876385779 -547000: 119864600 -546000: 3065674956 -545000: 1670853168 -544000: 997261561 -543000: 660227344 -542000: 3132294889 -541000: 521956271 -540000: 1133928405 -539000: 3838154786 -538000: 58624572 -537000: 3544030439 -536000: 432804999 -535000: 1021857051 -534000: 2644812356 -533000: 773094580 -532000: 901027171 -531000: 3976696839 -530000: 4167278216 -529000: 504481120 -528000: 320399857 -527000: 638048690 -526000: 3348998474 -525000: 2660662065 -524000: 2641437803 -523000: 626927006 -522000: 4063917554 -521000: 3212249308 -520000: 2561025301 -519000: 1078140141 -518000: 653939181 -517000: 2154098204 -516000: 3773089676 -515000: 2568381435 -514000: 3838886937 -513000: 941125346 -512000: 1318900410 -511000: 297013287 -510000: 241723934 -509000: 1835499795 -508000: 2309451230 -507000: 1174814430 -506000: 3615943386 -505000: 51034971 -504000: 3950453295 -503000: 4186097241 -502000: 327518343 -501000: 3052462710 -500000: 1586937404 -499000: 2169094819 -498000: 3613195151 -497000: 817359591 -496000: 1470916579 -495000: 2091261583 -494000: 2080080890 -493000: 1772858697 -492000: 2085609872 -491000: 3280632925 -490000: 1689322569 -489000: 2947406469 -488000: 765163324 -487000: 3122594732 -486000: 3385418480 -485000: 1712345567 -484000: 3675825158 -483000: 1558929764 -482000: 2672493410 -481000: 3822528440 -480000: 3741769935 -479000: 2794026235 -478000: 2541364185 -477000: 3964482316 -476000: 1202478165 -475000: 4027617791 -474000: 1905026738 -473000: 2573787636 -472000: 1170529797 -471000: 2272525618 -470000: 820833429 -469000: 3219769529 -468000: 2121197441 -467000: 269331764 -466000: 3038487237 -465000: 2462675338 -464000: 2703163101 -463000: 547052037 -462000: 3454526671 -461000: 2124641794 -460000: 1043737466 -459000: 1785834964 -458000: 3312335313 -457000: 1213835042 -456000: 3099430685 -455000: 3003350806 -454000: 3646781335 -453000: 1474165966 -452000: 705795987 -451000: 2723908407 -450000: 1323056304 -449000: 1157256530 -448000: 4077983523 -447000: 3189085703 -446000: 2241002747 -445000: 3229050072 -444000: 3500150226 -443000: 1290722604 -442000: 1866107725 -441000: 4238277470 -440000: 847346408 -439000: 2474557496 -438000: 2243092317 -437000: 706909230 -436000: 1303503693 -435000: 1456129560 -434000: 1073061079 -433000: 692226634 -432000: 186498656 -431000: 2203415525 -430000: 2183000701 -429000: 1007776545 -428000: 941117387 -427000: 3805851413 -426000: 1474193180 -425000: 4231673903 -424000: 2622576664 -423000: 388097625 -422000: 1165097488 -421000: 3226044518 -420000: 2531461570 -419000: 1509806310 -418000: 2667519114 -417000: 1751592438 -416000: 1286773513 -415000: 1098182293 -414000: 2111912709 -413000: 1230737431 -412000: 4090873946 -411000: 3998652133 -410000: 2486660396 -409000: 2120483596 -408000: 587404533 -407000: 188697995 -406000: 3265346093 -405000: 4234961905 -404000: 1211873901 -403000: 4265173305 -402000: 2208355316 -401000: 3315952806 -400000: 3917328941 -399000: 2523594649 -398000: 3805986783 -397000: 2624925960 -396000: 3716020189 -395000: 2016201122 -394000: 912930261 -393000: 596904160 -392000: 3571173642 -391000: 2290782861 -390000: 1162492227 -389000: 1738718380 -388000: 2599667355 -387000: 2382332909 -386000: 1471269037 -385000: 2238392684 -384000: 4034826126 -383000: 1378654892 -382000: 3702601850 -381000: 397206179 -380000: 2437704230 -379000: 4187604139 -378000: 779452169 -377000: 2010372403 -376000: 531902409 -375000: 1371470602 -374000: 4137796987 -373000: 567426549 -372000: 3082742955 -371000: 2271575596 -370000: 759731212 -369000: 4063369437 -368000: 299356452 -367000: 536656228 -366000: 3014961694 -365000: 3016542135 -364000: 2841873124 -363000: 524434057 -362000: 2887828889 -361000: 3865529589 -360000: 671363647 -359000: 3104594256 -358000: 1502485940 -357000: 1776624159 -356000: 4222478488 -355000: 4127624139 -354000: 2439477793 -353000: 1593794891 -352000: 591275342 -351000: 2177291538 -350000: 1923444781 -349000: 758084193 -348000: 775471359 -347000: 191356974 -346000: 494488375 -345000: 1990489399 -344000: 124118372 -343000: 2046377904 -342000: 1395427716 -341000: 1342299790 -340000: 38145994 -339000: 2291884417 -338000: 351940574 -337000: 3984301480 -336000: 2468666235 -335000: 371500747 -334000: 969922131 -333000: 240854580 -332000: 1644465214 -331000: 1539846168 -330000: 940087216 -329000: 1491329232 -328000: 2281687201 -327000: 3030170550 -326000: 3648503863 -325000: 2037898355 -324000: 174369956 -323000: 2433605668 -322000: 2334905107 -321000: 1597704047 -320000: 302297707 -319000: 3209203690 -318000: 3894539879 -317000: 2868907580 -316000: 2808087076 -315000: 4034586233 -314000: 3694191694 -313000: 2001671958 -312000: 559582279 -311000: 3043016195 -310000: 2785098502 -309000: 4104602138 -308000: 966154914 -307000: 2446376687 -306000: 789956605 -305000: 1708137092 -304000: 1733063901 -303000: 2924555399 -302000: 971356234 -301000: 481382543 -300000: 2647080988 -299000: 4065744916 -298000: 921140 -297000: 654346784 -296000: 485492098 -295000: 217516816 -294000: 4050820137 -293000: 534726686 -292000: 1686691079 -291000: 1316587195 -290000: 3746020838 -289000: 1641967381 -288000: 3492475215 -287000: 3154885393 -286000: 3686450617 -285000: 3589739293 -284000: 3558041700 -283000: 4130142319 -282000: 3132446063 -281000: 982677436 -280000: 799322395 -279000: 151715214 -278000: 3765942871 -277000: 1712470933 -276000: 3807622752 -275000: 4163730108 -274000: 1633425299 -273000: 1654241631 -272000: 1131025394 -271000: 1375475855 -270000: 553294237 -269000: 4091487177 -268000: 2841855980 -267000: 2997369904 -266000: 454385594 -265000: 3757482634 -264000: 3856197465 -263000: 1084605457 -262000: 2552759023 -261000: 3786548799 -260000: 272762545 -259000: 2670277860 -258000: 76233700 -257000: 476168167 -256000: 8969192 -255000: 1998841030 -254000: 1240074303 -253000: 1771564446 -252000: 710374418 -251000: 821383716 -250000: 3157726088 -249000: 3083379502 -248000: 2563632690 -247000: 33723341 -246000: 3303336748 -245000: 4110677892 -244000: 3811702913 -243000: 53856215 -242000: 243571468 -241000: 52177779 -240000: 46805590 -239000: 1622010618 -238000: 1321640849 -237000: 3106837291 -236000: 4102944642 -235000: 137904396 -234000: 339510135 -233000: 88415957 -232000: 3157666382 -231000: 2571005912 -230000: 3586247649 -229000: 4172761781 -228000: 2463305780 -227000: 956927307 -226000: 2169861547 -225000: 1751989251 -224000: 673059158 -223000: 2782464516 -222000: 3741392140 -221000: 2856154963 -220000: 3778376854 -219000: 1538476717 -218000: 2879698522 -217000: 3734645735 -216000: 1899042577 -215000: 371356008 -214000: 2416663698 -213000: 1595919347 -212000: 2816045438 -211000: 132438808 -210000: 1098603890 -209000: 834913667 -208000: 2707567283 -207000: 3154122448 -206000: 3696516104 -205000: 1427952551 -204000: 280496321 -203000: 1185678745 -202000: 3461951699 -201000: 1369208434 -200000: 3900136261 -199000: 870818876 -198000: 327248310 -197000: 3116959470 -196000: 1544241188 -195000: 1568248814 -194000: 2978831302 -193000: 205660429 -192000: 1704239501 -191000: 3570135474 -190000: 3878512103 -189000: 1212729210 -188000: 1873588815 -187000: 324853813 -186000: 432676298 -185000: 1641364437 -184000: 1568401301 -183000: 525792402 -182000: 861154382 -181000: 2357325066 -180000: 3626762590 -179000: 4172125462 -178000: 2108738993 -177000: 2084782857 -176000: 3956924509 -175000: 17183073 -174000: 3676839474 -173000: 458250029 -172000: 2635215219 -171000: 1801029767 -170000: 3602628987 -169000: 370704281 -168000: 177963345 -167000: 924067814 -166000: 3577678376 -165000: 3717789117 -164000: 3285809386 -163000: 3738962897 -162000: 3172510171 -161000: 417992786 -160000: 2591600214 -159000: 3315096579 -158000: 3590763949 -157000: 198872871 -156000: 2960653534 -155000: 2246563682 -154000: 2304045306 -153000: 2647353543 -152000: 2043381015 -151000: 3952056867 -150000: 2644058641 -149000: 3477151018 -148000: 1740210241 -147000: 3314851112 -146000: 1604832482 -145000: 2572410736 -144000: 1965059167 -143000: 889666293 -142000: 1024747903 -141000: 226685285 -140000: 3149168519 -139000: 403638872 -138000: 1725889104 -137000: 1417402331 -136000: 422304488 -135000: 2595894054 -134000: 4266597695 -133000: 1116326556 -132000: 3537080833 -131000: 2181246909 -130000: 1241997223 -129000: 628191304 -128000: 3074132403 -127000: 2112958836 -126000: 1371260930 -125000: 2272975771 -124000: 1379085607 -123000: 1998991877 -122000: 2760271255 -121000: 3784187756 -120000: 311188417 -119000: 1123593459 -118000: 1249155194 -117000: 908703020 -116000: 3765244393 -115000: 3040869794 -114000: 437536659 -113000: 3343598822 -112000: 2419089776 -111000: 1263143640 -110000: 1384687523 -109000: 1727931349 -108000: 2861733388 -107000: 963829093 -106000: 431354627 -105000: 3568623360 -104000: 2957399361 -103000: 1071045618 -102000: 3968457714 -101000: 3448338394 -100000: 2586060251 -99000: 3401651822 -98000: 1579089478 -97000: 3722618916 -96000: 759319595 -95000: 1269278712 -94000: 150489448 -93000: 390013662 -92000: 3663029784 -91000: 555197170 -90000: 166476858 -89000: 1658807720 -88000: 3430520531 -87000: 2946861093 -86000: 3000600326 -85000: 300034452 -84000: 2813719249 -83000: 3009927425 -82000: 1127728469 -81000: 2667791855 -80000: 2632316050 -79000: 2180301200 -78000: 418999983 -77000: 4254858933 -76000: 2728734498 -75000: 1863202698 -74000: 4226419921 -73000: 1917572494 -72000: 3117082625 -71000: 1032601538 -70000: 2992135524 -69000: 670119660 -68000: 638731522 -67000: 1460114012 -66000: 1232274665 -65000: 3667669961 -64000: 191277965 -63000: 3868442802 -62000: 700664540 -61000: 2271087482 -60000: 3274078227 -59000: 159900296 -58000: 2778747772 -57000: 2788477153 -56000: 3965957780 -55000: 2276993918 -54000: 1986966104 -53000: 3416414682 -52000: 2162594060 -51000: 2947744069 -50000: 4024793290 -49000: 631161701 -48000: 728285173 -47000: 1487641693 -46000: 4049519424 -45000: 613160608 -44000: 1566126172 -43000: 3731725133 -42000: 2746368727 -41000: 4168967735 -40000: 1319649932 -39000: 2964978784 -38000: 967937134 -37000: 3116555742 -36000: 2279790642 -35000: 2852914953 -34000: 1040410911 -33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 464394627000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index fdd12f539..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.464395 # Number of seconds simulated -sim_ticks 464394627000 # Number of ticks simulated -final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2996785 # Simulator instruction rate (inst/s) -host_op_rate 2996785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1498717563 # Simulator tick rate (ticks/s) -host_mem_usage 251436 # Number of bytes of host memory used -host_seconds 309.86 # Real time elapsed on the host -sim_insts 928587629 # Number of instructions simulated -sim_ops 928587629 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory -system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory -system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237510597 # DTB read hits -system.cpu.dtb.read_misses 194650 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237705247 # DTB read accesses -system.cpu.dtb.write_hits 98301200 # DTB write hits -system.cpu.dtb.write_misses 6871 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98308071 # DTB write accesses -system.cpu.dtb.data_hits 335811797 # DTB hits -system.cpu.dtb.data_misses 201521 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336013318 # DTB accesses -system.cpu.itb.fetch_hits 928789150 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 928789255 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 464394627000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 928789255 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928587629 # Number of instructions committed -system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses -system.cpu.num_func_calls 37048314 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls -system.cpu.num_int_insts 822136244 # number of integer instructions -system.cpu.num_fp_insts 33439365 # number of float instructions -system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read -system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read -system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written -system.cpu.num_mem_refs 336013318 # number of memory refs -system.cpu.num_load_insts 237705247 # Number of load instructions -system.cpu.num_store_insts 98308071 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 928789255 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 123111018 # Number of branches fetched -system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction -system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction -system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction -system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction -system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 928789150 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution -system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution -system.membus.trans_dist::WriteReq 98301200 # Transaction distribution -system.membus.trans_dist::WriteResp 98301200 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1264600947 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1264600947 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index b6ac9fa01..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 54e31201a..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index 6564d4aeb..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4305 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 -592000: 2038558826 -591000: 3948772976 -590000: 439262378 -589000: 329537197 -588000: 3678661972 -587000: 4240182727 -586000: 2283602206 -585000: 1129811410 -584000: 2831949168 -583000: 1224559023 -582000: 3161562107 -581000: 2695467835 -580000: 1234192577 -579000: 1974816198 -578000: 449576701 -577000: 1424873035 -576000: 2370444290 -575000: 1743089134 -574000: 2624046998 -573000: 2071148441 -572000: 2449219691 -571000: 3774476172 -570000: 1111630327 -569000: 121721805 -568000: 2981212266 -567000: 3811833647 -566000: 3676851843 -565000: 1766252334 -564000: 1622887950 -563000: 1684409857 -562000: 1686489387 -561000: 610219569 -560000: 2705092362 -559000: 108031723 -558000: 1316736987 -557000: 2434129258 -556000: 1411819652 -555000: 1173886179 -554000: 3044539233 -553000: 151590417 -552000: 3759426289 -551000: 3451520306 -550000: 294242855 -549000: 890241051 -548000: 876385779 -547000: 119864600 -546000: 3065674956 -545000: 1670853168 -544000: 997261561 -543000: 660227344 -542000: 3132294889 -541000: 521956271 -540000: 1133928405 -539000: 3838154786 -538000: 58624572 -537000: 3544030439 -536000: 432804999 -535000: 1021857051 -534000: 2644812356 -533000: 773094580 -532000: 901027171 -531000: 3976696839 -530000: 4167278216 -529000: 504481120 -528000: 320399857 -527000: 638048690 -526000: 3348998474 -525000: 2660662065 -524000: 2641437803 -523000: 626927006 -522000: 4063917554 -521000: 3212249308 -520000: 2561025301 -519000: 1078140141 -518000: 653939181 -517000: 2154098204 -516000: 3773089676 -515000: 2568381435 -514000: 3838886937 -513000: 941125346 -512000: 1318900410 -511000: 297013287 -510000: 241723934 -509000: 1835499795 -508000: 2309451230 -507000: 1174814430 -506000: 3615943386 -505000: 51034971 -504000: 3950453295 -503000: 4186097241 -502000: 327518343 -501000: 3052462710 -500000: 1586937404 -499000: 2169094819 -498000: 3613195151 -497000: 817359591 -496000: 1470916579 -495000: 2091261583 -494000: 2080080890 -493000: 1772858697 -492000: 2085609872 -491000: 3280632925 -490000: 1689322569 -489000: 2947406469 -488000: 765163324 -487000: 3122594732 -486000: 3385418480 -485000: 1712345567 -484000: 3675825158 -483000: 1558929764 -482000: 2672493410 -481000: 3822528440 -480000: 3741769935 -479000: 2794026235 -478000: 2541364185 -477000: 3964482316 -476000: 1202478165 -475000: 4027617791 -474000: 1905026738 -473000: 2573787636 -472000: 1170529797 -471000: 2272525618 -470000: 820833429 -469000: 3219769529 -468000: 2121197441 -467000: 269331764 -466000: 3038487237 -465000: 2462675338 -464000: 2703163101 -463000: 547052037 -462000: 3454526671 -461000: 2124641794 -460000: 1043737466 -459000: 1785834964 -458000: 3312335313 -457000: 1213835042 -456000: 3099430685 -455000: 3003350806 -454000: 3646781335 -453000: 1474165966 -452000: 705795987 -451000: 2723908407 -450000: 1323056304 -449000: 1157256530 -448000: 4077983523 -447000: 3189085703 -446000: 2241002747 -445000: 3229050072 -444000: 3500150226 -443000: 1290722604 -442000: 1866107725 -441000: 4238277470 -440000: 847346408 -439000: 2474557496 -438000: 2243092317 -437000: 706909230 -436000: 1303503693 -435000: 1456129560 -434000: 1073061079 -433000: 692226634 -432000: 186498656 -431000: 2203415525 -430000: 2183000701 -429000: 1007776545 -428000: 941117387 -427000: 3805851413 -426000: 1474193180 -425000: 4231673903 -424000: 2622576664 -423000: 388097625 -422000: 1165097488 -421000: 3226044518 -420000: 2531461570 -419000: 1509806310 -418000: 2667519114 -417000: 1751592438 -416000: 1286773513 -415000: 1098182293 -414000: 2111912709 -413000: 1230737431 -412000: 4090873946 -411000: 3998652133 -410000: 2486660396 -409000: 2120483596 -408000: 587404533 -407000: 188697995 -406000: 3265346093 -405000: 4234961905 -404000: 1211873901 -403000: 4265173305 -402000: 2208355316 -401000: 3315952806 -400000: 3917328941 -399000: 2523594649 -398000: 3805986783 -397000: 2624925960 -396000: 3716020189 -395000: 2016201122 -394000: 912930261 -393000: 596904160 -392000: 3571173642 -391000: 2290782861 -390000: 1162492227 -389000: 1738718380 -388000: 2599667355 -387000: 2382332909 -386000: 1471269037 -385000: 2238392684 -384000: 4034826126 -383000: 1378654892 -382000: 3702601850 -381000: 397206179 -380000: 2437704230 -379000: 4187604139 -378000: 779452169 -377000: 2010372403 -376000: 531902409 -375000: 1371470602 -374000: 4137796987 -373000: 567426549 -372000: 3082742955 -371000: 2271575596 -370000: 759731212 -369000: 4063369437 -368000: 299356452 -367000: 536656228 -366000: 3014961694 -365000: 3016542135 -364000: 2841873124 -363000: 524434057 -362000: 2887828889 -361000: 3865529589 -360000: 671363647 -359000: 3104594256 -358000: 1502485940 -357000: 1776624159 -356000: 4222478488 -355000: 4127624139 -354000: 2439477793 -353000: 1593794891 -352000: 591275342 -351000: 2177291538 -350000: 1923444781 -349000: 758084193 -348000: 775471359 -347000: 191356974 -346000: 494488375 -345000: 1990489399 -344000: 124118372 -343000: 2046377904 -342000: 1395427716 -341000: 1342299790 -340000: 38145994 -339000: 2291884417 -338000: 351940574 -337000: 3984301480 -336000: 2468666235 -335000: 371500747 -334000: 969922131 -333000: 240854580 -332000: 1644465214 -331000: 1539846168 -330000: 940087216 -329000: 1491329232 -328000: 2281687201 -327000: 3030170550 -326000: 3648503863 -325000: 2037898355 -324000: 174369956 -323000: 2433605668 -322000: 2334905107 -321000: 1597704047 -320000: 302297707 -319000: 3209203690 -318000: 3894539879 -317000: 2868907580 -316000: 2808087076 -315000: 4034586233 -314000: 3694191694 -313000: 2001671958 -312000: 559582279 -311000: 3043016195 -310000: 2785098502 -309000: 4104602138 -308000: 966154914 -307000: 2446376687 -306000: 789956605 -305000: 1708137092 -304000: 1733063901 -303000: 2924555399 -302000: 971356234 -301000: 481382543 -300000: 2647080988 -299000: 4065744916 -298000: 921140 -297000: 654346784 -296000: 485492098 -295000: 217516816 -294000: 4050820137 -293000: 534726686 -292000: 1686691079 -291000: 1316587195 -290000: 3746020838 -289000: 1641967381 -288000: 3492475215 -287000: 3154885393 -286000: 3686450617 -285000: 3589739293 -284000: 3558041700 -283000: 4130142319 -282000: 3132446063 -281000: 982677436 -280000: 799322395 -279000: 151715214 -278000: 3765942871 -277000: 1712470933 -276000: 3807622752 -275000: 4163730108 -274000: 1633425299 -273000: 1654241631 -272000: 1131025394 -271000: 1375475855 -270000: 553294237 -269000: 4091487177 -268000: 2841855980 -267000: 2997369904 -266000: 454385594 -265000: 3757482634 -264000: 3856197465 -263000: 1084605457 -262000: 2552759023 -261000: 3786548799 -260000: 272762545 -259000: 2670277860 -258000: 76233700 -257000: 476168167 -256000: 8969192 -255000: 1998841030 -254000: 1240074303 -253000: 1771564446 -252000: 710374418 -251000: 821383716 -250000: 3157726088 -249000: 3083379502 -248000: 2563632690 -247000: 33723341 -246000: 3303336748 -245000: 4110677892 -244000: 3811702913 -243000: 53856215 -242000: 243571468 -241000: 52177779 -240000: 46805590 -239000: 1622010618 -238000: 1321640849 -237000: 3106837291 -236000: 4102944642 -235000: 137904396 -234000: 339510135 -233000: 88415957 -232000: 3157666382 -231000: 2571005912 -230000: 3586247649 -229000: 4172761781 -228000: 2463305780 -227000: 956927307 -226000: 2169861547 -225000: 1751989251 -224000: 673059158 -223000: 2782464516 -222000: 3741392140 -221000: 2856154963 -220000: 3778376854 -219000: 1538476717 -218000: 2879698522 -217000: 3734645735 -216000: 1899042577 -215000: 371356008 -214000: 2416663698 -213000: 1595919347 -212000: 2816045438 -211000: 132438808 -210000: 1098603890 -209000: 834913667 -208000: 2707567283 -207000: 3154122448 -206000: 3696516104 -205000: 1427952551 -204000: 280496321 -203000: 1185678745 -202000: 3461951699 -201000: 1369208434 -200000: 3900136261 -199000: 870818876 -198000: 327248310 -197000: 3116959470 -196000: 1544241188 -195000: 1568248814 -194000: 2978831302 -193000: 205660429 -192000: 1704239501 -191000: 3570135474 -190000: 3878512103 -189000: 1212729210 -188000: 1873588815 -187000: 324853813 -186000: 432676298 -185000: 1641364437 -184000: 1568401301 -183000: 525792402 -182000: 861154382 -181000: 2357325066 -180000: 3626762590 -179000: 4172125462 -178000: 2108738993 -177000: 2084782857 -176000: 3956924509 -175000: 17183073 -174000: 3676839474 -173000: 458250029 -172000: 2635215219 -171000: 1801029767 -170000: 3602628987 -169000: 370704281 -168000: 177963345 -167000: 924067814 -166000: 3577678376 -165000: 3717789117 -164000: 3285809386 -163000: 3738962897 -162000: 3172510171 -161000: 417992786 -160000: 2591600214 -159000: 3315096579 -158000: 3590763949 -157000: 198872871 -156000: 2960653534 -155000: 2246563682 -154000: 2304045306 -153000: 2647353543 -152000: 2043381015 -151000: 3952056867 -150000: 2644058641 -149000: 3477151018 -148000: 1740210241 -147000: 3314851112 -146000: 1604832482 -145000: 2572410736 -144000: 1965059167 -143000: 889666293 -142000: 1024747903 -141000: 226685285 -140000: 3149168519 -139000: 403638872 -138000: 1725889104 -137000: 1417402331 -136000: 422304488 -135000: 2595894054 -134000: 4266597695 -133000: 1116326556 -132000: 3537080833 -131000: 2181246909 -130000: 1241997223 -129000: 628191304 -128000: 3074132403 -127000: 2112958836 -126000: 1371260930 -125000: 2272975771 -124000: 1379085607 -123000: 1998991877 -122000: 2760271255 -121000: 3784187756 -120000: 311188417 -119000: 1123593459 -118000: 1249155194 -117000: 908703020 -116000: 3765244393 -115000: 3040869794 -114000: 437536659 -113000: 3343598822 -112000: 2419089776 -111000: 1263143640 -110000: 1384687523 -109000: 1727931349 -108000: 2861733388 -107000: 963829093 -106000: 431354627 -105000: 3568623360 -104000: 2957399361 -103000: 1071045618 -102000: 3968457714 -101000: 3448338394 -100000: 2586060251 -99000: 3401651822 -98000: 1579089478 -97000: 3722618916 -96000: 759319595 -95000: 1269278712 -94000: 150489448 -93000: 390013662 -92000: 3663029784 -91000: 555197170 -90000: 166476858 -89000: 1658807720 -88000: 3430520531 -87000: 2946861093 -86000: 3000600326 -85000: 300034452 -84000: 2813719249 -83000: 3009927425 -82000: 1127728469 -81000: 2667791855 -80000: 2632316050 -79000: 2180301200 -78000: 418999983 -77000: 4254858933 -76000: 2728734498 -75000: 1863202698 -74000: 4226419921 -73000: 1917572494 -72000: 3117082625 -71000: 1032601538 -70000: 2992135524 -69000: 670119660 -68000: 638731522 -67000: 1460114012 -66000: 1232274665 -65000: 3667669961 -64000: 191277965 -63000: 3868442802 -62000: 700664540 -61000: 2271087482 -60000: 3274078227 -59000: 159900296 -58000: 2778747772 -57000: 2788477153 -56000: 3965957780 -55000: 2276993918 -54000: 1986966104 -53000: 3416414682 -52000: 2162594060 -51000: 2947744069 -50000: 4024793290 -49000: 631161701 -48000: 728285173 -47000: 1487641693 -46000: 4049519424 -45000: 613160608 -44000: 1566126172 -43000: 3731725133 -42000: 2746368727 -41000: 4168967735 -40000: 1319649932 -39000: 2964978784 -38000: 967937134 -37000: 3116555742 -36000: 2279790642 -35000: 2852914953 -34000: 1040410911 -33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 1288319411500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index b41b24d8c..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,571 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.288611 # Number of seconds simulated -sim_ticks 1288611150500 # Number of ticks simulated -final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2016883 # Simulator instruction rate (inst/s) -host_op_rate 2016883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2798849858 # Simulator tick rate (ticks/s) -host_mem_usage 261432 # Number of bytes of host memory used -host_seconds 460.41 # Real time elapsed on the host -sim_insts 928587629 # Number of instructions simulated -sim_ops 928587629 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18512320 # Number of bytes read from this memory -system.physmem.bytes_read::total 18649344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289255 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291396 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14366103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14472437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3311870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3311870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3311870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14366103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17784307 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237510597 # DTB read hits -system.cpu.dtb.read_misses 194650 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237705247 # DTB read accesses -system.cpu.dtb.write_hits 98301200 # DTB write hits -system.cpu.dtb.write_misses 6871 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98308071 # DTB write accesses -system.cpu.dtb.data_hits 335811797 # DTB hits -system.cpu.dtb.data_misses 201521 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336013318 # DTB accesses -system.cpu.itb.fetch_hits 928789151 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 928789256 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2577222301 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928587629 # Number of instructions committed -system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses -system.cpu.num_func_calls 37048314 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls -system.cpu.num_int_insts 822136244 # number of integer instructions -system.cpu.num_fp_insts 33439365 # number of float instructions -system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read -system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read -system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written -system.cpu.num_mem_refs 336013318 # number of memory refs -system.cpu.num_load_insts 237705247 # Number of load instructions -system.cpu.num_store_insts 98308071 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2577222301 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 123111018 # Number of branches fetched -system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction -system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction -system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction -system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction -system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 928789150 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.168779 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1112572500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.168779 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits -system.cpu.dcache.overall_hits::total 335031269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses -system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20380048000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20380048000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4229584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4229584000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24609632000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24609632000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24609632000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24609632000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28643.214329 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28643.214329 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61285.884024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61285.884024 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31529.467232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31529.467232 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88841 # number of writebacks -system.cpu.dcache.writebacks::total 88841 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19668534000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19668534000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4160570000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4160570000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23829104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23829104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23829104000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23829104000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27643.214329 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27643.214329 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60285.884024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60285.884024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.409268 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.409268 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits -system.cpu.icache.overall_hits::total 928782983 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses -system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 187267500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 187267500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 187267500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 187267500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 187267500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 187267500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30361.138132 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30361.138132 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30361.138132 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30361.138132 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4618 # number of writebacks -system.cpu.icache.writebacks::total 4618 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 181099500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 181099500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 181099500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 181099500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 181099500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 181099500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29361.138132 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29361.138132 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258865 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32717.214949 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1276112 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291633 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.375746 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4209362000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27.944200 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.856544 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32641.414205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000853 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001460 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.996137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998450 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31170 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12833601 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12833601 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88841 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88841 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488907 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488907 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491273 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495300 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491273 # number of overall hits -system.cpu.l2cache.overall_hits::total 495300 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222607 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222607 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289255 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291396 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289255 # number of overall misses -system.cpu.l2cache.overall_misses::total 291396 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4032205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4032205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 129556500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 129556500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13467735000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13467735000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 129556500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17499940000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17629496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 129556500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17499940000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17629496500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88841 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88841 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312864 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312864 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370589 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370405 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370589 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370405 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.051661 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.051661 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.132123 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.132123 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222607 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222607 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289255 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289255 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3365725000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3365725000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 108146500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 108146500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11241665000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11241665000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108146500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14607390000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14715536500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108146500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14607390000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14715536500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312864 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312864 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370405 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370405 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.051661 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.051661 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1726 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1726 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56329920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258865 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1045561 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.040596 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1043835 99.83% 99.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1726 0.17% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1045561 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877332000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 548536 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257140 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224748 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190457 # Transaction distribution -system.membus.trans_dist::ReadExReq 66648 # Transaction distribution -system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224748 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839932 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22917056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22917056 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 291396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 291396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 291396 # Request fanout histogram -system.membus.reqLayer0.occupancy 815280500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456980000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 46094eb94..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index a86af0918..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28063 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 61709224000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 0d9a67eb8..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,829 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.061709 # Number of seconds simulated -sim_ticks 61709224000 # Number of ticks simulated -final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 484192 # Simulator instruction rate (inst/s) -host_op_rate 484192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337853764 # Simulator tick rate (ticks/s) -host_mem_usage 263376 # Number of bytes of host memory used -host_seconds 182.65 # Real time elapsed on the host -sim_insts 88438073 # Number of instructions simulated -sim_ops 88438073 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory -system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory -system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165740 # Number of read requests accepted -system.physmem.writeReqs 115251 # Number of write requests accepted -system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue -system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10345 # Per bank write bursts -system.physmem.perBankRdBursts::1 10387 # Per bank write bursts -system.physmem.perBankRdBursts::2 10224 # Per bank write bursts -system.physmem.perBankRdBursts::3 10068 # Per bank write bursts -system.physmem.perBankRdBursts::4 10353 # Per bank write bursts -system.physmem.perBankRdBursts::5 10360 # Per bank write bursts -system.physmem.perBankRdBursts::6 9794 # Per bank write bursts -system.physmem.perBankRdBursts::7 10230 # Per bank write bursts -system.physmem.perBankRdBursts::8 10568 # Per bank write bursts -system.physmem.perBankRdBursts::9 10626 # Per bank write bursts -system.physmem.perBankRdBursts::10 10568 # Per bank write bursts -system.physmem.perBankRdBursts::11 10241 # Per bank write bursts -system.physmem.perBankRdBursts::12 10306 # Per bank write bursts -system.physmem.perBankRdBursts::13 10592 # Per bank write bursts -system.physmem.perBankRdBursts::14 10494 # Per bank write bursts -system.physmem.perBankRdBursts::15 10573 # Per bank write bursts -system.physmem.perBankWrBursts::0 7166 # Per bank write bursts -system.physmem.perBankWrBursts::1 7281 # Per bank write bursts -system.physmem.perBankWrBursts::2 7303 # Per bank write bursts -system.physmem.perBankWrBursts::3 7012 # Per bank write bursts -system.physmem.perBankWrBursts::4 7145 # Per bank write bursts -system.physmem.perBankWrBursts::5 7305 # Per bank write bursts -system.physmem.perBankWrBursts::6 6890 # Per bank write bursts -system.physmem.perBankWrBursts::7 7164 # Per bank write bursts -system.physmem.perBankWrBursts::8 7246 # Per bank write bursts -system.physmem.perBankWrBursts::9 7071 # Per bank write bursts -system.physmem.perBankWrBursts::10 7213 # Per bank write bursts -system.physmem.perBankWrBursts::11 7126 # Per bank write bursts -system.physmem.perBankWrBursts::12 7072 # Per bank write bursts -system.physmem.perBankWrBursts::13 7397 # Per bank write bursts -system.physmem.perBankWrBursts::14 7351 # Per bank write bursts -system.physmem.perBankWrBursts::15 7483 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61709200500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165740 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115251 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads -system.physmem.totQLat 3617300750 # Total ticks spent queuing -system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.28 # Data bus utilization in percentage -system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing -system.physmem.readRowHits 144262 # Number of row buffer hits during reads -system.physmem.writeRowHits 89468 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes -system.physmem.avgGap 219612.73 # Average gap between requests -system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ) -system.physmem_0.averagePower 393.299410 # Core power per rank (mW) -system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states -system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ) -system.physmem_1.averagePower 400.858918 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14696527 # Number of BP lookups -system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20579387 # DTB read hits -system.cpu.dtb.read_misses 95377 # DTB read misses -system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674764 # DTB read accesses -system.cpu.dtb.write_hits 14666029 # DTB write hits -system.cpu.dtb.write_misses 8840 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674869 # DTB write accesses -system.cpu.dtb.data_hits 35245416 # DTB hits -system.cpu.dtb.data_misses 104217 # DTB misses -system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35349633 # DTB accesses -system.cpu.itb.fetch_hits 25650137 # ITB hits -system.cpu.itb.fetch_misses 5179 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25655316 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 123418448 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88438073 # Number of instructions committed -system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.395535 # CPI: cycles per instruction -system.cpu.ipc 0.716571 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction -system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction -system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::MemRead 20366476 23.03% 83.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 14619024 16.53% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 310 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked -system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200809 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits -system.cpu.dcache.overall_hits::total 34647996 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses -system.cpu.dcache.overall_misses::total 341611 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168117 # number of writebacks -system.cpu.dcache.writebacks::total 168117 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136509 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136706 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136706 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136706 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136706 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61338 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61338 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3088657500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50354.714859 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50354.714859 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84853.890518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84853.890518 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 153962 # number of replacements -system.cpu.icache.tags.tagsinuse 1929.475732 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25494126 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 156010 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.413409 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 43906590500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1929.475732 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.942127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.942127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51456284 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51456284 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25494126 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25494126 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25494126 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25494126 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25494126 # number of overall hits -system.cpu.icache.overall_hits::total 25494126 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 156011 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 156011 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 156011 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 156011 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 156011 # number of overall misses -system.cpu.icache.overall_misses::total 156011 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2690499000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2690499000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2690499000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2690499000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2690499000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2690499000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25650137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25650137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25650137 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25650137 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25650137 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25650137 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17245.572428 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17245.572428 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17245.572428 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17245.572428 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153962 # number of writebacks -system.cpu.icache.writebacks::total 153962 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 156011 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 156011 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 156011 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 156011 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 156011 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 156011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2534489000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2534489000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2534489000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2534489000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2534489000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2534489000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16245.578837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16245.578837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 135280 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31691.220276 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 547521 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168048 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.258123 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 14447297000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 710.430921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1986.776331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28994.013023 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021681 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060632 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.884827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.967139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 8856 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22759 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5893544 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5893544 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168117 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168117 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153962 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153962 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 149161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33355 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33355 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 149161 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46014 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 195175 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 149161 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46014 # number of overall hits -system.cpu.l2cache.overall_hits::total 195175 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6850 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6850 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27983 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27983 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6850 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158891 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165741 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6850 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158891 # number of overall misses -system.cpu.l2cache.overall_misses::total 165741 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11833894500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11833894500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 734127500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 734127500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2646160500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2646160500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 734127500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14480055000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15214182500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 734127500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14480055000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15214182500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168117 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168117 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 153962 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 153962 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 156011 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 156011 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61338 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61338 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 156011 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360916 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 156011 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360916 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043907 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043907 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456210 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456210 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043907 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775437 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.459223 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043907 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775437 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.459223 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90398.558530 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90398.558530 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107171.897810 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107171.897810 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94563.145481 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94563.145481 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 91794.924008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 91794.924008 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115252 # number of writebacks -system.cpu.l2cache.writebacks::total 115252 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6850 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6850 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27983 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27983 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6850 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158891 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165741 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6850 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158891 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165741 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10524814500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10524814500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 665637500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 665637500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2366330500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2366330500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 665637500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12891145000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13556782500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 665637500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12891145000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13556782500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135280 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34832 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution -system.membus.trans_dist::CleanEvict 15886 # Transaction distribution -system.membus.trans_dist::ReadExReq 130908 # Transaction distribution -system.membus.trans_dist::ReadExResp 130908 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165740 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165740 # Request fanout histogram -system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index 42d282c4a..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 03964c60a..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28054 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 22819771500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg deleted file mode 100644 index 472b08431..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index 53a1c5599..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1097 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.022820 # Number of seconds simulated -sim_ticks 22819771500 # Number of ticks simulated -final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 390933 # Simulator instruction rate (inst/s) -host_op_rate 390933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112084385 # Simulator tick rate (ticks/s) -host_mem_usage 265424 # Number of bytes of host memory used -host_seconds 203.59 # Real time elapsed on the host -sim_insts 79591756 # Number of instructions simulated -sim_ops 79591756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 414016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10170944 # Number of bytes read from this memory -system.physmem.bytes_read::total 10584960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 414016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 414016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 7372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158921 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165390 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18142864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 445707530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 463850394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18142864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18142864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 323079835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 323079835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 323079835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18142864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 445707530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 786930228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165390 # Number of read requests accepted -system.physmem.writeReqs 115197 # Number of write requests accepted -system.physmem.readBursts 165390 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115197 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10584512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7370752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10584960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7372608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10310 # Per bank write bursts -system.physmem.perBankRdBursts::1 10353 # Per bank write bursts -system.physmem.perBankRdBursts::2 10221 # Per bank write bursts -system.physmem.perBankRdBursts::3 10036 # Per bank write bursts -system.physmem.perBankRdBursts::4 10349 # Per bank write bursts -system.physmem.perBankRdBursts::5 10326 # Per bank write bursts -system.physmem.perBankRdBursts::6 9802 # Per bank write bursts -system.physmem.perBankRdBursts::7 10209 # Per bank write bursts -system.physmem.perBankRdBursts::8 10557 # Per bank write bursts -system.physmem.perBankRdBursts::9 10617 # Per bank write bursts -system.physmem.perBankRdBursts::10 10516 # Per bank write bursts -system.physmem.perBankRdBursts::11 10223 # Per bank write bursts -system.physmem.perBankRdBursts::12 10279 # Per bank write bursts -system.physmem.perBankRdBursts::13 10557 # Per bank write bursts -system.physmem.perBankRdBursts::14 10475 # Per bank write bursts -system.physmem.perBankRdBursts::15 10553 # Per bank write bursts -system.physmem.perBankWrBursts::0 7167 # Per bank write bursts -system.physmem.perBankWrBursts::1 7277 # Per bank write bursts -system.physmem.perBankWrBursts::2 7300 # Per bank write bursts -system.physmem.perBankWrBursts::3 7008 # Per bank write bursts -system.physmem.perBankWrBursts::4 7142 # Per bank write bursts -system.physmem.perBankWrBursts::5 7300 # Per bank write bursts -system.physmem.perBankWrBursts::6 6892 # Per bank write bursts -system.physmem.perBankWrBursts::7 7158 # Per bank write bursts -system.physmem.perBankWrBursts::8 7240 # Per bank write bursts -system.physmem.perBankWrBursts::9 7069 # Per bank write bursts -system.physmem.perBankWrBursts::10 7202 # Per bank write bursts -system.physmem.perBankWrBursts::11 7121 # Per bank write bursts -system.physmem.perBankWrBursts::12 7069 # Per bank write bursts -system.physmem.perBankWrBursts::13 7390 # Per bank write bursts -system.physmem.perBankWrBursts::14 7350 # Per bank write bursts -system.physmem.perBankWrBursts::15 7483 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22819740500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165390 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115197 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 42313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 44648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 402.130084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 240.586732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.720381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13091 29.32% 29.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8315 18.62% 47.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5360 12.01% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2692 6.03% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2549 5.71% 71.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1575 3.53% 75.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1705 3.82% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1125 2.52% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8236 18.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 44648 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.304961 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.955367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 317.126574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7095 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7096 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.229989 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.211978 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.816035 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6480 91.32% 91.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 18 0.25% 91.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 334 4.71% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 161 2.27% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 74 1.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 24 0.34% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7096 # Writes before turning the bus around for reads -system.physmem.totQLat 7131716500 # Total ticks spent queuing -system.physmem.totMemAccLat 10232647750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43122.43 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 61872.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 463.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 323.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 463.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 323.08 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.15 # Data bus utilization in percentage -system.physmem.busUtilRead 3.62 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 145971 # Number of row buffer hits during reads -system.physmem.writeRowHits 89923 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes -system.physmem.avgGap 81328.57 # Average gap between requests -system.physmem.pageHitRate 84.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153103020 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 81361005 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 582666840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 298813680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1398920640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1820142240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 87895200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 2523555300 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1884269760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 2191410645 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11023267740 # Total energy per rank (pJ) -system.physmem_0.averagePower 483.057740 # Core power per rank (mW) -system.physmem_0.totalIdleTime 18596850000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 135529000 # Time in different power states -system.physmem_0.memoryStateTime::REF 594334000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 8155766000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 4906976500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3493009750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 5534156250 # Time in different power states -system.physmem_1.actEnergy 165747960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 88078155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 598167780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 302363280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1429652640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1911531480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 82258560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 2724848520 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1880202720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 2026371015 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11210189940 # Total energy per rank (pJ) -system.physmem_1.averagePower 491.248979 # Core power per rank (mW) -system.physmem_1.totalIdleTime 18411251500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 119903000 # Time in different power states -system.physmem_1.memoryStateTime::REF 607208000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 7539541250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 4896374750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3681289750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 5975454750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16458678 # Number of BP lookups -system.cpu.branchPred.condPredicted 10655092 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 320474 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8794743 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7227596 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.180866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1974394 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3324 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39317 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31522 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7795 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2656 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22495361 # DTB read hits -system.cpu.dtb.read_misses 227004 # DTB read misses -system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22722365 # DTB read accesses -system.cpu.dtb.write_hits 15803250 # DTB write hits -system.cpu.dtb.write_misses 44602 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15847852 # DTB write accesses -system.cpu.dtb.data_hits 38298611 # DTB hits -system.cpu.dtb.data_misses 271606 # DTB misses -system.cpu.dtb.data_acv 22 # DTB access violations -system.cpu.dtb.data_accesses 38570217 # DTB accesses -system.cpu.itb.fetch_hits 13713928 # ITB hits -system.cpu.itb.fetch_misses 29641 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13743569 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45639548 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15527632 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104958165 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16458678 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9233512 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 28526394 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 879432 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1335 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 342280 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 91 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13713928 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 186437 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 44842161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.340613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.113400 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25352844 56.54% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1513864 3.38% 59.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1375551 3.07% 62.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1499198 3.34% 66.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4186922 9.34% 75.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1824752 4.07% 79.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669001 1.49% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050081 2.34% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7369948 16.44% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44842161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.360623 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.299720 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14899514 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10738608 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18272960 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 588305 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 342774 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3699945 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98528 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 102994976 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312859 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 342774 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15240271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5029380 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97820 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18506228 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5625688 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102003977 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6871 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 88609 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 422499 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5043111 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61324692 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123005722 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122686459 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319262 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8777811 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5683 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5735 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2339310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23131891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16353716 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1249387 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502474 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90699211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5558 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88573949 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67838 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11113012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4439512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 975 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44842161 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.975238 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.240795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18402096 41.04% 41.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5711089 12.74% 53.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5105714 11.39% 65.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4382501 9.77% 74.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4313150 9.62% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2637224 5.88% 90.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1940283 4.33% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1377321 3.07% 97.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 972783 2.17% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44842161 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 241463 9.57% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168317 46.29% 55.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1113838 44.13% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 25 0.00% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 417 0.02% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49366935 55.74% 55.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43991 0.05% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22887385 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15970151 18.03% 99.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 459 0.00% 99.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 23933 0.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued -system.cpu.iq.rate 1.940728 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2524060 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028497 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223970516 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611441 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90792080 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305929 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5856 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740339 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3017 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 190756 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 342774 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1435868 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3107979 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100192818 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 116708 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23131891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16353716 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5558 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3773 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3106841 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 111267 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 152585 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 263852 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87883972 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22722991 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 689977 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9488049 # number of nop insts executed -system.cpu.iew.exec_refs 38571182 # number of memory reference insts executed -system.cpu.iew.exec_branches 15118040 # Number of branches executed -system.cpu.iew.exec_stores 15848191 # Number of stores executed -system.cpu.iew.exec_rate 1.925610 # Inst execution rate -system.cpu.iew.wb_sent 87519959 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87118018 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33843453 # num instructions producing a value -system.cpu.iew.wb_consumers 44250497 # num instructions consuming a value -system.cpu.iew.wb_rate 1.908827 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764815 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8632074 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 223532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43575084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.027321 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.870724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22117259 50.76% 50.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6277727 14.41% 65.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2900957 6.66% 71.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1737731 3.99% 75.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1677521 3.85% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1124025 2.58% 82.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1202727 2.76% 85.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795829 1.83% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5741308 13.18% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43575084 # Number of insts commited each cycle -system.cpu.commit.committedInsts 88340672 # Number of instructions committed -system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 34890015 # Number of memory references committed -system.cpu.commit.loads 20276638 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 13754477 # Number of branches committed -system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. -system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. -system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 20276331 22.95% 83.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 14611772 16.54% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 307 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5741308 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 133489180 # The number of ROB reads -system.cpu.rob.rob_writes 195215826 # The number of ROB writes -system.cpu.timesIdled 45373 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 797387 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 79591756 # Number of Instructions Simulated -system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.573421 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.573421 # CPI: Total CPI of All Threads -system.cpu.ipc 1.743921 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.743921 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116327818 # number of integer regfile reads -system.cpu.int_regfile_writes 57658172 # number of integer regfile writes -system.cpu.fp_regfile_reads 255578 # number of floating regfile reads -system.cpu.fp_regfile_writes 240399 # number of floating regfile writes -system.cpu.misc_regfile_reads 38260 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201413 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.948439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33978122 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205509 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.336418 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244590500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.948439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2488 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1533 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70808789 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70808789 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20418812 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20418812 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13559258 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13559258 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33978070 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33978070 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33978070 # number of overall hits -system.cpu.dcache.overall_hits::total 33978070 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269399 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269399 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1054119 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1054119 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1323518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1323518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1323518 # number of overall misses -system.cpu.dcache.overall_misses::total 1323518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19371317500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19371317500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 94432641988 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 94432641988 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113803959488 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113803959488 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113803959488 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113803959488 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20688211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20688211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35301588 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35301588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35301588 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35301588 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072134 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072134 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037492 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037492 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037492 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037492 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71905.677081 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71905.677081 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89584.422620 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89584.422620 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85985.955225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85985.955225 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7415690 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 299 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 82797 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.564719 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 149.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168510 # number of writebacks -system.cpu.dcache.writebacks::total 168510 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207284 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207284 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910725 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910725 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118009 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118009 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118009 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118009 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62115 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62115 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205509 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205509 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205509 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205509 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3617431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3617431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15283982713 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15283982713 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18901414213 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18901414213 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18901414213 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18901414213 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005822 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005822 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58237.647911 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58237.647911 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106587.323828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106587.323828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90457 # number of replacements -system.cpu.icache.tags.tagsinuse 1914.919853 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13608920 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92505 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.115507 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19216549500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1914.919853 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935019 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935019 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1462 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27520357 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27520357 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 13608920 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13608920 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13608920 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13608920 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13608920 # number of overall hits -system.cpu.icache.overall_hits::total 13608920 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105006 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105006 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105006 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105006 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105006 # number of overall misses -system.cpu.icache.overall_misses::total 105006 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2088801499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2088801499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2088801499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2088801499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2088801499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2088801499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13713926 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13713926 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13713926 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13713926 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13713926 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13713926 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007657 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007657 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007657 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007657 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007657 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007657 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19892.210912 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19892.210912 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19892.210912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19892.210912 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 683 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.687500 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 90457 # number of writebacks -system.cpu.icache.writebacks::total 90457 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12500 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12500 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12500 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12500 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12500 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12500 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92506 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 92506 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 92506 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 92506 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 92506 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 92506 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1693618500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1693618500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1693618500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1693618500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1693618500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1693618500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006745 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006745 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006745 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18308.201630 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18308.201630 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 134872 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31840.102351 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 422133 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 167640 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.518092 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5003072000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 716.868966 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1773.767441 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29349.465945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021877 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.054131 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.895675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.971683 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2733 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28770 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1005 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4886720 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4886720 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168510 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168510 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 90457 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 90457 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12581 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12581 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86036 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 86036 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34007 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 34007 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 86036 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46588 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132624 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 86036 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46588 # number of overall hits -system.cpu.l2cache.overall_hits::total 132624 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130815 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130815 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6470 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6470 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28106 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 28106 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6470 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158921 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165391 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6470 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158921 # number of overall misses -system.cpu.l2cache.overall_misses::total 165391 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14933033000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14933033000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 647096000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 647096000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3162742000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3162742000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 647096000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18095775000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18742871000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 647096000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18095775000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18742871000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168510 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168510 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 90457 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 90457 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143396 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143396 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92506 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 92506 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62113 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 62113 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 92506 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205509 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 298015 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 92506 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205509 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 298015 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912264 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912264 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069941 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069941 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452498 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452498 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069941 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773304 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.554975 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069941 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773304 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.554975 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 114153.827925 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 114153.827925 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100014.837713 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100014.837713 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112529.068526 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112529.068526 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 113324.612585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 113324.612585 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115198 # number of writebacks -system.cpu.l2cache.writebacks::total 115198 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130815 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130815 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6470 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6470 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28106 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28106 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6470 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158921 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6470 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158921 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165391 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13624883000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13624883000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 582406000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 582406000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2881682000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2881682000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 582406000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16506565000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17088971000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 582406000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16506565000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17088971000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912264 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912264 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452498 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452498 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.554975 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.554975 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 104153.827925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 104153.827925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90016.383308 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90016.383308 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102529.068526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102529.068526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589885 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291870 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4237 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4237 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62113 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275468 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612431 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11709568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23937216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35646784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134872 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7372672 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 432887 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009788 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 428650 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4237 0.98% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432887 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553909500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138764985 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308272981 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130745 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34575 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115197 # Transaction distribution -system.membus.trans_dist::CleanEvict 15548 # Transaction distribution -system.membus.trans_dist::ReadExReq 130815 # Transaction distribution -system.membus.trans_dist::ReadExResp 130815 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461525 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 461525 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17957568 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165390 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165390 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165390 # Request fanout histogram -system.membus.reqLayer0.occupancy 779827500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 851966000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.7 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 0a31f5d4d..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index 871055fe1..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28067 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 1241902335500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index d9427be27..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,836 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.241902 # Number of seconds simulated -sim_ticks 1241902335500 # Number of ticks simulated -final_tick 1241902335500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 473348 # Simulator instruction rate (inst/s) -host_op_rate 473348 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 321867657 # Simulator tick rate (ticks/s) -host_mem_usage 255296 # Number of bytes of host memory used -host_seconds 3858.43 # Real time elapsed on the host -sim_insts 1826378509 # Number of instructions simulated -sim_ops 1826378509 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126178240 # Number of bytes read from this memory -system.physmem.bytes_read::total 126239872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66092288 # Number of bytes written to this memory -system.physmem.bytes_written::total 66092288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1971535 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1972498 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032692 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032692 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 101600775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 101650402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 53218587 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 53218587 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 53218587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 101600775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 154868990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1972498 # Number of read requests accepted -system.physmem.writeReqs 1032692 # Number of write requests accepted -system.physmem.readBursts 1972498 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1032692 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 126161536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 78336 # Total number of bytes read from write queue -system.physmem.bytesWritten 66090880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126239872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66092288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1224 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119357 # Per bank write bursts -system.physmem.perBankRdBursts::1 114729 # Per bank write bursts -system.physmem.perBankRdBursts::2 116715 # Per bank write bursts -system.physmem.perBankRdBursts::3 118322 # Per bank write bursts -system.physmem.perBankRdBursts::4 118352 # Per bank write bursts -system.physmem.perBankRdBursts::5 118237 # Per bank write bursts -system.physmem.perBankRdBursts::6 120696 # Per bank write bursts -system.physmem.perBankRdBursts::7 125562 # Per bank write bursts -system.physmem.perBankRdBursts::8 127868 # Per bank write bursts -system.physmem.perBankRdBursts::9 130858 # Per bank write bursts -system.physmem.perBankRdBursts::10 129451 # Per bank write bursts -system.physmem.perBankRdBursts::11 131187 # Per bank write bursts -system.physmem.perBankRdBursts::12 126743 # Per bank write bursts -system.physmem.perBankRdBursts::13 125956 # Per bank write bursts -system.physmem.perBankRdBursts::14 123338 # Per bank write bursts -system.physmem.perBankRdBursts::15 123903 # Per bank write bursts -system.physmem.perBankWrBursts::0 62004 # Per bank write bursts -system.physmem.perBankWrBursts::1 62324 # Per bank write bursts -system.physmem.perBankWrBursts::2 61320 # Per bank write bursts -system.physmem.perBankWrBursts::3 62012 # Per bank write bursts -system.physmem.perBankWrBursts::4 62437 # Per bank write bursts -system.physmem.perBankWrBursts::5 63989 # Per bank write bursts -system.physmem.perBankWrBursts::6 65066 # Per bank write bursts -system.physmem.perBankWrBursts::7 66492 # Per bank write bursts -system.physmem.perBankWrBursts::8 66230 # Per bank write bursts -system.physmem.perBankWrBursts::9 66701 # Per bank write bursts -system.physmem.perBankWrBursts::10 66337 # Per bank write bursts -system.physmem.perBankWrBursts::11 66707 # Per bank write bursts -system.physmem.perBankWrBursts::12 65162 # Per bank write bursts -system.physmem.perBankWrBursts::13 65226 # Per bank write bursts -system.physmem.perBankWrBursts::14 65630 # Per bank write bursts -system.physmem.perBankWrBursts::15 65033 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1241902212500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1972498 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1032692 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1834002 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 137262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1848577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.999494 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.158472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.975371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1464855 79.24% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 267102 14.45% 93.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48426 2.62% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20608 1.11% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12613 0.68% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7404 0.40% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5582 0.30% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4649 0.25% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17338 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1848577 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60747 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.448697 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.033030 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 139.766082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60580 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 126 0.21% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 11 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 5 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60747 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60747 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.999523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.968024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.037878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 30790 50.69% 50.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1097 1.81% 52.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26995 44.44% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1834 3.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60747 # Writes before turning the bus around for reads -system.physmem.totQLat 58523135000 # Total ticks spent queuing -system.physmem.totMemAccLat 95484522500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9856370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29687.98 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48437.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 101.59 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 53.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 101.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 53.22 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.21 # Data bus utilization in percentage -system.physmem.busUtilRead 0.79 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing -system.physmem.readRowHits 727297 # Number of row buffer hits during reads -system.physmem.writeRowHits 428065 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.45 # Row buffer hit rate for writes -system.physmem.avgGap 413252.48 # Average gap between requests -system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6395269440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3399162525 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6797065800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2639461680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 75004519200.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 46893448560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2685169920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 246120093660 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 85384513440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 94763106600 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 570117979365 # Total energy per rank (pJ) -system.physmem_0.averagePower 459.068285 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1131989083250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3611832250 # Time in different power states -system.physmem_0.memoryStateTime::REF 31797904000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 369900280750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 222356311250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 74502708250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 539733299000 # Time in different power states -system.physmem_1.actEnergy 6803606040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3616187190 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7277830560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2751075720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 76383156720.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47598512910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2658705600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 254833635780 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 85755552000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 89279622225 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 576994094775 # Total energy per rank (pJ) -system.physmem_1.averagePower 464.605041 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1130512338500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3468880500 # Time in different power states -system.physmem_1.memoryStateTime::REF 32377406000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 348347909000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 223320346000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75543655250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 558844138750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 246965199 # Number of BP lookups -system.cpu.branchPred.condPredicted 186917374 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15586746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168139701 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165606683 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.493504 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18556232 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 106082 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 314 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 63 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 453404968 # DTB read hits -system.cpu.dtb.read_misses 5001226 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 458406194 # DTB read accesses -system.cpu.dtb.write_hits 161377184 # DTB write hits -system.cpu.dtb.write_misses 1709229 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163086413 # DTB write accesses -system.cpu.dtb.data_hits 614782152 # DTB hits -system.cpu.dtb.data_misses 6710455 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 621492607 # DTB accesses -system.cpu.itb.fetch_hits 600133421 # ITB hits -system.cpu.itb.fetch_misses 19 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 600133440 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2483804671 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1826378509 # Number of instructions committed -system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 55133015 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359962 # CPI: cycles per instruction -system.cpu.ipc 0.735315 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction -system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction -system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::MemRead 449492662 24.61% 91.11% # Class of committed instruction -system.cpu.op_class_0::MemWrite 162429751 8.89% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 55 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1826378509 # Class of committed instruction -system.cpu.tickCycles 2082494897 # Number of cycles that the object actually ticked -system.cpu.idleCycles 401309774 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9121955 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.932596 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 602775567 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 66.049989 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 17009517500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.932596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1466 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2515 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1233653477 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1233653477 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 444296125 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 444296125 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158479442 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158479442 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 602775567 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 602775567 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 602775567 # number of overall hits -system.cpu.dcache.overall_hits::total 602775567 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7239086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7239086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2249060 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2249060 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9488146 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9488146 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9488146 # number of overall misses -system.cpu.dcache.overall_misses::total 9488146 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 201399177000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 201399177000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119572112000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119572112000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 320971289000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 320971289000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 320971289000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 320971289000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 451535211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 451535211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 612263713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 612263713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 612263713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 612263713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016032 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016032 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013993 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013993 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015497 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015497 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015497 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015497 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27821.078103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27821.078103 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53165.372200 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53165.372200 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33828.662523 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33828.662523 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3671979 # number of writebacks -system.cpu.dcache.writebacks::total 3671979 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 361730 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 361730 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 362095 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 362095 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 362095 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 362095 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238721 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887330 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887330 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126051 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126051 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126051 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126051 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194152625000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 194152625000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91149337000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91149337000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285301962000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 285301962000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285301962000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 285301962000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016031 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016031 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014905 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014905 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26821.399112 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26821.399112 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48295.389254 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48295.389254 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31262.367699 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31262.367699 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31262.367699 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31262.367699 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 754.212981 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 600132458 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 623190.506750 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 754.212981 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.368268 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.368268 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 879 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1200267805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1200267805 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 600132458 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 600132458 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 600132458 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 600132458 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 600132458 # number of overall hits -system.cpu.icache.overall_hits::total 600132458 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 963 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 963 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.icache.overall_misses::total 963 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 93461000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 93461000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 93461000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 93461000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 93461000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 93461000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 600133421 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 600133421 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 600133421 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 600133421 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 600133421 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 600133421 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 97051.921080 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 97051.921080 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 97051.921080 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 97051.921080 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 97051.921080 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 97051.921080 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3 # number of writebacks -system.cpu.icache.writebacks::total 3 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 92498000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 92498000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 92498000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 92498000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 92498000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 92498000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 96051.921080 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 96051.921080 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 96051.921080 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 96051.921080 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 96051.921080 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 96051.921080 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1940051 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31462.306469 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16275911 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1972819 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.250078 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 89697966000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 7.975185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.025867 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31412.305417 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000243 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001283 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.958627 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.960153 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2816 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7096 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21807 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147964595 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147964595 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3671979 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3671979 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095271 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095271 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6059245 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6059245 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7154516 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7154516 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7154516 # number of overall hits -system.cpu.l2cache.overall_hits::total 7154516 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 792059 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 792059 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 963 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 963 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1179476 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1179476 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1971535 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1972498 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1971535 # number of overall misses -system.cpu.l2cache.overall_misses::total 1972498 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76750433500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 76750433500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 91051000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 91051000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 119656496500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 119656496500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 91051000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 196406930000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 196497981000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 91051000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 196406930000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 196497981000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3671979 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3671979 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887330 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1887330 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 963 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 963 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238721 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7238721 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 963 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9126051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127014 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 963 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9126051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9127014 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419672 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.419672 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162940 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162940 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216034 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216116 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216034 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216116 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96899.894452 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96899.894452 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 94549.325026 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 94549.325026 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101448.860765 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 101448.860765 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 94549.325026 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99621.325515 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 99618.849297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 94549.325026 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99621.325515 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 99618.849297 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032692 # number of writebacks -system.cpu.l2cache.writebacks::total 1032692 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 792059 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 792059 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 963 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 963 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1179476 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1179476 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1971535 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1972498 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1971535 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1972498 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68829843500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68829843500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 81421000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 81421000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 107861736500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 107861736500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 81421000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 176691580000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 176773001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81421000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 176691580000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 176773001000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419672 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419672 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162940 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162940 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216116 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216116 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86899.894452 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86899.894452 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 84549.325026 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 84549.325026 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 91448.860765 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 91448.860765 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18248972 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121958 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1442 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7239684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4704671 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6357335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887330 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887330 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 963 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238721 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1929 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374057 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27375986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819073920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819135744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1940051 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66092288 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11067065 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011414 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11065623 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1442 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11067065 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12796468000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1444500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689076500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3911349 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1938851 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1180439 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032692 # Transaction distribution -system.membus.trans_dist::CleanEvict 906159 # Transaction distribution -system.membus.trans_dist::ReadExReq 792059 # Transaction distribution -system.membus.trans_dist::ReadExResp 792059 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1180439 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883847 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5883847 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192332160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192332160 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1972498 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1972498 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1972498 # Request fanout histogram -system.membus.reqLayer0.occupancy 8507556000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10783034500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index 1d1d7a36d..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 03b7f79ab..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28058 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 684199968000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index 6249c394a..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1119 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.684200 # Number of seconds simulated -sim_ticks 684199968000 # Number of ticks simulated -final_tick 684199968000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295566 # Simulator instruction rate (inst/s) -host_op_rate 295566 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116486932 # Simulator tick rate (ticks/s) -host_mem_usage 257340 # Number of bytes of host memory used -host_seconds 5873.62 # Real time elapsed on the host -sim_insts 1736043781 # Number of instructions simulated -sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126674880 # Number of bytes read from this memory -system.physmem.bytes_read::total 126735616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66206592 # Number of bytes written to this memory -system.physmem.bytes_written::total 66206592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1979295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1980244 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1034478 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1034478 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 185143066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 185231836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96764974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96764974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96764974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 185143066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 281996809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1980244 # Number of read requests accepted -system.physmem.writeReqs 1034478 # Number of write requests accepted -system.physmem.readBursts 1980244 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1034478 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 126652288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83328 # Total number of bytes read from write queue -system.physmem.bytesWritten 66205120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126735616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66206592 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119682 # Per bank write bursts -system.physmem.perBankRdBursts::1 115093 # Per bank write bursts -system.physmem.perBankRdBursts::2 117079 # Per bank write bursts -system.physmem.perBankRdBursts::3 118658 # Per bank write bursts -system.physmem.perBankRdBursts::4 118799 # Per bank write bursts -system.physmem.perBankRdBursts::5 118596 # Per bank write bursts -system.physmem.perBankRdBursts::6 121104 # Per bank write bursts -system.physmem.perBankRdBursts::7 126057 # Per bank write bursts -system.physmem.perBankRdBursts::8 128556 # Per bank write bursts -system.physmem.perBankRdBursts::9 131368 # Per bank write bursts -system.physmem.perBankRdBursts::10 130043 # Per bank write bursts -system.physmem.perBankRdBursts::11 131744 # Per bank write bursts -system.physmem.perBankRdBursts::12 127398 # Per bank write bursts -system.physmem.perBankRdBursts::13 126519 # Per bank write bursts -system.physmem.perBankRdBursts::14 123764 # Per bank write bursts -system.physmem.perBankRdBursts::15 124482 # Per bank write bursts -system.physmem.perBankWrBursts::0 62070 # Per bank write bursts -system.physmem.perBankWrBursts::1 62408 # Per bank write bursts -system.physmem.perBankWrBursts::2 61409 # Per bank write bursts -system.physmem.perBankWrBursts::3 62103 # Per bank write bursts -system.physmem.perBankWrBursts::4 62566 # Per bank write bursts -system.physmem.perBankWrBursts::5 64096 # Per bank write bursts -system.physmem.perBankWrBursts::6 65160 # Per bank write bursts -system.physmem.perBankWrBursts::7 66609 # Per bank write bursts -system.physmem.perBankWrBursts::8 66404 # Per bank write bursts -system.physmem.perBankWrBursts::9 66820 # Per bank write bursts -system.physmem.perBankWrBursts::10 66475 # Per bank write bursts -system.physmem.perBankWrBursts::11 66816 # Per bank write bursts -system.physmem.perBankWrBursts::12 65322 # Per bank write bursts -system.physmem.perBankWrBursts::13 65320 # Per bank write bursts -system.physmem.perBankWrBursts::14 65711 # Per bank write bursts -system.physmem.perBankWrBursts::15 65166 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 684199865500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1980244 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1034478 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1615224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 253124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 75634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 58148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 64398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1786108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.975625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.936522 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 138.228671 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1386417 77.62% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 276583 15.49% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52891 2.96% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20920 1.17% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12358 0.69% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6524 0.37% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5164 0.29% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3751 0.21% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21500 1.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1786108 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.352277 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.914892 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.448273 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60991 99.72% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 137 0.22% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 7 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61165 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61165 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.912532 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.877578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.101156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 34708 56.74% 56.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1369 2.24% 58.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21665 35.42% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2721 4.45% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 576 0.94% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 109 0.18% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61165 # Writes before turning the bus around for reads -system.physmem.totQLat 56581400750 # Total ticks spent queuing -system.physmem.totMemAccLat 93686563250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9894710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28591.74 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47341.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 185.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 185.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.20 # Data bus utilization in percentage -system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing -system.physmem.readRowHits 796002 # Number of row buffer hits during reads -system.physmem.writeRowHits 431282 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.69 # Row buffer hit rate for writes -system.physmem.avgGap 226952.89 # Average gap between requests -system.physmem.pageHitRate 40.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6177735060 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3283540260 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6819185520 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2643517620 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 44816475600.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 37044798750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1443275040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 170396037690 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 31359460320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 36616359660 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 340610162070 # Total energy per rank (pJ) -system.physmem_0.averagePower 497.822532 # Core power per rank (mW) -system.physmem_0.totalIdleTime 599184631500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1534958250 # Time in different power states -system.physmem_0.memoryStateTime::REF 18981984000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 143840379000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 81664935250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 64497738500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 373679973000 # Time in different power states -system.physmem_1.actEnergy 6575111760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3494739600 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7310460360 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2756337480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 45376412640.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 37526229300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1410684000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 175219175340 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 30265452000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 34407180735 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 344356241235 # Total energy per rank (pJ) -system.physmem_1.averagePower 503.297652 # Core power per rank (mW) -system.physmem_1.totalIdleTime 598199672750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1433387500 # Time in different power states -system.physmem_1.memoryStateTime::REF 19217296000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 135130926250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 78815070250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 65349556500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 384253731500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 409436754 # Number of BP lookups -system.cpu.branchPred.condPredicted 318234486 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15963820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282367334 # Number of BTB lookups -system.cpu.branchPred.BTBHits 278623697 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.674196 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26172484 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 12628 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1002 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 11626 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 645003218 # DTB read hits -system.cpu.dtb.read_misses 12159343 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 657162561 # DTB read accesses -system.cpu.dtb.write_hits 218108239 # DTB write hits -system.cpu.dtb.write_misses 7507876 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225616115 # DTB write accesses -system.cpu.dtb.data_hits 863111457 # DTB hits -system.cpu.dtb.data_misses 19667219 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 882778676 # DTB accesses -system.cpu.itb.fetch_hits 420694791 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 420694828 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1368399937 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 431834940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3410573803 # Number of instructions fetch has processed -system.cpu.fetch.Branches 409436754 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 304797183 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 913784247 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45380414 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1708 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 420694791 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8284167 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1368311169 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.492543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.138689 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 743223403 54.32% 54.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47685517 3.48% 57.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24183643 1.77% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45097399 3.30% 62.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142825430 10.44% 73.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 65953370 4.82% 78.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43585313 3.19% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29408397 2.15% 83.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226348697 16.54% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1368311169 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299208 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.492381 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 353769261 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 432754726 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 524267891 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34829792 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22689499 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62032551 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256358950 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22689499 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 372017301 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 224454621 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9976 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 537214927 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211924845 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3173979679 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1947204 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21862090 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 161736150 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 34961727 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2371970000 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4117940809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4117804241 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136567 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 995767037 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 144 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 143 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99713027 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 717292360 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272467386 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90468830 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58360421 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2884387847 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620166340 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1550282 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1148344190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 502911540 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1368311169 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.914891 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.143845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 564702258 41.27% 41.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169734991 12.40% 53.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158008570 11.55% 65.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149164272 10.90% 76.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126054849 9.21% 85.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84104604 6.15% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68048276 4.97% 96.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34057471 2.49% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14435878 1.06% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1368311169 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13157745 35.86% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18955559 51.65% 87.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4574949 12.47% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 21 0.00% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 8342 0.02% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1716973131 65.53% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 895059 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 21 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671606942 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230625627 8.80% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 214 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 65011 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620166340 # Type of FU issued -system.cpu.iq.rate 1.914766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36696616 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014005 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6644950011 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4031627633 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2518705843 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1940736 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1246935 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 885827 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655894066 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 968890 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69399237 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 272696697 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 372755 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 144718 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 111738884 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 276 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6347426 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22689499 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 153700665 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24607409 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3035418130 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6594075 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 717292360 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272467386 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 793020 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 24069505 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 144718 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10634250 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8701065 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19335315 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2575033857 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 657162570 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45132483 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151030158 # number of nop insts executed -system.cpu.iew.exec_refs 882778753 # number of memory reference insts executed -system.cpu.iew.exec_branches 315511040 # Number of branches executed -system.cpu.iew.exec_stores 225616183 # Number of stores executed -system.cpu.iew.exec_rate 1.881785 # Inst execution rate -system.cpu.iew.wb_sent 2549403036 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2519591670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1487461563 # num instructions producing a value -system.cpu.iew.wb_consumers 1918503373 # num instructions consuming a value -system.cpu.iew.wb_rate 1.841268 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775324 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 998993468 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15963112 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1230277663 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.479162 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.528603 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 741569515 60.28% 60.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159647987 12.98% 73.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79500884 6.46% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52016561 4.23% 83.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28471103 2.31% 86.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19445294 1.58% 87.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19999560 1.63% 89.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23041626 1.87% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106585133 8.66% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1230277663 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1819780126 # Number of instructions committed -system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 605324165 # Number of memory references committed -system.cpu.commit.loads 444595663 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 214632552 # Number of branches committed -system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. -system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 444595584 24.43% 91.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 160728448 8.83% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 54 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106585133 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3856686924 # The number of ROB reads -system.cpu.rob.rob_writes 5775715040 # The number of ROB writes -system.cpu.timesIdled 709 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 88768 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1736043781 # Number of Instructions Simulated -system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.788229 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.788229 # CPI: Total CPI of All Threads -system.cpu.ipc 1.268667 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.268667 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3463738117 # number of integer regfile reads -system.cpu.int_regfile_writes 2019389646 # number of integer regfile writes -system.cpu.fp_regfile_reads 39803 # number of floating regfile reads -system.cpu.fp_regfile_writes 598 # number of floating regfile writes -system.cpu.misc_regfile_reads 25 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9207265 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.531672 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 712311191 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9211361 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.329636 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5174346500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.531672 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 666 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2980 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1470218079 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1470218079 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 556814159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 556814159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155497028 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155497028 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 712311187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 712311187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 712311187 # number of overall hits -system.cpu.dcache.overall_hits::total 712311187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12960693 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12960693 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5231474 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5231474 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18192167 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18192167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18192167 # number of overall misses -system.cpu.dcache.overall_misses::total 18192167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 452018170000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 452018170000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 345871511780 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 345871511780 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 79500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 79500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 797889681780 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 797889681780 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 797889681780 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 797889681780 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 569774852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 569774852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 730503354 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 730503354 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 730503354 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 730503354 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022747 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022747 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032549 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032549 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024904 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024904 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024904 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024904 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34876.080315 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34876.080315 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66113.587066 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66113.587066 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 79500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 79500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 43858.968631 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 43858.968631 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16718017 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10716708 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1109373 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 69036 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.069789 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 155.233617 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3713171 # number of writebacks -system.cpu.dcache.writebacks::total 3713171 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628505 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5628505 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3352302 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3352302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8980807 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8980807 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8980807 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8980807 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332188 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7332188 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879172 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879172 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9211360 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9211360 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9211360 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9211360 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194855974500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 194855974500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91510360097 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91510360097 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 78500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 78500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286366334597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 286366334597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286366334597 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 286366334597 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26575.419847 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26575.419847 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48697.170933 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48697.170933 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 78500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 78500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31088.388099 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31088.388099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31088.388099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31088.388099 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 753.632230 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 420693280 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 443301.664910 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 753.632230 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367984 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367984 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 841390531 # Number of tag accesses -system.cpu.icache.tags.data_accesses 841390531 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 420693280 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420693280 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420693280 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420693280 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420693280 # number of overall hits -system.cpu.icache.overall_hits::total 420693280 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1511 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1511 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1511 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1511 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1511 # number of overall misses -system.cpu.icache.overall_misses::total 1511 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 138965499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 138965499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 138965499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 138965499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 138965499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 138965499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420694791 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420694791 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420694791 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420694791 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420694791 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420694791 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91969.225017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 91969.225017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 91969.225017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 91969.225017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 91969.225017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 91969.225017 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 115.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 562 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 562 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 562 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 562 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 562 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 562 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 949 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 949 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 949 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 949 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 93919999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 93919999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 93919999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 93919999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 93919999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 93919999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98967.332982 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98967.332982 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98967.332982 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98967.332982 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98967.332982 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98967.332982 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1947802 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32040.149631 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16438766 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1980570 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.300018 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28106474000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8.660797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.112733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32006.376101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000264 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000766 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.976757 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.977788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3407 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 643 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13986 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 14548 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149337178 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149337178 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3713171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3713171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095576 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095576 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6136490 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6136490 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7232066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7232066 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7232066 # number of overall hits -system.cpu.l2cache.overall_hits::total 7232066 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 783612 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 783612 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 949 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 949 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1195683 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1195683 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 949 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1979295 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1980244 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 949 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1979295 # number of overall misses -system.cpu.l2cache.overall_misses::total 1980244 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76631269000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 76631269000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 92491000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 92491000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 118466842500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 118466842500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92491000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 195098111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 195190602500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92491000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 195098111500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 195190602500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3713171 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3713171 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1879188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 949 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 949 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332173 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7332173 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 949 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9211361 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9212310 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 949 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9211361 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9212310 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.416995 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.416995 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.163073 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.163073 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214875 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214956 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214875 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214956 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97792.362802 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97792.362802 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 97461.538462 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 97461.538462 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99078.804750 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99078.804750 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 97461.538462 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98569.496462 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98568.965491 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 97461.538462 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98569.496462 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98568.965491 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1034478 # number of writebacks -system.cpu.l2cache.writebacks::total 1034478 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 783612 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 783612 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1195683 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1195683 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1979295 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1980244 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1979295 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1980244 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68795149000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68795149000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 83001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 83001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 106510012500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 106510012500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 83001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 175305161500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 175388162500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 83001000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 175305161500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 175388162500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.416995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.416995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.163073 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.163073 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214956 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214956 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87792.362802 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87792.362802 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 87461.538462 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 87461.538462 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89078.804750 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89078.804750 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18419576 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207266 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1448 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1448 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7333122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4747649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6407418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332173 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27631886 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827170048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827230848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1947802 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66206592 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11160112 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11158664 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1448 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11160112 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12922960000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1423500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13817041500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3926838 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1946594 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1196632 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1034478 # Transaction distribution -system.membus.trans_dist::CleanEvict 912116 # Transaction distribution -system.membus.trans_dist::ReadExReq 783612 # Transaction distribution -system.membus.trans_dist::ReadExResp 783612 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1196632 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5907082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5907082 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192942208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192942208 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1980244 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1980244 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1980244 # Request fanout histogram -system.membus.reqLayer0.occupancy 8533086500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 10770167500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 346da75e3..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 96524c915..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index d6f6a9638..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4310 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 913189263000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index 9f7e15391..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.913189 # Number of seconds simulated -sim_ticks 913189263000 # Number of ticks simulated -final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3052391 # Simulator instruction rate (inst/s) -host_op_rate 3052390 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1531729085 # Simulator tick rate (ticks/s) -host_mem_usage 242484 # Number of bytes of host memory used -host_seconds 596.18 # Real time elapsed on the host -sim_insts 1819780127 # Number of instructions simulated -sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory -system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory -system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory -system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.itb.fetch_hits 1826378509 # ITB hits -system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1826378527 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 913189263000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1826378527 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1819780127 # Number of instructions committed -system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses -system.cpu.num_func_calls 33534877 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls -system.cpu.num_int_insts 1725565901 # number of integer instructions -system.cpu.num_fp_insts 805526 # number of float instructions -system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read -system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written -system.cpu.num_fp_register_reads 357 # number of times the floating registers were read -system.cpu.num_fp_register_writes 345 # number of times the floating registers were written -system.cpu.num_mem_refs 611922547 # number of memory refs -system.cpu.num_load_insts 449492741 # Number of load instructions -system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1826378527 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 214632552 # Number of branches fetched -system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1826378509 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution -system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution -system.membus.trans_dist::WriteReq 160728502 # Transaction distribution -system.membus.trans_dist::WriteResp 160728502 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2431702674 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2431702674 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index b0859ad68..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 96524c915..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index eae87e351..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4312 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2636719559500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 6af37cfb2..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,566 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.639614 # Number of seconds simulated -sim_ticks 2639613874500 # Number of ticks simulated -final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2013574 # Simulator instruction rate (inst/s) -host_op_rate 2013574 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2920714569 # Simulator tick rate (ticks/s) -host_mem_usage 253500 # Number of bytes of host memory used -host_seconds 903.76 # Real time elapsed on the host -sim_insts 1819780127 # Number of instructions simulated -sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126106432 # Number of bytes read from this memory -system.physmem.bytes_read::total 126157760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66087296 # Number of bytes written to this memory -system.physmem.bytes_written::total 66087296 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1970413 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1971215 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032614 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032614 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47774575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47794021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25036729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25036729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25036729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47774575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72830749 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.itb.fetch_hits 1826378510 # ITB hits -system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1826378528 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5279227749 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1819780127 # Number of instructions committed -system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses -system.cpu.num_func_calls 33534877 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls -system.cpu.num_int_insts 1725565901 # number of integer instructions -system.cpu.num_fp_insts 805526 # number of float instructions -system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read -system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written -system.cpu.num_fp_register_reads 357 # number of times the floating registers were read -system.cpu.num_fp_register_writes 345 # number of times the floating registers were written -system.cpu.num_mem_refs 611922547 # number of memory refs -system.cpu.num_load_insts 449492741 # Number of load instructions -system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5279227749 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 214632552 # Number of branches fetched -system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1826378509 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.303630 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41048093500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.303630 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2646 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits -system.cpu.dcache.overall_hits::total 596212431 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses -system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152711735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152711735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64261460000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64261460000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216973195000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216973195000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216973195000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216973195000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21144.140311 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21144.140311 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34013.009972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34013.009972 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23812.503196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23812.503196 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3664823 # number of writebacks -system.cpu.dcache.writebacks::total 3664823 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145489321000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 145489321000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62372140000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62372140000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207861461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 207861461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207861461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 207861461000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20144.140311 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20144.140311 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33013.009972 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33013.009972 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.633318 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.633318 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299137 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299137 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits -system.cpu.icache.overall_hits::total 1826377708 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50541500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50541500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50541500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50541500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50541500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50541500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63019.326683 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63019.326683 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63019.326683 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63019.326683 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49739500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49739500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49739500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49739500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49739500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49739500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62019.326683 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62019.326683 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938767 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31260.683710 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16248398 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1971535 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.241496 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 217871689000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8.109026 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.419408 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31214.155276 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000247 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001172 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.952580 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.954000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 664 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27794 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147732935 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147732935 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3664823 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3664823 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095314 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095314 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046007 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6046007 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7141321 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7141321 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7141321 # number of overall hits -system.cpu.l2cache.overall_hits::total 7141321 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 794006 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 794006 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176407 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1176407 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1970413 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1971215 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1970413 # number of overall misses -system.cpu.l2cache.overall_misses::total 1971215 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48037363000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48037363000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48529000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 48529000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71172626500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71172626500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48529000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 119209989500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 119258518500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 48529000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 119209989500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 119258518500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3664823 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3664823 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222414 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7222414 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420260 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.420260 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162883 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162883 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216250 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216319 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216250 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216319 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60509.975062 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60509.975062 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.002550 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.002550 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.005580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.005580 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032614 # number of writebacks -system.cpu.l2cache.writebacks::total 1032614 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 794006 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 794006 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176407 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176407 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1970413 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1971215 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1970413 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1971215 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40097303000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40097303000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40509000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40509000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59408556500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59408556500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40509000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99505859500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 99546368500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40509000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99505859500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99546368500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420260 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420260 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162883 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162883 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216319 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216319 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50509.975062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50509.975062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.002550 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.002550 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1292 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1292 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4697437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6348968 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 817699648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 817751040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938767 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66087296 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11051303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000117 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11050011 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1292 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11051303 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12774911500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3908932 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1937717 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1177209 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032614 # Transaction distribution -system.membus.trans_dist::CleanEvict 905103 # Transaction distribution -system.membus.trans_dist::ReadExReq 794006 # Transaction distribution -system.membus.trans_dist::ReadExResp 794006 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1177209 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5880147 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5880147 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192245056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192245056 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1971215 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1971215 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1971215 # Request fanout histogram -system.membus.reqLayer0.occupancy 8039396000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9856075000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 35828777f..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index 4b089cf00..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:43 -gem5 executing on e108600-lin, pid 28042 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing - -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 53437621500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 40657583a..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,795 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.053438 # Number of seconds simulated -sim_ticks 53437621500 # Number of ticks simulated -final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 468238 # Simulator instruction rate (inst/s) -host_op_rate 468238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272260061 # Simulator tick rate (ticks/s) -host_mem_usage 257916 # Number of bytes of host memory used -host_seconds 196.27 # Real time elapsed on the host -sim_insts 91903089 # Number of instructions simulated -sim_ops 91903089 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory -system.physmem.bytes_read::total 340608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202880 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5322 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 468 # Per bank write bursts -system.physmem.perBankRdBursts::1 295 # Per bank write bursts -system.physmem.perBankRdBursts::2 308 # Per bank write bursts -system.physmem.perBankRdBursts::3 524 # Per bank write bursts -system.physmem.perBankRdBursts::4 224 # Per bank write bursts -system.physmem.perBankRdBursts::5 238 # Per bank write bursts -system.physmem.perBankRdBursts::6 222 # Per bank write bursts -system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 254 # Per bank write bursts -system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 254 # Per bank write bursts -system.physmem.perBankRdBursts::11 261 # Per bank write bursts -system.physmem.perBankRdBursts::12 410 # Per bank write bursts -system.physmem.perBankRdBursts::13 344 # Per bank write bursts -system.physmem.perBankRdBursts::14 501 # Per bank write bursts -system.physmem.perBankRdBursts::15 448 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53437285500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5322 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation -system.physmem.totQLat 132267250 # Total ticks spent queuing -system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4338 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10040827.79 # Average gap between requests -system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.626273 # Core power per rank (mW) -system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states -system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states -system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ) -system.physmem_1.averagePower 251.716611 # Core power per rank (mW) -system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states -system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450652 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2073 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20415218 # DTB read hits -system.cpu.dtb.read_misses 43383 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20458601 # DTB read accesses -system.cpu.dtb.write_hits 6579912 # DTB write hits -system.cpu.dtb.write_misses 276 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580188 # DTB write accesses -system.cpu.dtb.data_hits 26995130 # DTB hits -system.cpu.dtb.data_misses 43659 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27038789 # DTB accesses -system.cpu.itb.fetch_hits 22968644 # ITB hits -system.cpu.itb.fetch_misses 90 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968734 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106875243 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903089 # Number of instructions committed -system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.162912 # CPI: cycles per instruction -system.cpu.ipc 0.859910 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction -system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction -system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction -system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::MemRead 19433628 21.15% 92.31% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6424338 6.99% 99.30% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 76788 0.08% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits -system.cpu.dcache.overall_hits::total 26572187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses -system.cpu.dcache.overall_misses::total 3415 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1743 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2231 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.239495 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952813 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.956601 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.239495 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953118 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953118 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952813 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952813 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952813 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952813 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952813 # number of overall hits -system.cpu.icache.overall_hits::total 22952813 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses -system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 456439000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 456439000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 456439000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 456439000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 456439000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 456439000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968644 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968644 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968644 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968644 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28831.975238 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13865 # number of writebacks -system.cpu.icache.writebacks::total 13865 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15831 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15831 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15831 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 440609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 440609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440609000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 440609000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3574.446973 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.836656 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.610316 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064143 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044941 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109083 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13865 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12660 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 12660 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12660 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 12739 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12660 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 12739 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1717 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1717 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3170 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3170 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 435 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 435 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2152 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5322 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses -system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163078000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 163078000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 283932500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 283932500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 56594000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 56594000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 283932500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 503604500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 283932500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219672000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 503604500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 13865 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15830 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15830 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 488 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 488 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15830 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2231 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 18061 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15830 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2231 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 18061 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985083 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985083 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.891393 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.891393 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200253 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964590 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.294668 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1717 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1717 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3170 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3170 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 435 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 435 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2152 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5322 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 145908000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 145908000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252232500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252232500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 52244000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 52244000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252232500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 198152000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 450384500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252232500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 198152000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 450384500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.891393 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.891393 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 488 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45525 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4619 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50144 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1900480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2050112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 18061 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 18061 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18061 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 30013500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23745000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3605 # Transaction distribution -system.membus.trans_dist::ReadExReq 1717 # Transaction distribution -system.membus.trans_dist::ReadExResp 1717 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3605 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10644 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10644 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5322 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5322 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index f4beb67d4..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index e5a3bf839..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28064 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/o3-timing - -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 21954917500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out deleted file mode 100644 index 98777e0af..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index bb93c695e..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1074 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.021955 # Number of seconds simulated -sim_ticks 21954917500 # Number of ticks simulated -final_tick 21954917500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 353144 # Simulator instruction rate (inst/s) -host_op_rate 353144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92103562 # Simulator tick rate (ticks/s) -host_mem_usage 259964 # Number of bytes of host memory used -host_seconds 238.37 # Real time elapsed on the host -sim_insts 84179709 # Number of instructions simulated -sim_ops 84179709 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8923012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6311115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15234127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8923012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8923012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8923012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6311115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15234127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5226 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5226 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 469 # Per bank write bursts -system.physmem.perBankRdBursts::1 292 # Per bank write bursts -system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 523 # Per bank write bursts -system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 223 # Per bank write bursts -system.physmem.perBankRdBursts::6 218 # Per bank write bursts -system.physmem.perBankRdBursts::7 288 # Per bank write bursts -system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts -system.physmem.perBankRdBursts::10 249 # Per bank write bursts -system.physmem.perBankRdBursts::11 251 # Per bank write bursts -system.physmem.perBankRdBursts::12 395 # Per bank write bursts -system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 492 # Per bank write bursts -system.physmem.perBankRdBursts::15 449 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21954815500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5226 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.932636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.340491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 360.649518 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 261 30.31% 30.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 173 20.09% 50.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 10.80% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.62% 67.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37 4.30% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 30 3.48% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 47 5.46% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 3.83% 84.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 130 15.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 861 # Bytes accessed per row activation -system.physmem.totQLat 128746000 # Total ticks spent queuing -system.physmem.totMemAccLat 226733500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26130000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24635.67 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43385.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.23 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4356 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4201074.53 # Average gap between requests -system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3034500 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1593900 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18099900 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 118625520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 48811380 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6176640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 312556080 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 154176960 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 5001436845 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 5664547785 # Total energy per rank (pJ) -system.physmem_0.averagePower 258.008156 # Core power per rank (mW) -system.physmem_0.totalIdleTime 21831003750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 11536500 # Time in different power states -system.physmem_0.memoryStateTime::REF 50426000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 20744771750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 401491250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 61308000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 685384000 # Time in different power states -system.physmem_1.actEnergy 3177300 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1673595 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19213740 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 106332720.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46621440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 5256960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 301076850 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 131936160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 5018107080 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 5633395845 # Total energy per rank (pJ) -system.physmem_1.averagePower 256.589251 # Core power per rank (mW) -system.physmem_1.totalIdleTime 21838957750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 9258500 # Time in different power states -system.physmem_1.memoryStateTime::REF 45178000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 20835144000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 343577000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 61468500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 660291500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16102182 # Number of BP lookups -system.cpu.branchPred.condPredicted 11688137 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 930988 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8963257 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7508303 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.767575 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1594537 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 29363 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3639 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24064359 # DTB read hits -system.cpu.dtb.read_misses 206311 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 24270670 # DTB read accesses -system.cpu.dtb.write_hits 7168837 # DTB write hits -system.cpu.dtb.write_misses 1192 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7170029 # DTB write accesses -system.cpu.dtb.data_hits 31233196 # DTB hits -system.cpu.dtb.data_misses 207503 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 31440699 # DTB accesses -system.cpu.itb.fetch_hits 15932695 # ITB hits -system.cpu.itb.fetch_misses 79 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15932774 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43909836 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16643979 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137979397 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16102182 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9128564 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26000321 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1939876 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2307 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15932695 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367713 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43616730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.163451 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433365 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19436456 44.56% 44.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2618537 6.00% 50.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1330059 3.05% 53.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1934096 4.43% 58.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3001834 6.88% 64.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1292274 2.96% 67.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1355703 3.11% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 886638 2.03% 73.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11761133 26.96% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43616730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.366710 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.142335 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12867029 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8250930 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19434015 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2106147 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 958609 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2654207 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11848 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132149793 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49699 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 958609 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13986200 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4658485 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10631 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20305693 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3697112 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128776944 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2027533 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1361651 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 79521 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94599397 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167333600 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159779432 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7554167 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26172036 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 950 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8272242 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26904484 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8704450 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3461355 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1614052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111855473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1918 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99762246 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119439 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27677681 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21095832 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1529 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43616730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.287247 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099564 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11270720 25.84% 25.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7659760 17.56% 43.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7470187 17.13% 60.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5700495 13.07% 73.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4466514 10.24% 83.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2981046 6.83% 90.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2041941 4.68% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1170841 2.68% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 855226 1.96% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43616730 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 484010 20.07% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1012503 41.99% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 682717 28.32% 92.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160804 6.67% 99.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 21053 0.87% 99.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 2406 0.10% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60662676 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2847523 2.85% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2443321 2.45% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314198 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24115562 24.17% 91.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7190219 7.21% 99.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 739060 0.74% 99.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 78236 0.08% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99762246 # Type of FU issued -system.cpu.iq.rate 2.271979 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2411149 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024169 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229977416 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129921960 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89757276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15694394 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9653681 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7189481 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93785924 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8387464 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1923320 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6908286 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11342 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40947 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2203347 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42864 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1503 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 958609 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3613912 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 479107 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122779790 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241415 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26904484 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8704450 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1918 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38391 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 434865 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40947 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502384 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034333 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98436741 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24271214 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1325505 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10922399 # number of nop insts executed -system.cpu.iew.exec_refs 31441282 # number of memory reference insts executed -system.cpu.iew.exec_branches 12471732 # Number of branches executed -system.cpu.iew.exec_stores 7170068 # Number of stores executed -system.cpu.iew.exec_rate 2.241792 # Inst execution rate -system.cpu.iew.wb_sent 97645487 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96946757 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66976137 # num instructions producing a value -system.cpu.iew.wb_consumers 94960144 # num instructions consuming a value -system.cpu.iew.wb_rate 2.207860 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705308 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30878503 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 919659 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39122931 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.349084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.919383 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14724541 37.64% 37.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8532800 21.81% 59.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880104 9.92% 69.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1909784 4.88% 74.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1376640 3.52% 77.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1034511 2.64% 80.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692868 1.77% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 729092 1.86% 84.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6242591 15.96% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39122931 # Number of insts commited each cycle -system.cpu.commit.committedInsts 91903055 # Number of instructions committed -system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 26497301 # Number of memory references committed -system.cpu.commit.loads 19996198 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 10240685 # Number of branches committed -system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. -system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. -system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 51001453 55.49% 63.90% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 19433618 21.15% 92.31% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6424318 6.99% 99.30% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 76785 0.08% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6242591 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155660858 # The number of ROB reads -system.cpu.rob.rob_writes 250112359 # The number of ROB writes -system.cpu.timesIdled 4774 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 293106 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 84179709 # Number of Instructions Simulated -system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.521620 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.521620 # CPI: Total CPI of All Threads -system.cpu.ipc 1.917104 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.917104 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133010551 # number of integer regfile reads -system.cpu.int_regfile_writes 72904644 # number of integer regfile writes -system.cpu.fp_regfile_reads 6263409 # number of floating regfile reads -system.cpu.fp_regfile_writes 6178123 # number of floating regfile writes -system.cpu.misc_regfile_reads 719113 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.034872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28588531 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12734.312249 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.034872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355721 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355721 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57198427 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57198427 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22095438 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22095438 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492623 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492623 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28588061 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28588061 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28588061 # number of overall hits -system.cpu.dcache.overall_hits::total 28588061 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1079 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1079 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8480 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8480 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9559 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9559 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9559 # number of overall misses -system.cpu.dcache.overall_misses::total 9559 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87318000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87318000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 649645257 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 649645257 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 106000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 106000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 736963257 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 736963257 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 736963257 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 736963257 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22096517 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22096517 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28597620 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28597620 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28597620 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28597620 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80924.930491 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 80924.930491 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76609.110495 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76609.110495 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 106000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 106000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77096.271263 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77096.271263 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 43101 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 174 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 350 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 123.145714 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 108 # number of writebacks -system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6751 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6751 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7315 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7315 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7315 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7315 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1729 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47711000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47711000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177283495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 177283495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224994495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 224994495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224994495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 224994495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92642.718447 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92642.718447 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102535.277617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102535.277617 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 105000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 105000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 9511 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.395362 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15918262 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11449 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1390.362652 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.395362 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781443 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781443 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31876835 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31876835 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 15918262 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15918262 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15918262 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15918262 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15918262 # number of overall hits -system.cpu.icache.overall_hits::total 15918262 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14431 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14431 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14431 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14431 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14431 # number of overall misses -system.cpu.icache.overall_misses::total 14431 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 508617000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 508617000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 508617000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 508617000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 508617000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 508617000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15932693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15932693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15932693 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15932693 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15932693 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15932693 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000906 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000906 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000906 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000906 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35244.750884 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35244.750884 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35244.750884 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35244.750884 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35244.750884 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35244.750884 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 80.833333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 9511 # number of writebacks -system.cpu.icache.writebacks::total 9511 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2981 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2981 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2981 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2981 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2981 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2981 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11450 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11450 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11450 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11450 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11450 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11450 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 378748000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 378748000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 378748000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 378748000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 378748000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 378748000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000719 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000719 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33078.427948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33078.427948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33078.427948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33078.427948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33078.427948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33078.427948 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3489.228607 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 18138 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5226 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.470723 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2006.844021 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.384585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061244 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.045239 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106483 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5226 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1370 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3517 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.159485 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 192138 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 192138 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 9511 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 9511 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8389 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8389 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 54 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 54 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8389 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8469 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8389 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits -system.cpu.l2cache.overall_hits::total 8469 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1703 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1703 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3061 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3061 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 462 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 462 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3061 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5226 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3061 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses -system.cpu.l2cache.overall_misses::total 5226 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 174274000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 174274000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 273178000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 273178000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 46458500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 46458500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 273178000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 220732500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 493910500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 273178000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 220732500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 493910500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 9511 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 9511 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1729 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1729 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11450 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 11450 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 516 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 516 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11450 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13695 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11450 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13695 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984962 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.984962 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267336 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267336 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.895349 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.895349 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267336 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.381599 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267336 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.381599 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102333.529066 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102333.529066 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89244.691277 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89244.691277 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100559.523810 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100559.523810 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89244.691277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101954.965358 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94510.237275 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89244.691277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101954.965358 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94510.237275 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3061 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3061 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 462 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 462 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3061 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5226 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3061 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5226 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 157244000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157244000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 242568000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 242568000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41838500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41838500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 242568000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 199082500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 441650500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 242568000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 199082500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 441650500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267336 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.895349 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.895349 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.381599 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.381599 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92333.529066 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92333.529066 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79244.691277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79244.691277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90559.523810 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90559.523810 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 23364 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9669 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 11965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9511 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 37058 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1492032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 13695 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13695 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13695 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21301000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17173500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5226 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1703 # Transaction distribution -system.membus.trans_dist::ReadExResp 1703 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3523 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5226 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5226 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5226 # Request fanout histogram -system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27424000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |